JP5826894B2 - 絶縁分離された集積回路装置 - Google Patents
絶縁分離された集積回路装置 Download PDFInfo
- Publication number
- JP5826894B2 JP5826894B2 JP2014114788A JP2014114788A JP5826894B2 JP 5826894 B2 JP5826894 B2 JP 5826894B2 JP 2014114788 A JP2014114788 A JP 2014114788A JP 2014114788 A JP2014114788 A JP 2014114788A JP 5826894 B2 JP5826894 B2 JP 5826894B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- isolation
- substrate
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000002955 isolation Methods 0.000 claims description 355
- 239000000758 substrate Substances 0.000 claims description 130
- 238000000926 separation method Methods 0.000 claims description 53
- 239000004065 semiconductor Substances 0.000 claims description 20
- 210000000746 body region Anatomy 0.000 claims description 16
- 239000003989 dielectric material Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 167
- 238000009826 distribution Methods 0.000 description 136
- 238000000034 method Methods 0.000 description 118
- 239000007943 implant Substances 0.000 description 104
- 230000008569 process Effects 0.000 description 100
- 239000002019 doping agent Substances 0.000 description 87
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 63
- 229920005591 polysilicon Polymers 0.000 description 63
- 229910052751 metal Inorganic materials 0.000 description 50
- 239000002184 metal Substances 0.000 description 50
- 230000015556 catabolic process Effects 0.000 description 42
- 230000015572 biosynthetic process Effects 0.000 description 38
- 238000005755 formation reaction Methods 0.000 description 38
- 238000002513 implantation Methods 0.000 description 37
- 238000004519 manufacturing process Methods 0.000 description 35
- 125000006850 spacer group Chemical group 0.000 description 31
- 230000003121 nonmonotonic effect Effects 0.000 description 29
- 230000004888 barrier function Effects 0.000 description 20
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 18
- 238000007667 floating Methods 0.000 description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 17
- 108091006146 Channels Proteins 0.000 description 15
- 238000002347 injection Methods 0.000 description 15
- 239000007924 injection Substances 0.000 description 15
- 230000002829 reductive effect Effects 0.000 description 15
- 229910021332 silicide Inorganic materials 0.000 description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 229910052698 phosphorus Inorganic materials 0.000 description 12
- 230000008901 benefit Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 10
- 230000000295 complement effect Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 230000010354 integration Effects 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 230000002411 adverse Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000007480 spreading Effects 0.000 description 6
- 238000003892 spreading Methods 0.000 description 6
- 241000293849 Cordylanthus Species 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000001010 compromised effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000005370 isotopic spin Effects 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
半導体集積回路(IC)チップの製造においては、チップの表面上に形成されたデバイスを電気的に分離することが必要であることが多い。これを行なう種々の方法がある。一つの方法は、チップの表面が窒化ケイ素のような比較的固い材料によりマスクされ、マスクの開口において厚い酸化膜層が熱的に成長する、周知のシリコン局所酸化(Local Oxidation Of Silicon, LOCOS)プロセスを使用することによる。他の方法は、シリコンに溝をエッチングし、その後その溝に酸化ケイ素のような誘電体材料を充填することであり、トレンチ分離としても知られている。LOCOS、トレンチ分離の両方ともに、装置間の不要な表面導電を防止することができるが、完全な電気的分離は容易に行なわれない。
集積デバイスの完全な電気的分離は、典型的には、三重拡散、エピタキシャル接合または誘電体分離を用いて達成される。完全な電気的分離の最も一般的な形式は接合分離である。酸化物がデバイスまたは回路の各々を取り囲む誘電体分離ほど理想的ではないものの、接合分離は歴史的に、製造コストと分離性能との間の最善の妥協を提供してきた。
リチャード・ケイ・ウィリアムズらによる米国特許第6,855,985号明細書、第6,900,091号明細書、第6,943,426号明細書は、これらの各々が本明細書中に引用により援用されるが、これらに開示されるように、CMOSトランジスタ、バイポーラトランジスタおよびDMOSトランジスタを集積する完全分離プロセスは、高温拡散またはエピタキシーを必要とすることなく達成される。このモジュール式のBCDプロセスの原理は、高温プロセスを実質的に必要とせず自己形成する分離構造を製造するための、輪郭に合わせた酸化物を介した高エネルギー(MeV)イオン注入に依存する。輪郭に合わせた酸化物を介した共形イオン注入の原理は、厚い酸化膜層を通ってドーパントを注入することにより原子がシリコン表面の近傍に配置され、薄い酸化膜層を通って注入することにより注入された原子はシリコンの表面から離れたより深くに配置される、という概念である。この低サーマルバジェットプロセスは、高温プロセスが用いられないためにドーパントの再分布がほとんどまたは全く起こらない、「注入されたままの」ドーパント分布によって利益を得る。
本発明に係る分離構造は、埋め込まれたフロア分離領域と、フロア分離領域の上方に配置された誘電体の充填されたトレンチと、トレンチの底部からフロア分離領域へ延びる側壁分離領域とを含み、これらのすべては、一体に基板の分離されたポケットを取り囲む。フロア分離領域は基板内にドーパントを注入することにより形成され、同様に側壁分離領域は、トレンチに誘電体材料が充填される前に、トレンチの底部を経由してドーパントを注入することにより形成される。側壁分離領域は、注入エネルギーの異なる一連の注入により形成されてもよい。これらのプロセスは、注入された領域が本質的に、注入されたときにそうであったのと同一の寸法および形状のままであるように、低温環境において実行される。エピタキシャルプロセスまたはその他の高温プロセスは用いられない。このプロセスは、各ステップが任意の順序で実行されてもよいという意味において、モジュール化されている。もっとも、側壁分離領域を注入する前にトレンチをエッチングするのが好ましい。
先行技術のプロセスに関連する上述した制限を無くすために、本明細書中に開示されるデバイスは、LOCOSの代わりとして、浅い、中間の、または深いトレンチ分離された領域(いわゆるSTIまたはDTI)を使用して分離される。これらの誘電体の充填されたトレンチは、高エネルギーのチェーンイオン注入を用いて結合され、フロア分離を形成し、かつ側壁分離の電圧能力を高める。
・タイプIの分離:深い高エネルギーイオン注入されたフロア分離と、誘電体の充填されたトレンチ側壁分離であって、側壁分離に関連しない浅いトレンチに対する選択肢を有するものと、の組合せ。
・タイプIIの分離:深い高エネルギーイオン注入されたフロア分離と、トレンチの底部に形成された追加的な分離注入部を有する、誘電体の充填されたトレンチ側壁分離と、の組合せ。
・タイプIIIの分離:深い高エネルギーイオン注入されたフロア分離と、側壁分離に必ずしも関連しない誘電体の充填されたトレンチを有する、チェーン注入部が形成された接合側壁分離と、の組合せ。
タイプIIのエピレス分離構造は、図1Aのデバイス分離構造1に示されるが、P型基板2内に形成され誘電体の充填されたトレンチ4A〜4Dを有するN型フロア分離領域3A,3Bと、トレンチ4A〜4Dの底部に形成された側壁N型ドープ分離(NI)領域5A〜5Dと、を備える。随意のP型領域7は、基板2内に、フロア分離領域3A,3Bよりも浅いもしくは深い深さに、または等しい深さに、形成される。結果としてP型ポケット6A,6Bおよび6Dが形成されるが、これらは、各々のポケットの底部における接合分離と各々のポケットの側壁を取り囲む誘電体の充填されたトレンチとの組合せによって、P型基板2から電気的に分離される。
図2A,図2Bは、高温プロセスまたはエピタキシーを必要とせず完全に分離された種々のバイポーラデバイス、CMOSデバイスおよびDMOSデバイスの製造に関する、モジュール化されたプロセスアーキテクチャ30,40を示す。
・側壁の分離およびSTIの形成
・相補型ウェルおよび深い注入の形成
・相補型バイポーラベースの形成
・デュアルゲートの形成
プロセスフロー30に示す工程に続いて、図2Bのモジュール化された集積プロセス順40が、次の工程とともに続く。
・DMOSボディの形成
・浅いドリフトおよび側壁スペーサの形成
・ソースおよびドレイン注入部の形成
・ポリシリコンエミッタの形成
・コンタクトの形成
・多層相互接続の形成
・バンプメタル再分布層の形成
・パッシベーション
・アンダーバンプメタルおよびバンプの形成
本プロセスの重要な特徴は、そのモジュール性、または所望の組のデバイスを実行するために必要とされるプロセスのみを実行する能力である。そのため、上に列記され図2A,2Bに示す工程の多くは、随意である。図2Aのモジュール化されたプロセスアーキテクチャ30を再度参照して、相補型ウェルの形成は、一連のマスクおよび注入部の形成を備え、その後高温拡散および最小限のドーパントの分離は行なわれない。たとえば、予め注入された酸化物は、注入の前にたとえば850℃〜900℃の低温において熱的に成長し、数百オングストロームの厚みに達し、表面濃度を最小化し得る。一つの予め注入された酸化物が、酸化物の除去および再成長の必要なく、複数のウェル注入に使用されてもよい。一つ以上のP型およびN型ウェルが、異なる電圧デバイスの製造を容易に行なうために、異なる領域で形成されてもよい。
浅いドリフトまたは低濃度ドープドレイン(Lightly-doped Drain、LDD)注入部は、マスクされ注入されて、続いてたとえばより低濃度ドープされた12V〜20Vのドリフト領域、および、より高濃度ドープされた1.5V、3Vまたは5Vのドリフト注入部を含む。これらの浅い注入後に、伝統的な方法を使用して、たとえば厚い酸化膜を堆積し異方性エッチングを使用してエッチングすることにより、側壁スペーサ酸化膜が形成される。
図3Aは、共通のP型基板61内に製造された二つの分離されたCMOSデバイス、すなわちCMOS1とCMOS2との断面60を示す。CMOS1は、フロア分離領域62A、誘電体の充填されたトレンチ70およびNI領域65によって基板61から分離された、第一の分離領域内に形成される。この分離領域の内部で、第一のN型ウェル66が、第一のPMOS60Aを含むボディまたはウェル領域を形成するために使用される。N型ウェル66はまた、フロア分離領域62Aに重なることによって直接的に、またはNI領域65にコンタクトし重なることによって間接的に、フロア分離領域62Aにコンタクトするために使用される。好ましい実施の形態では、N型ウェル66のドープ分布は非単調であり、少なくとも頂部NW1と深い部分NW1Bとを備え、N型ウェル66はエネルギーおよびドーズ量の異なるリンチェーン注入を使用して形成される。N型ウェル66の底部がフロア分離領域62Aに重ならない場合、介在するP型領域64Aが結果として生じる。P型領域64Aは浮いており、CMOS1に実質的な電気的影響を及ぼさない。
図4A〜4Cは、上述されたモジュール式のBCDプロセスにおいて構成され得る、いくつかの分離されていないおよび分離された高電圧Nチャネルトランジスタを示す。これらのデバイスは、表面電界を緩和し、デバイスのアヴァランシェ・ブレークダウン(avalanche breakdown)電圧能力を高めるために、深く注入されたN型ドリフト領域NDを使用して形成される。深いND層は、12Vのドリフト領域を形成するために使用される浅いポストポリシリコンLDD領域と違い、ゲートにセルフアラインされない。深い接合は、最適化されたとき、浅いセルフアラインされたドリフト領域よりも、より低い表面電界と低減されたホットキャリア効果との能力を提供する。
多くのパワーアプリケーション(power application)において、整流器としての用途のために、または、スイッチングコンバータ(switching converters)におけるブレイクビフォーメイク(break-before-make)間隔の間にインダクタ電流を再循環するために、分離された高電圧ダイオードが必要とされる。図6Aは、DNカソード302と、P型ウェル305内に囲まれたP+領域309A,309Bを備えるセグメント化されたアノードとを備える、そのような分離されたダイオード300の一つを示す。本発明の一実施の形態では、P型ウェル305のドープ分布は非単調であり、少なくとも頂部PW1と深い部分PW1Bとを備え、エネルギーおよびドーズ量の異なるホウ素チェーン注入を使用して形成される。
他の分離されたダイオード330が図6Bに示される。ダイオード330は、DNカソード領域332と、P型ウェル336A,336B内に囲まれたP+領域339A,339Bを備えるセグメント化されたアノードとを備える。一実施の形態では、P型ウェル336A,336Bのドープ分布は非単調であり、少なくとも頂部PW1と深い部分PW1Bとを備え、好ましくはエネルギーおよびドーズ量の異なるホウ素チェーン注入を使用して形成される。
「常時オフ」のデバイスである従来のエンハンスメント・モードMOSFETとは異なり、JFETは、ソース電位にバイアスされたゲートを有していてもドレイン電流を流す。すなわち、JFETは、VGS=0において電気伝導する。他のトランジスタがまだ動作していないとき、スタートアップ回路のための電流源を形成する場合に、そのようなデバイスが便利である。
拡散エミッタを有するバイポーラトランジスタは、その最大周波数において、ベース領域とエミッタ領域との両方に亘るキャリア移動によって制限される。そのようなデバイスの高周波能力を改善するための従来技術の方法は、ベース領域を有するダイレクトコンタクトにおいて拡散エミッタとポリシリコンとを置き換えることである(たとえば、ミヒャエル・ライシュ(Michael Reisch)著、「ハイフリークエンシー・バイポーラ・トランジスタ(High-frequency Bipolar Transistors)」、シュプリンガー(Springer)、2003年を参照)。極度に浅いポリシリコンエミッタ用のベース深さを調整することにより、数十ギガヘルツの周波数が得られる。
タイプIIのトレンチ分離において分離されたデバイスの電圧能力は、注入された領域の相対的な接合深さによって決定される。他のトレンチ分離の構成と異なり、分離されたデバイスの最大ブレークダウン電圧は、トレンチ深さによって決定されず、深く注入されたDNフロア分離領域の深さおよび注入エネルギーによって決定される。
分離されたポケット間の間隔の低減を可能とすることとは別に、DP注入部は、低電圧および高電圧のNMOS形成において、有効なP型ウェルの抵抗率を下げるために使用されてもよい。たとえば、図13Aでは、一対の相補的な低濃度ドープドレイン(LDD)MOSFETトランジスタが形成され、トレンチ分離によって分離される。
本発明のプロセスは完全に分離されたデバイスの集積を可能にするが、そのモジュール性のために、設計者は、完全な分離が必要でない時にNI注入部およびDN注入部を省略することができる。そのようにするとき、完全に分離されたBCDデバイス集積は、NPNバイポーラトランジスタを有するCMOSへ、すなわち、より少ないマスクとより低いコストとを有するBiCMOSプロセスへと復帰する。このアーキテクチャのモジュール性はさらに、CMOSが分離されていても分離されていなくても、CMOSの電気的特性は不変のままであることを意味する。NPNの電気的特性は、DN層が分離された形のコレクタ抵抗を低減することを除いて、不変のままである。NPNは、周辺のP型基板への逆方向バイアスされた接合を本質的に形成するN型ウェルの内部において形成されるので、ちょうどPMOSデバイスのように「自己分離」する。
本発明に係る他の好ましい実施の形態は、絶縁側壁と、シリコンの表面からトレンチの底部にまで延び、トレンチの底部においてトレンチの底部の下方にあるNI領域と電気的にコンタクトする導電性中心部と、を深いトレンチに組み入れる。絶縁側壁は、二酸化ケイ素、窒化ケイ素、酸窒化膜もしくはサンドイッチ構造、または任意のその他の非導電性誘電体を備えてもよい。側壁の厚みは、トレンチの幅に依存して、100オングストロームから300オングストロームの範囲であってもよい。導電性材料は、好ましくはその場ドープされたポリシリコンであるが、代替的には、高温または高融点金属などのその他の導電性材料を備えてもよい。
本発明の特定の実施の形態が開示されたが、これらの実施の形態は例示のみであって、限定的なものではないことを理解されたい。本発明の広い原理に従った多くの追加のまたは代替する実施の形態が、当業者には明白であろう。
Claims (10)
- 半導体基板に形成された半導体構造であって、前記基板はエピタキシャル層を備えず、前記半導体構造は分離構造を備え、前記分離構造は、
前記基板に埋め込まれた第一導電型のフロア分離領域と、
前記基板の表面から下方へ延びる充填されたトレンチであって、前記充填されたトレンチは誘電体材料を備え、前記充填されたトレンチの底部は前記フロア分離領域の上方に配置され前記フロア分離領域から分離されている、充填されたトレンチと、
前記第一導電型の側壁分離領域であって、前記充填されたトレンチの底部から少なくとも前記フロア分離領域にまで下方へ延び、前記側壁分離領域は前記フロア分離領域に重なり、前記側壁分離領域は前記基板の表面にまで延びておらず、前記フロア分離領域と充填されたトレンチと側壁分離領域とは一体で前記基板の分離されたポケットを囲み、前記基板の前記分離構造の外部に隣接する部分は前記第一導電型と反対の第二導電型である、側壁分離領域と、
前記分離されたポケット内に配置され、前記充填されたトレンチに当接し前記側壁分離領域に重なる前記第一導電型のボディ領域を含む、MOSFETと、
を備え、
前記MOSFETは、
前記基板の表面の上にありゲート誘電体層により前記基板から分離されたゲートと、前記基板の前記表面に近接して配置された前記第二導電型のドレイン領域と、
前記ゲートの下方の前記基板の前記表面に近接して配置されたチャネル領域と、
前記ドレイン領域と前記チャネル領域との間の前記第二導電型のドリフト領域とをさらに備え、
前記ドリフト領域の一部は、前記ゲートの下側へ延びず、前記分離されたポケットの前記第二導電型である一部は、前記ドリフト領域と前記ゲートとの間に存在する、半導体構造。 - 前記ドリフト領域は、前記ゲートにセルフアラインされている、請求項1に記載の半導体構造。
- 前記基板の前記表面と前記分離されたポケットの外部の前記充填されたトレンチとに近接して配置された前記第一導電型の終端領域をさらに備え、前記終端領域は前記ボディ領域に電気的に短絡される、請求項1に記載の半導体構造。
- 前記ボディ領域は、頂部と、前記頂部の下方に配置された深い部分とを含み、前記深い部分は前記頂部よりも高い前記第一導電型のドープ濃度を有する、請求項1に記載の半導体構造。
- 前記深い部分は、前記側壁分離領域に重なる、請求項4に記載の半導体構造。
- 前記MOSFETを囲う前記第二導電型の深く埋め込まれた領域をさらに含む、請求項1に記載の半導体構造。
- 前記MOSFETを囲う前記第二導電型の基板コンタクト領域をさらに含む、請求項6に記載の半導体構造。
- 前記深く埋め込まれた領域は、前記基板コンタクト領域の下にある、請求項7に記載の半導体構造。
- 前記充填されたトレンチは導電性材料を含み、前記誘電体材料は前記充填されたトレンチの壁を覆い、前記充填されたトレンチの底部は前記誘電体材料で覆われておらず、前記充填されたトレンチ内の前記導電性材料は前記側壁分離領域に電気的に接続する、請求項1に記載の半導体構造。
- 半導体基板に形成された半導体構造であって、前記基板はエピタキシャル層を備えず、前記半導体構造は分離構造を備え、前記分離構造は、
前記基板に埋め込まれた第一導電型のフロア分離領域と、
前記基板の表面から下方へ延びる充填されたトレンチであって、前記充填されたトレンチは誘電体材料を備え、前記充填されたトレンチの底部は前記フロア分離領域の上方に配置され前記フロア分離領域から分離されている、充填されたトレンチと、
前記第一導電型の側壁分離領域であって、前記充填されたトレンチの底部から少なくとも前記フロア分離領域にまで下方へ延び、前記側壁分離領域は前記フロア分離領域に重なり、前記側壁分離領域は前記基板の表面にまで延びておらず、前記フロア分離領域と充填されたトレンチと側壁分離領域とは一体で前記基板の分離されたポケットを囲み、前記基板の前記分離構造の外部に隣接する部分は前記第一導電型と反対の第二導電型である、側壁分離領域と、
前記分離されたポケット内に配置され、前記充填されたトレンチに当接し前記側壁分離領域に重なる前記第一導電型のボディ領域を含む、MOSFETと、
を備え、
前記ボディ領域の下側の境界は、前記フロア分離領域の上側の境界の上方に配置され、前記分離されたポケットの介在する部分が前記ボディ領域と前記フロア分離領域との間に残存し、前記分離されたポケットの前記介在する部分は前記第二導電型である、半導体構造。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US92048807P | 2007-03-28 | 2007-03-28 | |
US60/920,488 | 2007-03-28 | ||
US12/002,358 US7737526B2 (en) | 2007-03-28 | 2007-12-17 | Isolated trench MOSFET in epi-less semiconductor sustrate |
US12/002,358 | 2007-12-17 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010500907A Division JP5600839B2 (ja) | 2007-03-28 | 2008-02-27 | 絶縁分離された集積回路装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015202679A Division JP5925374B2 (ja) | 2007-03-28 | 2015-10-14 | 絶縁分離された集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014209634A JP2014209634A (ja) | 2014-11-06 |
JP5826894B2 true JP5826894B2 (ja) | 2015-12-02 |
Family
ID=39788802
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010500907A Expired - Fee Related JP5600839B2 (ja) | 2007-03-28 | 2008-02-27 | 絶縁分離された集積回路装置 |
JP2014114788A Expired - Fee Related JP5826894B2 (ja) | 2007-03-28 | 2014-06-03 | 絶縁分離された集積回路装置 |
JP2015202679A Expired - Fee Related JP5925374B2 (ja) | 2007-03-28 | 2015-10-14 | 絶縁分離された集積回路装置 |
JP2016083661A Expired - Fee Related JP6067907B2 (ja) | 2007-03-28 | 2016-04-19 | 絶縁分離された集積回路装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010500907A Expired - Fee Related JP5600839B2 (ja) | 2007-03-28 | 2008-02-27 | 絶縁分離された集積回路装置 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015202679A Expired - Fee Related JP5925374B2 (ja) | 2007-03-28 | 2015-10-14 | 絶縁分離された集積回路装置 |
JP2016083661A Expired - Fee Related JP6067907B2 (ja) | 2007-03-28 | 2016-04-19 | 絶縁分離された集積回路装置 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7737526B2 (ja) |
EP (1) | EP2130216A4 (ja) |
JP (4) | JP5600839B2 (ja) |
KR (1) | KR101131320B1 (ja) |
CN (1) | CN101730934B (ja) |
TW (1) | TWI385754B (ja) |
WO (1) | WO2008118271A1 (ja) |
Families Citing this family (88)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7956391B2 (en) | 2002-08-14 | 2011-06-07 | Advanced Analogic Technologies, Inc. | Isolated junction field-effect transistor |
US8513087B2 (en) | 2002-08-14 | 2013-08-20 | Advanced Analogic Technologies, Incorporated | Processes for forming isolation structures for integrated circuit devices |
US8089129B2 (en) * | 2002-08-14 | 2012-01-03 | Advanced Analogic Technologies, Inc. | Isolated CMOS transistors |
US7667268B2 (en) | 2002-08-14 | 2010-02-23 | Advanced Analogic Technologies, Inc. | Isolated transistor |
US7812403B2 (en) * | 2002-08-14 | 2010-10-12 | Advanced Analogic Technologies, Inc. | Isolation structures for integrated circuit devices |
US20080197408A1 (en) * | 2002-08-14 | 2008-08-21 | Advanced Analogic Technologies, Inc. | Isolated quasi-vertical DMOS transistor |
US7902630B2 (en) * | 2002-08-14 | 2011-03-08 | Advanced Analogic Technologies, Inc. | Isolated bipolar transistor |
US7939420B2 (en) * | 2002-08-14 | 2011-05-10 | Advanced Analogic Technologies, Inc. | Processes for forming isolation structures for integrated circuit devices |
US7825488B2 (en) | 2006-05-31 | 2010-11-02 | Advanced Analogic Technologies, Inc. | Isolation structures for integrated circuits and modular methods of forming the same |
US7834421B2 (en) * | 2002-08-14 | 2010-11-16 | Advanced Analogic Technologies, Inc. | Isolated diode |
US8212315B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US7230302B2 (en) | 2004-01-29 | 2007-06-12 | Enpirion, Inc. | Laterally diffused metal oxide semiconductor device and method of forming the same |
US8212317B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8212316B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253195B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253196B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253197B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
KR100867977B1 (ko) | 2006-10-11 | 2008-11-10 | 한국과학기술원 | 인도시아닌 그린 혈중 농도 역학을 이용한 조직 관류 분석장치 및 그를 이용한 조직 관류 분석방법 |
US7737526B2 (en) | 2007-03-28 | 2010-06-15 | Advanced Analogic Technologies, Inc. | Isolated trench MOSFET in epi-less semiconductor sustrate |
US7868414B2 (en) * | 2007-03-28 | 2011-01-11 | Advanced Analogic Technologies, Inc. | Isolated bipolar transistor |
DE102007056103B4 (de) * | 2007-11-15 | 2010-03-04 | Texas Instruments Deutschland Gmbh | Verfahren zur Herstellung von isolierten integrierten Halbleiterstrukturen |
KR101035596B1 (ko) * | 2007-12-28 | 2011-05-19 | 매그나칩 반도체 유한회사 | 딥 트렌치 구조를 갖는 반도체 소자 |
US9240402B2 (en) * | 2008-02-13 | 2016-01-19 | Acco Semiconductor, Inc. | Electronic circuits including a MOSFET and a dual-gate JFET |
US7859009B1 (en) | 2008-06-17 | 2010-12-28 | Rf Micro Devices, Inc. | Integrated lateral high-voltage diode and thyristor |
US7989889B1 (en) | 2008-06-17 | 2011-08-02 | Rf Micro Devices, Inc. | Integrated lateral high-voltage metal oxide semiconductor field effect transistor |
US7633095B1 (en) * | 2008-06-17 | 2009-12-15 | Rf Micro Devices, Inc. | Integration of high-voltage devices and other devices |
JP5570743B2 (ja) * | 2009-03-09 | 2014-08-13 | 株式会社東芝 | 半導体装置 |
US7902608B2 (en) * | 2009-05-28 | 2011-03-08 | International Business Machines Corporation | Integrated circuit device with deep trench isolation regions for all inter-well and intra-well isolation and with a shared contact to a junction between adjacent device diffusion regions and an underlying floating well section |
US9478537B2 (en) * | 2009-07-15 | 2016-10-25 | Cree, Inc. | High-gain wide bandgap darlington transistors and related methods of fabrication |
JP4995873B2 (ja) * | 2009-08-05 | 2012-08-08 | 株式会社東芝 | 半導体装置及び電源回路 |
JP5546191B2 (ja) * | 2009-09-25 | 2014-07-09 | セイコーインスツル株式会社 | 半導体装置 |
JP5560812B2 (ja) | 2010-03-23 | 2014-07-30 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
KR20110119400A (ko) * | 2010-04-27 | 2011-11-02 | 삼성전자주식회사 | 슬리티드 웰 터브를 갖는 반도체소자 |
US7977742B1 (en) | 2010-08-20 | 2011-07-12 | Monolithic Power Systems, Inc. | Trench-gate MOSFET with capacitively depleted drift region |
JP2012124207A (ja) * | 2010-12-06 | 2012-06-28 | Toshiba Corp | 半導体装置 |
CN102623511B (zh) * | 2011-01-26 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | 功率二极管 |
US9543434B2 (en) | 2011-05-19 | 2017-01-10 | Hewlett-Packard Development Company, L.P. | Device active channel length/width greater than channel length/width |
US8581339B2 (en) | 2011-08-08 | 2013-11-12 | Macronix International Co., Ltd. | Structure of NPN-BJT for improving punch through between collector and emitter |
JP5743831B2 (ja) * | 2011-09-29 | 2015-07-01 | 株式会社東芝 | 半導体装置 |
CN102496573B (zh) * | 2011-12-28 | 2014-01-01 | 上海先进半导体制造股份有限公司 | 沟槽绝缘栅型双极晶体管的制作方法 |
US8921978B2 (en) * | 2012-01-10 | 2014-12-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual DNW isolation structure for reducing RF noise on high voltage semiconductor devices |
US8723178B2 (en) | 2012-01-20 | 2014-05-13 | Monolithic Power Systems, Inc. | Integrated field effect transistors with high voltage drain sensing |
JP5343141B2 (ja) * | 2012-02-20 | 2013-11-13 | 株式会社東芝 | 半導体装置 |
US8664050B2 (en) | 2012-03-20 | 2014-03-04 | International Business Machines Corporation | Structure and method to improve ETSOI MOSFETS with back gate |
US9190535B2 (en) | 2012-05-25 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bootstrap MOS for high voltage applications |
US8704279B2 (en) | 2012-05-25 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded JFETs for high voltage applications |
US9231083B2 (en) * | 2012-06-29 | 2016-01-05 | Freescal Semiconductor Inc. | High breakdown voltage LDMOS device |
US10269658B2 (en) | 2012-06-29 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit devices with well regions and methods for forming the same |
US9076760B2 (en) * | 2012-08-29 | 2015-07-07 | Texas Instruments Incorporated | JFET having width defined by trench isolation |
TWI655718B (zh) | 2012-11-30 | 2019-04-01 | 美商英力股份有限公司 | 包含耦合至一去耦裝置之半導體裝置之設備及其形成方法 |
JP6085166B2 (ja) * | 2012-12-20 | 2017-02-22 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置 |
JP2014150113A (ja) * | 2013-01-31 | 2014-08-21 | Toyota Motor Corp | 半導体装置及び半導体装置の製造方法 |
KR101392587B1 (ko) * | 2013-02-19 | 2014-05-27 | 주식회사 동부하이텍 | 고전압 정전기 방전 보호 소자 |
JP2014170831A (ja) | 2013-03-04 | 2014-09-18 | Seiko Epson Corp | 回路装置及び電子機器 |
KR101975608B1 (ko) * | 2013-06-12 | 2019-05-08 | 매그나칩 반도체 유한회사 | 고전압용 esd 트랜지스터 및 그 정전기 보호 회로 |
US9006833B2 (en) * | 2013-07-02 | 2015-04-14 | Texas Instruments Incorporated | Bipolar transistor having sinker diffusion under a trench |
US9059278B2 (en) * | 2013-08-06 | 2015-06-16 | International Business Machines Corporation | High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region |
US9536938B1 (en) | 2013-11-27 | 2017-01-03 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US9673192B1 (en) | 2013-11-27 | 2017-06-06 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US10020739B2 (en) | 2014-03-27 | 2018-07-10 | Altera Corporation | Integrated current replicator and method of operating the same |
US9299857B2 (en) * | 2014-06-19 | 2016-03-29 | Macronix International Co., Ltd. | Semiconductor device |
US9312382B2 (en) * | 2014-07-22 | 2016-04-12 | Empire Technology Development Llc | High voltage transistor device with reduced characteristic on resistance |
TWI559530B (zh) * | 2014-07-29 | 2016-11-21 | 旺宏電子股份有限公司 | 半導體裝置 |
KR20160058499A (ko) * | 2014-11-17 | 2016-05-25 | 삼성전자주식회사 | 반도체 소자, 및 그 반도체 소자의 제조방법과 제조장치 |
CN104538397A (zh) * | 2014-12-29 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | 桥式二极管整流器及其制造方法 |
CN105826322B (zh) * | 2015-01-04 | 2018-12-14 | 旺宏电子股份有限公司 | 有源元件及应用其的高压半导体元件 |
US10103627B2 (en) | 2015-02-26 | 2018-10-16 | Altera Corporation | Packaged integrated circuit including a switch-mode regulator and method of forming the same |
US10784372B2 (en) * | 2015-04-03 | 2020-09-22 | Magnachip Semiconductor, Ltd. | Semiconductor device with high voltage field effect transistor and junction field effect transistor |
CN106206585B (zh) * | 2015-05-04 | 2019-03-12 | 华邦电子股份有限公司 | 自对准埋入式字线隔离结构的形成方法 |
JP6641958B2 (ja) * | 2015-12-11 | 2020-02-05 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
US9633993B1 (en) * | 2016-04-01 | 2017-04-25 | Texas Instruments Incorporated | Bipolar SCR |
CN106024697B (zh) * | 2016-07-12 | 2024-01-26 | 杭州士兰集成电路有限公司 | 沟槽功率器件及制作方法 |
KR102166618B1 (ko) * | 2016-09-26 | 2020-10-16 | 온세미컨덕터코리아 주식회사 | 정전기 방전 회로 및 그 제조 방법 |
KR102140358B1 (ko) * | 2016-12-23 | 2020-08-03 | 매그나칩 반도체 유한회사 | 잡음 감소를 위한 분리 구조를 갖는 통합 반도체 소자 |
CN108878367B (zh) * | 2017-05-09 | 2021-02-05 | 上海珏芯光电科技有限公司 | BiCMOS集成电路器件的制造方法及器件 |
JP2017139503A (ja) * | 2017-05-18 | 2017-08-10 | セイコーエプソン株式会社 | 回路装置及び電子機器 |
US10340266B2 (en) * | 2017-10-02 | 2019-07-02 | Globalfoundries Singapore Pte. Ltd. | ESD protection circuit and method of making the same |
WO2019143733A1 (en) * | 2018-01-16 | 2019-07-25 | Ipower Semiconductor | Self-aligned and robust igbt devices |
KR20190140220A (ko) | 2018-06-11 | 2019-12-19 | 에스케이하이닉스 주식회사 | 정전기 방지 회로를 구비하는 반도체 집적 회로 장치 및 그 제조방법 |
CN109638083B (zh) * | 2018-12-29 | 2024-04-05 | 捷捷半导体有限公司 | 一种快恢复二极管及其制备方法 |
JP7376516B2 (ja) * | 2019-02-07 | 2023-11-08 | ローム株式会社 | 半導体装置 |
US10896953B2 (en) * | 2019-04-12 | 2021-01-19 | Globalfoundries Inc. | Diode structures |
JP2021034493A (ja) * | 2019-08-22 | 2021-03-01 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置及び電子機器 |
US11227921B2 (en) * | 2019-11-22 | 2022-01-18 | Nxp Usa, Inc. | Laterally-diffused metal-oxide semiconductor transistor and method therefor |
US11482521B2 (en) * | 2020-02-06 | 2022-10-25 | Globalfoundries U.S. Inc. | Integrated circuit with P-N-P junction and vertically aligned field effect transistor, and method to form same |
CN111933640B (zh) * | 2020-07-28 | 2023-03-17 | 杭州士兰微电子股份有限公司 | 高压集成电路及其制造方法 |
CN114975574A (zh) * | 2021-02-19 | 2022-08-30 | 联华电子股份有限公司 | 高压半导体装置 |
US20230040387A1 (en) * | 2021-08-06 | 2023-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Seal Ring For Semiconductor Device With Gate-All-Around Transistors |
Family Cites Families (96)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5269587A (en) * | 1975-12-08 | 1977-06-09 | Hitachi Ltd | Device and manufacture for high voltage resisting semiconductor |
US4269636A (en) | 1978-12-29 | 1981-05-26 | Harris Corporation | Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking |
JPS5824018B2 (ja) | 1979-12-21 | 1983-05-18 | 富士通株式会社 | バイポ−ラicの製造方法 |
FR2498812A1 (fr) * | 1981-01-27 | 1982-07-30 | Thomson Csf | Structure de transistors dans un circuit integre et son procede de fabrication |
US4454647A (en) | 1981-08-27 | 1984-06-19 | International Business Machines Corporation | Isolation for high density integrated circuits |
JPS58100441A (ja) | 1981-12-10 | 1983-06-15 | Toshiba Corp | 半導体装置の製造方法 |
US4485392A (en) * | 1981-12-28 | 1984-11-27 | North American Philips Corporation | Lateral junction field effect transistor device |
JPS60117654A (ja) * | 1983-11-30 | 1985-06-25 | Toshiba Corp | 相補型半導体装置 |
JPS613449A (ja) * | 1984-06-15 | 1986-01-09 | Nec Corp | 集積回路装置 |
US4655875A (en) | 1985-03-04 | 1987-04-07 | Hitachi, Ltd. | Ion implantation process |
US6740958B2 (en) | 1985-09-25 | 2004-05-25 | Renesas Technology Corp. | Semiconductor memory device |
JPS639968A (ja) * | 1986-07-01 | 1988-01-16 | Olympus Optical Co Ltd | 静電誘導トランジスタイメ−ジセンサの素子分離法 |
JPS63110769A (ja) * | 1986-10-29 | 1988-05-16 | Hitachi Ltd | 高集積半導体装置 |
US4819052A (en) | 1986-12-22 | 1989-04-04 | Texas Instruments Incorporated | Merged bipolar/CMOS technology using electrically active trench |
US4980747A (en) | 1986-12-22 | 1990-12-25 | Texas Instruments Inc. | Deep trench isolation with surface contact to substrate |
JPH01149464A (ja) * | 1987-12-04 | 1989-06-12 | Nec Corp | 半導体装置 |
US5156989A (en) | 1988-11-08 | 1992-10-20 | Siliconix, Incorporated | Complementary, isolated DMOS IC technology |
US5410175A (en) | 1989-08-31 | 1995-04-25 | Hamamatsu Photonics K.K. | Monolithic IC having pin photodiode and an electrically active element accommodated on the same semi-conductor substrate |
US5386136A (en) | 1991-05-06 | 1995-01-31 | Siliconix Incorporated | Lightly-doped drain MOSFET with improved breakdown characteristics |
KR100292851B1 (ko) | 1991-09-27 | 2001-09-17 | 스콧 티. 마이쿠엔 | 높은얼리전압,고주파성능및고항복전압특성을구비한상보형바이폴라트랜지스터및그제조방법 |
JPH05109886A (ja) | 1991-10-17 | 1993-04-30 | N M B Semiconductor:Kk | フイールドシールド分離構造の半導体装置およびその製造方法 |
JPH0613409A (ja) * | 1992-06-24 | 1994-01-21 | Ricoh Co Ltd | 半導体素子及びその製造方法 |
US5422508A (en) | 1992-09-21 | 1995-06-06 | Siliconix Incorporated | BiCDMOS structure |
US5420061A (en) | 1993-08-13 | 1995-05-30 | Micron Semiconductor, Inc. | Method for improving latchup immunity in a dual-polysilicon gate process |
US5892264A (en) | 1993-10-04 | 1999-04-06 | Harris Corporation | High frequency analog transistors, method of fabrication and circuit implementation |
JPH07106412A (ja) * | 1993-10-07 | 1995-04-21 | Toshiba Corp | 半導体装置およびその製造方法 |
JP3252569B2 (ja) | 1993-11-09 | 2002-02-04 | 株式会社デンソー | 絶縁分離基板及びそれを用いた半導体装置及びその製造方法 |
US5517046A (en) * | 1993-11-19 | 1996-05-14 | Micrel, Incorporated | High voltage lateral DMOS device with enhanced drift region |
US5506431A (en) | 1994-05-16 | 1996-04-09 | Thomas; Mammen | Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications |
US5684305A (en) | 1995-06-07 | 1997-11-04 | Harris Corporation | Pilot transistor for quasi-vertical DMOS device |
JPH10506503A (ja) | 1995-07-19 | 1998-06-23 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | Hv−ldmost型の半導体装置 |
JP3575908B2 (ja) | 1996-03-28 | 2004-10-13 | 株式会社東芝 | 半導体装置 |
EP0847078A4 (en) * | 1996-06-24 | 2000-10-04 | Matsushita Electric Ind Co Ltd | MANUFACTURING METHOD OF SEMICONDUCTOR ARRANGEMENTS |
US5807783A (en) | 1996-10-07 | 1998-09-15 | Harris Corporation | Surface mount die by handle replacement |
KR100205609B1 (ko) | 1997-01-06 | 1999-07-01 | 윤종용 | 정전기 보호 소자 |
JP3393544B2 (ja) * | 1997-02-26 | 2003-04-07 | シャープ株式会社 | 半導体装置の製造方法 |
US6163052A (en) | 1997-04-04 | 2000-12-19 | Advanced Micro Devices, Inc. | Trench-gated vertical combination JFET and MOSFET devices |
EP1021828B1 (en) * | 1997-07-11 | 2010-01-06 | Infineon Technologies AG | A process for manufacturing ic-components to be used at radio frequencies |
JP2978467B2 (ja) * | 1998-03-16 | 1999-11-15 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
JP3097652B2 (ja) * | 1998-03-31 | 2000-10-10 | 日本電気株式会社 | 半導体集積回路装置の製造方法 |
US6331456B1 (en) | 1998-05-04 | 2001-12-18 | Texas Instruments - Acer Incorporated | Fipos method of forming SOI CMOS structure |
US6759306B1 (en) * | 1998-07-10 | 2004-07-06 | Micron Technology, Inc. | Methods of forming silicon dioxide layers and methods of forming trench isolation regions |
US6013936A (en) | 1998-08-06 | 2000-01-11 | International Business Machines Corporation | Double silicon-on-insulator device and method therefor |
JP2000114361A (ja) * | 1998-09-29 | 2000-04-21 | Toshiba Corp | 半導体集積回路装置及びその製造方法 |
JP4508304B2 (ja) * | 1998-11-26 | 2010-07-21 | 三洋電機株式会社 | 半導体集積回路装置 |
US20010013636A1 (en) | 1999-01-22 | 2001-08-16 | James S. Dunn | A self-aligned, sub-minimum isolation ring |
EP1043775B1 (en) | 1999-04-06 | 2006-06-14 | STMicroelectronics S.r.l. | Power integrated circuit with vertical current flow and related manufacturing process |
US6144086A (en) | 1999-04-30 | 2000-11-07 | International Business Machines Corporation | Structure for improved latch-up using dual depth STI with impurity implant |
KR100300069B1 (ko) | 1999-05-10 | 2001-09-26 | 김영환 | 반도체 소자 및 그 제조방법 |
US6448124B1 (en) | 1999-11-12 | 2002-09-10 | International Business Machines Corporation | Method for epitaxial bipolar BiCMOS |
US6489653B2 (en) | 1999-12-27 | 2002-12-03 | Kabushiki Kaisha Toshiba | Lateral high-breakdown-voltage transistor |
US6440805B1 (en) * | 2000-02-29 | 2002-08-27 | Mototrola, Inc. | Method of forming a semiconductor device with isolation and well regions |
IT1316871B1 (it) | 2000-03-31 | 2003-05-12 | St Microelectronics Srl | Dispositivo elettronico integrato monoliticamente e relativo processodi fabbricazione |
IT1317516B1 (it) | 2000-05-11 | 2003-07-09 | St Microelectronics Srl | Dispositivo integrato con struttura d'isolamento a trench e relativoprocesso di realizzazione. |
JP2002198439A (ja) | 2000-12-26 | 2002-07-12 | Sharp Corp | 半導体装置および携帯電子機器 |
US6600199B2 (en) | 2000-12-29 | 2003-07-29 | International Business Machines Corporation | Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity |
JP2002237591A (ja) | 2000-12-31 | 2002-08-23 | Texas Instruments Inc | Dmosトランジスタ・ソース構造とその製法 |
JP2002237575A (ja) * | 2001-02-08 | 2002-08-23 | Sharp Corp | 半導体装置及びその製造方法 |
JP2003100862A (ja) * | 2001-09-21 | 2003-04-04 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
KR100456691B1 (ko) * | 2002-03-05 | 2004-11-10 | 삼성전자주식회사 | 이중격리구조를 갖는 반도체 소자 및 그 제조방법 |
US7179691B1 (en) | 2002-07-29 | 2007-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for four direction low capacitance ESD protection |
US6867462B2 (en) | 2002-08-09 | 2005-03-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device using an SOI substrate and having a trench isolation and method for fabricating the same |
US7834421B2 (en) | 2002-08-14 | 2010-11-16 | Advanced Analogic Technologies, Inc. | Isolated diode |
US7667268B2 (en) | 2002-08-14 | 2010-02-23 | Advanced Analogic Technologies, Inc. | Isolated transistor |
US20080197408A1 (en) | 2002-08-14 | 2008-08-21 | Advanced Analogic Technologies, Inc. | Isolated quasi-vertical DMOS transistor |
US7956391B2 (en) | 2002-08-14 | 2011-06-07 | Advanced Analogic Technologies, Inc. | Isolated junction field-effect transistor |
US6900091B2 (en) | 2002-08-14 | 2005-05-31 | Advanced Analogic Technologies, Inc. | Isolated complementary MOS devices in epi-less substrate |
US7902630B2 (en) | 2002-08-14 | 2011-03-08 | Advanced Analogic Technologies, Inc. | Isolated bipolar transistor |
US7939420B2 (en) | 2002-08-14 | 2011-05-10 | Advanced Analogic Technologies, Inc. | Processes for forming isolation structures for integrated circuit devices |
US7825488B2 (en) | 2006-05-31 | 2010-11-02 | Advanced Analogic Technologies, Inc. | Isolation structures for integrated circuits and modular methods of forming the same |
US8089129B2 (en) | 2002-08-14 | 2012-01-03 | Advanced Analogic Technologies, Inc. | Isolated CMOS transistors |
US6943426B2 (en) * | 2002-08-14 | 2005-09-13 | Advanced Analogic Technologies, Inc. | Complementary analog bipolar transistors with trench-constrained isolation diffusion |
US7741661B2 (en) | 2002-08-14 | 2010-06-22 | Advanced Analogic Technologies, Inc. | Isolation and termination structures for semiconductor die |
US7719054B2 (en) | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
US6855985B2 (en) * | 2002-09-29 | 2005-02-15 | Advanced Analogic Technologies, Inc. | Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology |
EP1612861B1 (en) * | 2003-04-10 | 2018-10-03 | Fujitsu Semiconductor Limited | Semiconductor device and its manufacturing method |
JP4569105B2 (ja) * | 2003-12-25 | 2010-10-27 | 富士電機システムズ株式会社 | 半導体装置 |
US20050179111A1 (en) | 2004-02-12 | 2005-08-18 | Iwen Chao | Semiconductor device with low resistive path barrier |
US7304354B2 (en) | 2004-02-17 | 2007-12-04 | Silicon Space Technology Corp. | Buried guard ring and radiation hardened isolation structures and fabrication methods |
JP4429036B2 (ja) * | 2004-02-27 | 2010-03-10 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
TWI231986B (en) | 2004-03-22 | 2005-05-01 | Sunplus Technology Co Ltd | ESD protection device for high voltage and negative voltage tolerance |
US7009271B1 (en) | 2004-04-13 | 2006-03-07 | Advanced Micro Devices, Inc. | Memory device with an alternating Vss interconnection |
US7183610B2 (en) | 2004-04-30 | 2007-02-27 | Siliconix Incorporated | Super trench MOSFET including buried source electrode and method of fabricating the same |
JP4592340B2 (ja) * | 2004-06-29 | 2010-12-01 | 三洋電機株式会社 | 半導体装置の製造方法 |
US7161213B2 (en) * | 2004-08-05 | 2007-01-09 | Broadcom Corporation | Low threshold voltage PMOS apparatus and method of fabricating the same |
US7229886B2 (en) * | 2004-08-23 | 2007-06-12 | Enpirion, Inc. | Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein |
US20060076629A1 (en) | 2004-10-07 | 2006-04-13 | Hamza Yilmaz | Semiconductor devices with isolation and sinker regions containing trenches filled with conductive material |
JP4959140B2 (ja) | 2005-02-04 | 2012-06-20 | 株式会社日立超エル・エス・アイ・システムズ | 半導体装置 |
CN100449782C (zh) * | 2005-04-29 | 2009-01-07 | 崇贸科技股份有限公司 | 具隔离结构的金属氧化物半导体场效晶体管及其制作方法 |
US7719080B2 (en) | 2005-06-20 | 2010-05-18 | Teledyne Scientific & Imaging, Llc | Semiconductor device with a conduction enhancement layer |
US20070132056A1 (en) | 2005-12-09 | 2007-06-14 | Advanced Analogic Technologies, Inc. | Isolation structures for semiconductor integrated circuit substrates and methods of forming the same |
US20070158779A1 (en) * | 2006-01-12 | 2007-07-12 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a buried damage layer |
US7718481B2 (en) * | 2006-04-17 | 2010-05-18 | International Business Machines Corporation | Semiconductor structure and method of manufacture |
US7868414B2 (en) | 2007-03-28 | 2011-01-11 | Advanced Analogic Technologies, Inc. | Isolated bipolar transistor |
US7737526B2 (en) | 2007-03-28 | 2010-06-15 | Advanced Analogic Technologies, Inc. | Isolated trench MOSFET in epi-less semiconductor sustrate |
US7541247B2 (en) | 2007-07-16 | 2009-06-02 | International Business Machines Corporation | Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication |
-
2007
- 2007-12-17 US US12/002,358 patent/US7737526B2/en not_active Expired - Fee Related
-
2008
- 2008-02-27 EP EP08726138A patent/EP2130216A4/en not_active Withdrawn
- 2008-02-27 CN CN2008800182214A patent/CN101730934B/zh not_active Expired - Fee Related
- 2008-02-27 KR KR1020097022107A patent/KR101131320B1/ko not_active IP Right Cessation
- 2008-02-27 JP JP2010500907A patent/JP5600839B2/ja not_active Expired - Fee Related
- 2008-02-27 WO PCT/US2008/002558 patent/WO2008118271A1/en active Application Filing
- 2008-03-12 TW TW097108747A patent/TWI385754B/zh not_active IP Right Cessation
-
2014
- 2014-06-03 JP JP2014114788A patent/JP5826894B2/ja not_active Expired - Fee Related
-
2015
- 2015-10-14 JP JP2015202679A patent/JP5925374B2/ja not_active Expired - Fee Related
-
2016
- 2016-04-19 JP JP2016083661A patent/JP6067907B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP5925374B2 (ja) | 2016-05-25 |
KR20100036221A (ko) | 2010-04-07 |
EP2130216A4 (en) | 2011-09-28 |
US7737526B2 (en) | 2010-06-15 |
TW200847330A (en) | 2008-12-01 |
JP5600839B2 (ja) | 2014-10-08 |
CN101730934A (zh) | 2010-06-09 |
JP6067907B2 (ja) | 2017-01-25 |
EP2130216A1 (en) | 2009-12-09 |
US20080237704A1 (en) | 2008-10-02 |
CN101730934B (zh) | 2012-01-25 |
JP2010522986A (ja) | 2010-07-08 |
WO2008118271A1 (en) | 2008-10-02 |
TWI385754B (zh) | 2013-02-11 |
JP2016028444A (ja) | 2016-02-25 |
JP2014209634A (ja) | 2014-11-06 |
KR101131320B1 (ko) | 2012-04-04 |
JP2016167613A (ja) | 2016-09-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6067907B2 (ja) | 絶縁分離された集積回路装置 | |
US7868414B2 (en) | Isolated bipolar transistor | |
JP6349337B2 (ja) | 分離されたcmosおよびバイポーラトランジスタ、それらのための分離構造、ならびにその作製方法 | |
US7902630B2 (en) | Isolated bipolar transistor | |
US7939420B2 (en) | Processes for forming isolation structures for integrated circuit devices | |
US10074716B2 (en) | Saucer-shaped isolation structures for semiconductor devices | |
US8513087B2 (en) | Processes for forming isolation structures for integrated circuit devices | |
US7812403B2 (en) | Isolation structures for integrated circuit devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150227 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150331 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150630 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150915 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20151014 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5826894 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |