CN100449782C - 具隔离结构的金属氧化物半导体场效晶体管及其制作方法 - Google Patents
具隔离结构的金属氧化物半导体场效晶体管及其制作方法 Download PDFInfo
- Publication number
- CN100449782C CN100449782C CNB2005100668502A CN200510066850A CN100449782C CN 100449782 C CN100449782 C CN 100449782C CN B2005100668502 A CNB2005100668502 A CN B2005100668502A CN 200510066850 A CN200510066850 A CN 200510066850A CN 100449782 C CN100449782 C CN 100449782C
- Authority
- CN
- China
- Prior art keywords
- type
- region
- diffusion region
- effect transistor
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 87
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 53
- 150000004706 metal oxides Chemical class 0.000 title claims description 51
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 238000009792 diffusion process Methods 0.000 claims description 144
- 239000002184 metal Substances 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 47
- 238000005304 joining Methods 0.000 claims description 28
- 238000000926 separation method Methods 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 230000000694 effects Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 description 60
- 238000005516 engineering process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 2
- 230000005516 deep trap Effects 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
本发明涉及一种具有隔离结构的金属氧化物半导体场效晶体管,其中一N型金属氧化物半导体场效晶体管包括有一置于一P型衬底内的第一N型嵌入层与一P型外延层;一P型场效晶体管包括有一置于该P型衬底内的一第二N型嵌入层与该P型外延层。该第一、第二N型嵌入层与该P型外延层提供了场效晶体管间的隔离。此外,多个置于该P型外延层中的分离P型区域更提供进一步的隔离效果;一第一间隙存在于一第一厚场氧化层与一第一P型区域间,用以提高该N型场效晶体管的击穿电压;一第二间隙则存在于一第二厚场氧化层与一第二N型阱间,用以提高该P型场效晶体管的击穿电压。
Description
技术领域
本发明涉及一种具有隔离结构的金属氧化物半导体场效晶体管及其制作方法,尤指一种通过低压互补型金属氧化物半导体制造过程制造的具有隔离结构的金属氧化物半导体场效晶体管(Metal Oxide Semiconductor FieldEffect Transistor)。
背景技术
集成控制电路与驱动晶体管的技术已成为现今电源集成电路(Power IC)的发展趋势。因此,若能利用标准制造过程来制作晶体管器件,似乎是单片IC集成的较佳方案。然而,现今标准制造过程所制作的晶体管却是非隔离结构,其未经隔离的晶体管电流可能会在衬底中流动而对控制电路产生干扰;此外,该晶体管电流也可能产生地弹跳(ground bounce),而影响控制电路的控制信号,因此非隔离结构的晶体管并不适用在这样的集成技术上。
请参阅图1及图2所示,其为N型及P型金属氧化物半导体场效晶体管的电路示意图。由图中可知,该N型金属氧化物半导体场效晶体管(NMOS)10包括有一漏极20、一源极30与一栅极40;该P型金属氧化物半导体场效晶体管(PMOS)50包括有一漏极60、一源极70与一栅极80。
请参阅图3所示,其为公知金属氧化物半导体场效晶体管的结构剖面图。由图中可知,一N型金属氧化物半导体场效晶体管10与P型金属氧化物半导体场效晶体管50,包括一P型衬底100,一N+型嵌入层860与一P+型嵌入层880形成于该P型衬底100内,一N型外延(epitaxial)层660与一N型外延层680分别形成于该N+型嵌入层860与该P+型嵌入层880上。
再者,传统晶体管隔离结构是采用该N型外延层660将该N型场效晶体管10的第一漏极区域230及第一P型区域220包围起来,并利用一N型外延层680将该P型场效晶体管50的第二源极区域440、第二接点区域450及第二P型区域420包围起来。且多个具有P+型离子的分离P+型区域500形成于该N型外延层660与680之间,为金属氧化物半导体场效晶体管之间提供隔离。然而,以上述传统方式所形成的隔离结构不但制造过程较复杂,而且需花费较高的制作成本。
发明内容
本发明所要解决的技术问题,在于提供一种具有较高击穿电压、低导通阻抗与隔离结构的金属氧化物半导体场效晶体管器件,以达成单片IC集成的目标。另外,本发明不需要传统制造过程中制造外延层的额外光掩模数,仅利用标准的阱结构,便能达到低成本、高良率与隔离的晶体管结构。
为了解决上述技术问题,根据本发明的其中一种方案,提供一种低压互补型金属氧化物半导体制造过程制造的具有隔离结构的金属氧化物半导体场效晶体管。该金属氧化物半导体场效晶体管包括有一N型金属氧化物半导体场效晶体管与一P型金属氧化物半导体场效晶体管置于一P型衬底内。该N型金属氧化物半导体场效晶体管包括有一置于该P型衬底内的第一N型嵌入层与一P型外延层;一具有N型导电离子的第一N型扩散区,在该第一N型嵌入层内形成一第一N型阱;一具有P型导电离子的第一P型扩散区,在该第一N型阱中形成一第一P型区域;一具有N+型导电离子的第一漏极扩散区,在该第一N型扩散区中形成一第一漏极区域;一具有N+型导电离子的第一源极扩散区形成一第一源极区域;与一具有P+型导电离子的第一接点扩散区形成一第一接点区域;其中,该第一P型扩散区将该第一源极区域与该第一接点区域包围起来。该N型金属氧化物半导体场效晶体管还包括:具有P型导电离子的多个分离的P型扩散区,在该P型外延层内形成有多个分离的P型区域以提供隔离特性;第一薄栅氧化层与一第一厚场氧化层,形成于该P型衬底上;第一栅极,置放于该第一薄栅氧化层与该第一厚场氧化层之上,用以控制该第一沟道内的电流量;硅氧化绝缘层,覆盖于该第一栅极与该第一厚场氧化层上;第一漏极金属接点,其具有与该第一漏极扩散区相连接的第一金属电极;第一源极金属接点,其具有连接至该第一源极扩散区与该第一接点扩散区的第二金属电极;以及第一间隙,存在于该第一厚场氧化层与该第一P型区域间,借以提高该N型金属氧化物半导体场效晶体管的击穿电压。
根据本发明的N型金属氧化物半导体场效晶体管,其中位于该第一N型阱内的该第一P型区域是通过一P型阱制造过程制得。
根据本发明的N型金属氧化物半导体场效晶体管,其中位于该第一N型阱内的该第一P型区域是通过一P型基体制造过程制得。
该P型金属氧化物半导体场效晶体管包括有一置于该P型衬底内的第二N型嵌入层与该P型外延层;一具有N型导电离子的第二N型扩散区,在该第二N型嵌入层中形成一第二N型阱;一具有P型导电离子的第二P型扩散区,在该第二N型阱中形成一第二P型区域;一具有P+型导电离子的第二漏极扩散区,在该第二P型扩散区中形成一第二漏极区域;一具有P+型导电离子的第二源极扩散区形成一第二源极区域;与一具有N+型导电离子的第二接点扩散区形成一第二接点区域;其中,该第二N型扩散区将该第二源极区域与该第二接点区域包围起来。
根据本发明的P型金属氧化物半导体场效晶体管,其中位于该第二N型阱内的该第二P型区域是通过一P型阱制造过程制得。
根据本发明的P型金属氧化物半导体场效晶体管,其中位于该第二N型阱内的该第二P型区域是通过一P型基体制造过程制得。
该第一N型嵌入层、该第二N型嵌入层与该P型外延层提供场效晶体管间的隔离。此外,具有P型导电离子的多个分离的P型扩散区在该P型外延层中形成多个分离的P型区域,提供场效晶体管间更进一步的隔离,位于该第一N型扩散区的该第一P型区域、位于该第二N型扩散区的该第二P型区域、该多个分离的P型区域、该第一N型阱与该第二N型阱,于不同极性的区域间形成耗尽区域。一第一沟道在该第一源极区域与该第一漏极区域间形成,一第二沟道在该第二源极区域与该第二漏极区域间形成,一第一栅极位于一第一薄栅氧化层与一第一厚场氧化层之上,用以控制该第一沟道中的电流量,一第二栅极位于一第二薄栅氧化层与一第二厚场氧化层之上,用以控制该第二沟道中的电流量。
再者,由该第一N型扩散区与该第二N型扩散区所分别形成的该第一N型阱与该第二N型阱,为该N型金属氧化物半导体场效晶体管与该P型金属氧化物半导体场效晶体管提供了一低阻抗路径,用以限制在该第一漏极区域与该第一源极区域之间的晶体管电流以及该第二漏极区域与该第二源极区域之间的晶体管电流。
为了解决上述技术问题,根据本发明的另一种方案,提供一种低压互补型金属氧化物半导体制造过程制造的具有隔离结构的金属氧化物半导体场效晶体管的制作方法。其中,一N型金属氧化物半导体场效晶体管的制作方法包括有:首先,形成一P型衬底;接着,于该P型衬底内形成一第一N型嵌入层与一P型外延层;接下来,在一具有N型导电离子的第一N型扩散区形成一第一N型阱于该第一N型嵌入层内;然后,在一具有P型导电离子的第一P型扩散区形成一第一P型区域于该第一N型阱内;接续,在一具有N+型导电离子的第一漏极扩散区形成一第一漏极区域于该第一N型扩散区内;然后,在一具有N+型导电离子的第一源极扩散区形成一第一源极区域,其中于该第一源极区域与该第一漏极区域间形成一第一沟道。
接下来,在一具有P+型导电离子的第一接点扩散区形成一第一接点区域,其中该第一P型扩散区将该第一源极区域与该第一接点区域包围起来;然后,在一具有P型导电离子的多个分离的P型扩散区形成多个分离的P型区域于该P型外延层内,以提供隔离特性;接着,形成一第一薄栅氧化层与一第一厚场氧化层于该P型衬底上;接下来,置放一第一栅极于该第一薄栅氧化层与该第一厚场氧化层之上,用以控制该第一沟道内的电流量;然后,覆盖一硅氧化绝缘层于该第一栅极与该第一厚场氧化层上;接续,形成一第一漏极金属接点,其具有一与该第一漏极扩散区相连接的第一金属电极;然后,形成一第一源极金属接点,其具有一连接至该第一源极扩散区与该第一接点扩散区的第二金属电极;最后,形成一存在于该第一厚场氧化层与该第一P型区域间的第一间隙,借以提高该N型金属氧化物半导体场效晶体管的击穿电压。
根据本发明的N型金属氧化物半导体场效晶体管的制作方法,其中位于该第一N型阱内的该第一P型区域是通过一P型阱制造过程制得。
根据本发明的N型金属氧化物半导体场效晶体管的制作方法,其中位于该第一N型阱内的该第一P型区域是通过一P型基体制造过程制得。
再者,一P型金属氧化物半导体场效晶体管的制作方法包括有:首先,形成一P型衬底;接着,于该P型衬底内形成一第二N型嵌入层与一P型外延层;接下来,在一具有N型导电离子的第二N型扩散区形成一第二N型阱于该第二N型嵌入层内;然后,在一具有P型导电离子的第二P型扩散区形成一第二P型区域于该第二N型阱内;接续,在一具有P+型导电离子的第二漏极扩散区形成一第二漏极区域于该第二P型扩散区内;然后,在一具有P+型导电离子的第二源极扩散区形成一第二源极区域,其中于该第二源极区域与该第二漏极区域间形成一第二沟道。
接下来,在一具有N+型导电离子的第二接点扩散区形成一第二接点区域,其中该第二N型扩散区将该第二源极区域与该第二接点区域包围起来;然后,在一具有P型导电离子的数个分离的P型扩散区形成多个分离的P型区域于该P型外延层内,以提供隔离特性;接着,形成一第二薄栅氧化层与一第二厚场氧化层于该P型衬底上;接下来,置放一第二栅极于该第二薄栅氧化层与该第二厚场氧化层之上,用以控制该第二沟道内的电流量;然后,覆盖一硅氧化绝缘层于该第二栅极与该第二厚场氧化层上;接续,形成一第二漏极金属接点,其具有一与该第二漏极扩散区相连接的第三金属电极;然后,形成一第二源极金属接点,其具有一连接至该第二接点扩散区与该第二源极扩散区的第四金属电极;最后,形成一存在于该第二厚场氧化层与该第二N型阱间的第二间隙,借以提高该P型金属氧化物半导体场效晶体管的击穿电压。
根据本发明的P型金属氧化物半导体场效晶体管的制作方法,其中位于该第二N型阱内的该第二P型区域是通过一P型阱制造过程制得。
根据本发明的P型金属氧化物半导体场效晶体管的制作方法,其中位于该第二N型阱内的该第二P型区域是通过一P型基体制造过程制得。
本发明不需要传统制造过程中制造外延层的额外光掩模数,仅利用标准的阱结构,便能达到成本、高良率与隔离的晶体管结构。并且仅利用此一简化的制造过程,便能达到高击穿电压、低导通阻抗、与隔离结构的特性,进而达成单片IC集成的目标。
为了能更进一步了解本发明为达成预定目的所采取的技术、手段及功效,请参阅以下有关本发明的详细说明与附图,相信本发明的目的、特征与特点,当可由此得一深入且具体的了解,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图说明
图1:N型金属氧化物半导体场效晶体管的电路示意图;
图2:P型金属氧化物半导体场效晶体管的电路示意图;
图3:公知金属氧化物半导体场效晶体管的结构剖面图;
图4:本发明的金属氧化物半导体场效晶体管的区域示意俯视图;
图5:本发明的金属氧化物半导体场效晶体管的结构示意剖视图;
图6:本发明N型金属氧化物半导体场效晶体管的制作方法的流程图;以及
图7:本发明P型金属氧化物半导体场效晶体管的制作方法的流程图。
其中,附图标记说明如下:
10 N型金属氧化物半导体场效晶体管
20 漏极
21 具有N型导电离子的第一N型扩散区
22 具有P型导电离子的第一P型扩散区
23 具有N+型导电离子的第一漏极扩散区
24 具有N+型导电离子的第一源极扩散区
25 具有P+型导电离子的第一接点扩散区
30 源极
40 栅极
41 具有N型导电离子的第二N型扩散区
42 具有P型导电离子的第二P型扩散区
43 具有P+型导电离子的第二漏极扩散区
44 具有P+型导电离子的第二源极扩散区
45 具有N+型导电离子的第二接点扩散区
50 P型金属氧化物半导体场效晶体管
60 漏极
70 源极
80 栅极
90 P型外延层
100 P型衬底
101 第一N型嵌入层
102 第二N型嵌入层
160 具有P型导电离子的分离的P型扩散区
210 第一N型阱
220 第一P型区域
230 第一漏极区域
240 第一源极区域
250 第一接点区域
260 分离的P型区域
410 第二N型阱
420 第二P型区域
430 第二漏极区域
440 第二源极区域
450 第二接点区域
500 具有P+型离子的分离P+区域
510 第一薄栅氧化层
520 第二薄栅氧化层
530 第一厚场氧化层
531 第三厚场氧化层
540 第二厚场氧化层
541 第四厚场氧化层
550 第一栅极
560 第二栅极
600 硅氧化绝缘层
660 N型外延层
680 N型外延层
710 具有金属电极的第一漏极金属接点
720 具有金属电极的第二漏极金属接点
750 具有金属电极的第一源极金属接点
760 具有金属电极的第二源极金属接点
860 N+型嵌入层
880 P+型嵌入层
810 第一间隙
820 第二间隙
具体实施方式
请参阅图4及图5所示,其为本发明的金属氧化物半导体场效晶体管的区域示意俯视图及结构示意剖视图。由图中可知,本发明提供一N型金属氧化物半导体场效晶体管10,其至少包括有:一P型衬底100、一第一N型嵌入层(buried layer)101与一P型外延层(epitaxial layer)90置于该P型衬底100内、一具有N型导电离子的第一N型扩散区21于该第一N型嵌入层101内形成一第一N型阱210、一具有P型导电离子的第一P型扩散区22于该第一N型阱210中形成一第一P型区域220、一具有N+型导电离子的第一漏极扩散区23在该第一N型扩散区21中形成一第一漏极区域230、一具有N+型导电离子的第一源极扩散区24形成一第一源极区域240、一第一沟道于该第一源极区域240与该第一漏极区域230间形成、以及一具有P+型导电离子的第一接点扩散区25形成一第一接点区域250。其中该第一N型扩散区21将该第一源极区域240与该第一接点区域250包围起来。该N型场效晶体管10还包含有多个分离的P型扩散区160,以在该P型外延层90中形成多个分离的P型区域260,用以作为金属氧化物半导体场效晶体管间的隔离。
另外,本发明提供一P型金属氧化物半导体场效晶体管50,其也包括该P型衬底100、一第二N型嵌入层102与该P型外延层90置于该P型衬底100内、一具有N型导电离子的第二N型扩散区41在该第二N型嵌入层102中形成一第二N型阱410、一具有P型导电离子的第二P型扩散区42在该第二N型阱410中形成一第二P型区域420、一具有P+型导电离子的第二漏极扩散区43在该第二P型扩散区42中形成一第二漏极区域430、一具有P+型导电离子的第二源极扩散区44形成一第二源极区域440、一第二沟道于该第二源极区域440与该第二漏极区域430间形成、以及一具有N+型导电离子的第二接点扩散区45形成一第二接点区域450。其中该第二N型扩散区41则将该第二源极区440与该第二接点区域450包围起来。该N型场效晶体管10还包含具有P型导电离子的多个分离的P型扩散区160,以在该P型外延层90中形成多个分离的P型区域260,作为金属氧化物半导体场效晶体管间的隔离。
再者,该第一P型区域220与该第二P型区域420的制造过程可以是P型阱(P-Well)也可以是P型基体(P Body/Base)。其中,当该第一P型区域220与该第二P型区域420为P型基体时,该第一N型阱210与该第二N型阱410为N型阱(N-Well);当该第一P型区域220与该第二P型区域420为P型阱时,该第一N型阱210与该第二N型阱410为深N型阱(DeepN-Well)。以浓度而言,基体(Body/Base)大于阱(Well),阱又大于深阱(Deep Well)。
另外,一第一薄栅氧化层510与一第二薄栅氧化层520、一第一厚场氧化层530、一第二厚场氧化层540、一第三厚场氧化层531、一第四厚场氧化层541形成于该P型衬底100上,一第一栅极550置于该第一薄栅氧化层510与该第一厚场氧化层530之上,用以控制该N型金属氧化物半导体场效晶体管10的该第一沟道的电流量,一第二栅极560置于该第二薄栅氧化层520与该第二厚场氧化层540之上,用以控制该P型金属氧化物半导体场效晶体管50的该第二沟道的电流量,一硅氧化绝缘层600覆盖于该栅极550与560以及厚场氧化层530、531、540与541上,具有金属电极的一第一漏极金属接点710与一第二漏极金属接点720分别与该第一漏极扩散区23及该第二漏极扩散区43相连接,一具有金属电极的第一源极金属接点750与该第一源极扩散区24与该第一接点扩散区25相连接,一具有金属电极的第二源极金属接点760与该第二源极扩散区44及该第二接点扩散区45相连接。
再者,一第一间隙810存在于该第一厚场氧化层530与该第一P型区域220间,以提高该N型金属氧化物半导体场效晶体管10的击穿电压,一第二间隙820存在于该第二厚场氧化层540与该第二N型阱410间,以提高该P型金属氧化物半导体场效晶体管50的击穿电压,该第一P型区域220与该第一N型阱210产生一耗尽区,该第二P型区域420与该第二N型阱410产生另一耗尽区,加上该P型区域260,使得晶体管之间的隔离效果更佳。
请参阅图6所示,其为本发明N型金属氧化物半导体场效晶体管的制作方法的流程图。由流程图可知,该N型金属氧化物半导体场效晶体管的制作方法包括有:首先,形成一P型衬底100(S100);接着,于该P型衬底100内形成一第一N型嵌入层101与一P型外延层90(S102);接下来,在一具有N型导电离子的第一N型扩散区21形成一第一N型阱210于该第一N型嵌入层101内(S104);然后,在一具有P型导电离子的第一P型扩散区22形成一第一P型区域220于该第一N型阱210内(S106);接续,在一具有N+型导电离子的第一漏极扩散区23形成一第一漏极区域230于该第一N型扩散区21内(S108);然后,在一具有N+型导电离子的第一源极扩散区24形成一第一源极区域240(S110),其中于该第一源极区域240与该第一漏极区域230间形成一第一沟道。
接下来,在一具有P+型导电离子的第一接点扩散区25形成一第一接点区域250(S112),其中该第一P型扩散区22将该第一源极区域240与该第一接点区域250包围起来;然后,在一具有P型导电离子的多个分离的P型扩散区160形成多个分离的P型区域260于该P型外延层90内,以提供隔离特性(S114);接着,形成一第一薄栅氧化层510与一第一厚场氧化层530于该P型衬底100上(S116);接下来,置放一第一栅极550于该第一薄栅氧化层510与该第一厚场氧化层530之上,用以控制该第一沟道内的电流量(S118);然后,覆盖一硅氧化绝缘层600于该第一栅极550与该第一厚场氧化层530上(S120);接续,形成一第一漏极金属接点710,其具有一与该第一漏极扩散区23相连接的第一金属电极(S122);然后,形成一第一源极金属接点750,其具有一连接至该第一源极扩散区24与该第一接点扩散区25的第二金属电极(S124);最后,形成一存在于该第一厚场氧化层530与该第一P型区域220间的第一间隙810,借以提高该N型金属氧化物半导体场效晶体管的击穿电压(S126)。
请参阅图7所示,其为本发明P型金属氧化物半导体场效晶体管的制作方法的流程图。由流程图可知,该P型金属氧化物半导体场效晶体管的制作方法包括有:首先,形成一P型衬底100(S200);接着,于该P型衬底100内形成一第二N型嵌入层102与一P型外延层90(S202);接下来,在一具有N型导电离子的第二N型扩散区41形成一第二N型阱410于该第二N型嵌入层102内(S204);然后,在一具有P型导电离子的第二P型扩散区42形成一第二P型区域420于该第二N型阱410内(S206);接续,在一具有P+型导电离子的第二漏极扩散区43形成一第二漏极区域430于该第二P型扩散区42内(S208);然后,在一具有P+型导电离子的第二源极扩散区44形成一第二源极区域440(S210),其中于该第二源极区域440与该第二漏极区域430间形成一第二沟道。
接下来,在一具有N+型导电离子的第二接点扩散区45形成一第二接点区域450(S212),其中该第二N型扩散区41将该第二源极区域440与该第二接点区域450包围起来;然后,在一具有P型导电离子的多个分离的P型扩散区160形成多个分离的P型区域260于该P型外延层90内,以提供隔离特性(S214);接着,形成一第二薄栅氧化层520与一第二厚场氧化层540于该P型衬底100上(S216);接下来,置放一第二栅极560于该第二薄栅氧化层520与该第二厚场氧化层540之上,用以控制该第二沟道内的电流量(S218);然后,覆盖一硅氧化绝缘层600于该第二栅极560与该第二厚场氧化层540上(S220);接续,形成一第二漏极金属接点720,其具有一与该第二漏极扩散区43相连接的第三金属电极(S222);然后,形成一第二源极金属接点760,其具有一连接至该第二接点扩散区45与该第二源极扩散区44的第四金属电极(S224);最后,形成一存在于该第二厚场氧化层540与该第二N型阱410间的第二间隙820,借以提高该P型金属氧化物半导体场效晶体管的击穿电压(S226)。
综上所述,传统晶体管隔离结构是采用该N型外延层660将该N型场效晶体管10的第一漏极区域230及第一P型区域220包围起来,并利用一N型外延层680将该P型场效晶体管50的第二源极区域440、第二接点区域450及第二P型区域420包围起来。本发明的场效晶体管器件,如该N型金属氧化物半导体场效晶体管10与该P型金属氧化物半导体场效晶体管50,则是利用该第一N型阱210与该第二N型阱410配合其它结构来达成隔离效果,另外本发明的优点于结构上:因利用该第一N型嵌入层101、该第二N型嵌入层102及该一P型外延层90,以加强原本仅有阱(Well)隔离结构的隔离效果;于成本上:因少了制作该N型外延层660与该N型外延层680、及该N+型嵌入层860与该P+型嵌入层880的光掩模数,而可以减少制造成本。
因此,本发明不需要传统制造过程中制造外延层的额外光掩模数,仅利用标准的阱结构,便能达到成本、高良率与隔离的晶体管结构。并且仅利用此一简化的制造过程,便能达到高击穿电压、低导通阻抗、与隔离结构的特性,进而达成单片IC集成的目标。
以上所述,仅为本发明最佳的一的具体实施例的详细说明与附图,但本发明的特征并不局限于此,并非用以限制本发明,本发明的所有范围应以所附权利要求范围为准,凡合于本发明权利要求范围的精神与其类似变化的实施例,皆应包含于本发明的范畴中,任何熟悉本领域的技术人员在本发明的领域内,可轻易思及的变化或修饰皆可涵盖在本发明的专利范围。
Claims (12)
1、一种N型金属氧化物半导体场效晶体管,包括有:
一P型衬底;
一第一N型嵌入层与一P型外延层,于该P型衬底内形成;
一具有N型导电离子的第一N型扩散区,于该第一N型嵌入层内形成一第一N型阱;
一具有P型导电离子的第一P型扩散区,于该第一N型阱内形成一第一P型区域;
一具有N+型导电离子的第一漏极扩散区,于该第一N型扩散区内形成一第一漏极区域;
一具有N+型导电离子的第一源极扩散区形成一第一源极区域,其中一第一沟道于该第一源极区域与该第一漏极区域间形成;
一具有P+型导电离子的第一接点扩散区形成一第一接点区域,其中该第一P型扩散区将该第一源极区域与该第一接点区域包围起来;
一具有P型导电离子的多个分离的P型扩散区,在该P型外延层内形成多个分离的P型区域以提供隔离特性;
一第一薄栅氧化层与一第一厚场氧化层,形成于该P型衬底上;
一第一栅极,置放于该第一薄栅氧化层与该第一厚场氧化层之上,用以控制该第一沟道内的电流量;
一硅氧化绝缘层,覆盖于该第一栅极与该第一厚场氧化层上;
一第一漏极金属接点,其具有一与该第一漏极扩散区相连接的第一金属电极;
一第一源极金属接点,其具有一连接至该第一源极扩散区与该第一接点扩散区的第二金属电极;以及
一第一间隙,存在于该第一厚场氧化层与该第一P型区域间,借以提高该N型金属氧化物半导体场效晶体管的击穿电压。
2、如权利要求1所述的该N型金属氧化物半导体场效晶体管,其特征在于位于该第一N型阱内的该第一P型区域是通过一P型阱制造过程制得。
3、如权利要求1所述的该N型金属氧化物半导体场效晶体管,其特征在于位于该第一N型阱内的该第一P型区域是通过一P型基体制造过程制得。
4、一种P型金属氧化物半导体场效晶体管,包括有:
一P型衬底;
一第二N型嵌入层与一P型外延层,于该P型衬底内形成;
一具有N型导电离子的第二N型扩散区,于该第二N型嵌入层内形成一第二N型阱;
一具有P型导电离子的第二P型扩散区,于该第二N型阱内形成一第二P型区域;
一具有P+型导电离子的第二漏极扩散区,于该第二P型扩散区内形成一第二漏极区域;
一具有P+型导电离子的第二源极扩散区形成一第二源极区域,其中一第二沟道于该第二源极区域与该第二漏极区域间形成;
一具有N+型导电离子的第二接点扩散区形成一第二接点区域,其中该第二N型扩散区将该第二源极区域与该第二接点区域包围起来;
一具有P型导电离子的多个分离的P型扩散区,在该P型外延层内形成多个分离的P型区域以提供隔离特性;
一第二薄栅氧化层与一第二厚场氧化层,形成于该P型衬底上;
一第二栅极,置放于该第二薄栅氧化层与该第二厚场氧化层之上,用以控制该第二沟道内的电流量;
一硅氧化绝缘层,覆盖于该第二栅极与该第二厚场氧化层上;
一第二漏极金属接点,其具有一与该第二漏极扩散区相连接的第三金属电极;
一第二源极金属接点,其具有一连接至该第二接点扩散区与该第二源极扩散区的第四金属电极;以及
一第二间隙,存在于该第二厚场氧化层与该第二N型阱间,借以提高该P型金属氧化物半导体场效晶体管的击穿电压。
5、如权利要求4所述的该P型金属氧化物半导体场效晶体管,其特征在于位于该第二N型阱内的该第二P型区域是通过一P型阱制造过程制得。
6、如权利要求4所述的该P型金属氧化物半导体场效晶体管,其特征在于位于该第二N型阱内的该第二P型区域是通过一P型基体制造过程制得。
7、一种N型金属氧化物半导体场效晶体管的制作方法,包括有:
形成一P型衬底;
于该P型衬底内形成一第一N型嵌入层与一P型外延层;
在一具有N型导电离子的第一N型扩散区形成一第一N型阱于该第一N型嵌入层内;
在一具有P型导电离子的第一P型扩散区形成一第一P型区域于该第一N型阱内;
在一具有N+型导电离子的第一漏极扩散区形成一第一漏极区域于该第一N型扩散区内;
在一具有N+型导电离子的第一源极扩散区形成一第一源极区域,其中于该第一源极区域与该第一漏极区域间形成一第一沟道;
在一具有P+型导电离子的第一接点扩散区形成一第一接点区域,其中该第一P型扩散区将该第一源极区域与该第一接点区域包围起来;
在一具有P型导电离子的多个分离的P型扩散区形成多个分离的P型区域于该P型外延层内,以提供隔离特性;
形成一第一薄栅氧化层与一第一厚场氧化层于该P型衬底上;
置放一第一栅极于该第一薄栅氧化层与该第一厚场氧化层之上,用以控制该第一沟道内的电流量;
覆盖一硅氧化绝缘层于该第一栅极与该第一厚场氧化层上;
形成一第一漏极金属接点,其具有一与该第一漏极扩散区相连接的第一金属电极;
形成一第一源极金属接点,其具有一连接至该第一源极扩散区与该第一接点扩散区的第二金属电极;以及
形成一存在于该第一厚场氧化层与该第一P型区域间的第一间隙,借以提高该N型金属氧化物半导体场效晶体管的击穿电压。
8、如权利要求7所述的该N型金属氧化物半导体场效晶体管的制作方法,其特征在于位于该第一N型阱内的该第一P型区域是通过一P型阱制造过程制得。
9、如权利要求7所述的该N型金属氧化物半导体场效晶体管的制作方法,其特征在于位于该第一N型阱内的该第一P型区域是通过一P型基体制造过程制得。
10、一种P型金属氧化物半导体场效晶体管的制作方法,包括有:
形成一P型衬底;
于该P型衬底内形成一第二N型嵌入层与一P型外延层;
在一具有N型导电离子的第二N型扩散区形成一第二N型阱于该第二N型嵌入层内;
在一具有P型导电离子的第二P型扩散区形成一第二P型区域于该第二N型阱内;
在一具有P+型导电离子的第二漏极扩散区形成一第二漏极区域于该第二P型扩散区内;
在一具有P+型导电离子的第二源极扩散区形成一第二源极区域,其中于该第二源极区域与该第二漏极区域间形成一第二沟道;
在一具有N+型导电离子的第二接点扩散区形成一第二接点区域,其中该第二N型扩散区将该第二源极区域与该第二接点区域包围起来;
在一具有P型导电离子的多个分离的P型扩散区形成多个分离的P型区域于该P型外延层内,以提供隔离特性;
形成一第二薄栅氧化层与一第二厚场氧化层于该P型衬底上;
置放一第二栅极于该第二薄栅氧化层与该第二厚场氧化层之上,用以控制该第二沟道内的电流量;
覆盖一硅氧化绝缘层于该第二栅极与该第二厚场氧化层上;
形成一第二漏极金属接点,其具有一与该第二漏极扩散区相连接的第三金属电极;
形成一第二源极金属接点,其具有一连接至该第二接点扩散区与该第二源极扩散区的第四金属电极;以及
形成一存在于该第二厚场氧化层与该第二N型阱间的第二间隙,借以提高该P型金属氧化物半导体场效晶体管的击穿电压。
11、如权利要求10所述的P型金属氧化物半导体场效晶体管的制作方法,其特征在于位于该第二N型阱内的该第二P型区域是通过一P型阱制造过程制得。
12、如权利要求10所述的P型金属氧化物半导体场效晶体管的制作方法,其特征在于位于该第二N型阱内的该第二P型区域是通过一P型基体制造过程制得。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005100668502A CN100449782C (zh) | 2005-04-29 | 2005-04-29 | 具隔离结构的金属氧化物半导体场效晶体管及其制作方法 |
PCT/CN2005/001687 WO2006116902A1 (fr) | 2005-04-29 | 2005-10-14 | Transistor a effet de champ en semi-conducteur d'oxyde metallique presentant une structure d'isolation et ses procedes de fabrication |
US11/913,044 US7923787B2 (en) | 2005-04-29 | 2005-10-14 | MOSFET with isolation structure and fabrication method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005100668502A CN100449782C (zh) | 2005-04-29 | 2005-04-29 | 具隔离结构的金属氧化物半导体场效晶体管及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1855537A CN1855537A (zh) | 2006-11-01 |
CN100449782C true CN100449782C (zh) | 2009-01-07 |
Family
ID=37195522
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100668502A Active CN100449782C (zh) | 2005-04-29 | 2005-04-29 | 具隔离结构的金属氧化物半导体场效晶体管及其制作方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7923787B2 (zh) |
CN (1) | CN100449782C (zh) |
WO (1) | WO2006116902A1 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7737526B2 (en) * | 2007-03-28 | 2010-06-15 | Advanced Analogic Technologies, Inc. | Isolated trench MOSFET in epi-less semiconductor sustrate |
KR101578931B1 (ko) * | 2008-12-05 | 2015-12-21 | 주식회사 동부하이텍 | 반도체 소자 및 반도체 소자의 제조 방법 |
CN102110694B (zh) * | 2009-12-29 | 2013-03-27 | 中芯国际集成电路制造(上海)有限公司 | Cmos图像传感器的制造方法及其器件结构 |
US8482066B2 (en) * | 2011-09-02 | 2013-07-09 | Macronix International Co., Ltd. | Semiconductor device |
JP5784512B2 (ja) * | 2012-01-13 | 2015-09-24 | 株式会社東芝 | 半導体装置 |
JP2014170831A (ja) | 2013-03-04 | 2014-09-18 | Seiko Epson Corp | 回路装置及び電子機器 |
JP2017139503A (ja) * | 2017-05-18 | 2017-08-10 | セイコーエプソン株式会社 | 回路装置及び電子機器 |
CN109148448B (zh) * | 2017-06-19 | 2020-09-01 | 中芯国际集成电路制造(上海)有限公司 | 一种cmos反相器和电子装置 |
US20220285497A1 (en) * | 2019-12-30 | 2022-09-08 | Unist(Ulsan National Institute Of Science And Technology) | Transistor, ternary inverter comprising same, and transistor manufacturing method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5548147A (en) * | 1994-04-08 | 1996-08-20 | Texas Instruments Incorporated | Extended drain resurf lateral DMOS devices |
US5852314A (en) * | 1995-05-02 | 1998-12-22 | SGS--Thomson Microelectronics S.r.l. | Thin epitaxy resurf integrated circuit containing high voltage p-channel and n-channel devices with source or drain not tied to ground |
CN1079996C (zh) * | 1995-12-02 | 2002-02-27 | Lg半导体株式会社 | 高压金属氧化物硅场效应晶体管结构 |
CN2842736Y (zh) * | 2005-04-30 | 2006-11-29 | 崇贸科技股份有限公司 | 具有隔离结构的金属氧化物半导体场效应晶体管 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5104076A (en) * | 1990-10-15 | 1992-04-14 | Goodall Jr James M | Article holder |
WO2002095833A1 (en) * | 2001-05-15 | 2002-11-28 | Virtual Silicon Technology, Inc. | High voltage n-channel ldmos devices built in a deep submicron cmos process |
JP4437388B2 (ja) * | 2003-02-06 | 2010-03-24 | 株式会社リコー | 半導体装置 |
US7262471B2 (en) * | 2005-01-31 | 2007-08-28 | Texas Instruments Incorporated | Drain extended PMOS transistor with increased breakdown voltage |
-
2005
- 2005-04-29 CN CNB2005100668502A patent/CN100449782C/zh active Active
- 2005-10-14 WO PCT/CN2005/001687 patent/WO2006116902A1/zh active Application Filing
- 2005-10-14 US US11/913,044 patent/US7923787B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5548147A (en) * | 1994-04-08 | 1996-08-20 | Texas Instruments Incorporated | Extended drain resurf lateral DMOS devices |
US5852314A (en) * | 1995-05-02 | 1998-12-22 | SGS--Thomson Microelectronics S.r.l. | Thin epitaxy resurf integrated circuit containing high voltage p-channel and n-channel devices with source or drain not tied to ground |
CN1079996C (zh) * | 1995-12-02 | 2002-02-27 | Lg半导体株式会社 | 高压金属氧化物硅场效应晶体管结构 |
CN2842736Y (zh) * | 2005-04-30 | 2006-11-29 | 崇贸科技股份有限公司 | 具有隔离结构的金属氧化物半导体场效应晶体管 |
Also Published As
Publication number | Publication date |
---|---|
CN1855537A (zh) | 2006-11-01 |
US20080290410A1 (en) | 2008-11-27 |
WO2006116902A1 (fr) | 2006-11-09 |
US7923787B2 (en) | 2011-04-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100449782C (zh) | 具隔离结构的金属氧化物半导体场效晶体管及其制作方法 | |
CN100334742C (zh) | 具有一分开井结构的隔离的高电压ldmos晶体管 | |
US8304830B2 (en) | LDPMOS structure for enhancing breakdown voltage and specific on resistance in biCMOS-DMOS process | |
US8957473B2 (en) | MOS-gated power devices, methods, and integrated circuits | |
US7187033B2 (en) | Drain-extended MOS transistors with diode clamp and methods for making the same | |
EP2860762B1 (en) | High voltage junction field effect transistor | |
US20080070369A1 (en) | MOS transistor device structure combining Si-trench and field plate structures for high voltage device | |
KR100962233B1 (ko) | 고전압 접합형 전계효과 트랜지스터 | |
JP5098026B2 (ja) | 高圧nmosトランジスタの製造方法 | |
JP2001352070A (ja) | 半導体装置およびその製造方法 | |
US6888210B2 (en) | Lateral DMOS transistor having reduced surface field | |
WO2015093052A1 (ja) | 半導体装置 | |
US7851883B2 (en) | Semiconductor device and method of manufacture thereof | |
CN1866542B (zh) | 具有隔离结构的mos场效应晶体管及其制作方法 | |
KR20060106667A (ko) | 고내압 반도체장치 및 그 제조방법 | |
TWI740719B (zh) | 高壓半導體裝置 | |
KR20090070513A (ko) | 반도체 소자 및 그 제조방법 | |
CN109817719B (zh) | Nldmos器件及其制造方法 | |
JP2014207324A (ja) | 半導体装置及びその製造方法 | |
CN2842736Y (zh) | 具有隔离结构的金属氧化物半导体场效应晶体管 | |
CN2821868Y (zh) | 具有隔离结构的mos场效应晶体管 | |
JP3904725B2 (ja) | 半導体装置及びその製造方法 | |
JP2007150125A (ja) | 半導体装置およびそれの製造方法 | |
KR100482950B1 (ko) | 반도체소자 및 그 제조방법 | |
US20060220170A1 (en) | High-voltage field effect transistor having isolation structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |