CN100334742C - 具有一分开井结构的隔离的高电压ldmos晶体管 - Google Patents

具有一分开井结构的隔离的高电压ldmos晶体管 Download PDF

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CN100334742C
CN100334742C CNB2004100551829A CN200410055182A CN100334742C CN 100334742 C CN100334742 C CN 100334742C CN B2004100551829 A CNB2004100551829 A CN B2004100551829A CN 200410055182 A CN200410055182 A CN 200410055182A CN 100334742 C CN100334742 C CN 100334742C
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黄志丰
杨大勇
林振宇
简铎欣
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Fairchild Taiwan Corp
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Abstract

本发明为一种具有一分开井结构的隔离的高电压LDMOS晶体管，包含在N型井区中的漏极延伸区域内形成的分离的P型井区，在N型井区的漏极延伸区域内的P型井区被分开，以在N型井区形成一分开的接面场效(splitjunction-field)，分开的N型井区与P型井区使漂移区空乏，而将电场的极大值转移至N型井区，如此可达到较高的崩溃电压(breakdown voltage)，并且容许N型井区具有较高的掺杂浓度。此外，本发明所揭示的LDMOS包含一内嵌于源极(source)扩散区之下的N型井区，使得源极区具有低阻抗的路径，以限制漏极与源极之间的晶体管电流。

Description

具有一分开井结构的隔离的高电压LDMOS晶体管
技术领域
本发明涉及一种半导体组件，尤指一种横向功率金氧半场效应晶体管(lateral power MOSFET)。
背景技术
在功率集成电路的发展中，为了将功率开关以及控制电路整合在一起而开发的单芯片制程，尤其是目前用于制作单石集成电路(monolithic IC)的横向二次扩散金氧半导体(lateral double diffusion MOS，LDMOS)制程，为一主流的趋势，LDMOS制程是于半导体基板的表面进行平面扩散(planar diffusion)以便形成横向的主要电流路径，由于横向MOSFET是以典型的IC制程所制造，因此控制电路与横向功率MOSFET可以整合在一个单石电源IC上，LDMOS制程采用表面电场缩减(reduced surface electric field，RESURF)技术与低厚度磊晶(EPI)或N型井区(N-well)，可以达到高电压与低导通阻抗的目标。
近来，业界提出许多整合控制电路与功率开关的LDMOS设计方式，其中有许多与高电压LDMOS有关。
这些公知技术都有一个缺点，那就是晶体管的电场极大值(electric fieldmaximum)发生在靠近硅表面，在高温操作时会造成可靠度问题，这些半导体技术还有一个缺点为其非隔离的源极结构，在单石集成电路设计中，非隔离的晶体管电流可能会在基板中流动，产生噪声干扰控制电路。
为了克服这些缺点，本发明提出一种具有一分离井结构(split wellstructure)的隔离的(isolated)高电压横向二次扩散金氧半导体(LDMOS)晶体管。
发明内容
本发明要解决的技术问题是：提供一种具有一分开井结构的隔离的(isolated)高电压横向二次扩散金氧半导体(LDMOS)晶体管，主要用以控制电流的流动，可提高晶体管的可靠性。
本发明的技术解决方案是：一种具有一分开井结构的隔离的(isolated)高电压横向二次扩散金氧半导体(LDMOS)晶体管包括：
一P型基板(P-Substrate)；
一具有N型导电离子(conductivity-type)的第一扩散区(first diffusionregion)与第二扩散区，其中该第一扩散区与该第二扩散区于该P型基板内形成一N型井区(N-well)，而其中该第一扩散区形成一漏极延伸区(extended drainregion)；
一漏极扩散区(drain diffusion region)，用以形成一漏极区，该漏极扩散区具有N+型导电离子，其中该漏极区位于该漏极延伸区内；
一第三扩散区，用以于该N型井区的该漏极延伸区内形成一P型井区，该第三扩散区具有P型导电离子；
一源极扩散区(source diffusion region)，用以形成一源极区，该源极扩散区具有N+型导电离子，其中一传导通道穿过该N型井区，而其中该传导通道连接该源极区与该漏极区；
一接点扩散区(contact diffusion region)，用以形成一接点区，该接点扩散区具有N+型导电离子；以及
一第四扩散区，用以形成一隔离的P型井区以防止崩溃，该第四扩散区具有P型导电离子，其中该隔离的P型井区位于该第二扩散区以将该源极区与该接点区围起，其中由该第二扩散区形成的N型井区为该源极区提供一低阻抗路径，而其中该第二扩散区形成的N型井区限制该漏极区与该源极区之间的一晶体管电流。
如上所述的具有一分开井结构的隔离的高电压LDMOS晶体管，其中该漏极延伸区与该漏极扩散区形成一漏极电极。
如上所述的具有一分开井结构的隔离的高电压LDMOS晶体管，其中该隔离的P型井区、该源极扩散区、以及该接点扩散区形成一源极电极。
如上所述的具有一分开井结构的隔离的高电压LDMOS晶体管，其中该N型井区由漏极电极延伸至源极电极。
如上所述的具有一分开井结构的隔离的高电压LDMOS晶体管，其中该P型井区将该N型井区分开。
如上所述的具有一分开井结构的隔离的高电压LDMOS晶体管更包括：一薄闸极氧化层(thin gate oxide)与厚场氧化层(thick field oxide)，于该P型基板上形成；一多晶硅闸极(polysilicon gate electrode)，用以控制该传导信道的该晶体管电流，其中该多晶硅闸极置放在该薄闸极氧化层与该厚场氧化层的区域之上；一漏极间隙(drain-gap)，用以在该漏极扩散区与该厚场氧化层之间维持一空间；一源极间隙(source-gap)，用以在该厚场氧化层与该隔离的P型井区之间维持一空间，其中该漏极间隙与该源极间隙的适当配置可实质上助于提升该隔离的高电压LDMOS晶体管的崩溃电压；一二氧化硅(silicondioxide)绝缘层，覆盖于该多晶硅闸极与该厚场氧化层之上；一漏极金属接点，具有一金属电极以接触该漏极扩散区；以及一源极金属接点，具有一金属电极以接触该源极扩散区与该接点扩散区。
如上所述的具有一分开井结构的隔离的高电压LDMOS晶体管，其中该P型井区将位于该N型井区中的该漏极延伸区分开，以于该N型井区形成一分开的接面场效(split junction-field)，其中该分开的N型井区与该P型井区使一漂移区空乏。
本发明的特点和优点是：本发明的隔离的高电压横向二次扩散金氧半晶体管(LDMOS Transistor)形成于P型基板(P-substrate)之上，具有N型导电离子的第一扩散区与第二扩散区于P型基板内形成一N型井区(N-well)，而第一扩散区同样也形成一漏极延伸区(extended drain region)；具有N+型导电离子的漏极扩散区在漏极延伸区内形成一漏极区；具有P型导电离子的第三扩散区于漏极延伸区内分别形成一P型井区。
具有N+型导电离子的源极扩散区形成一源极区；具有P+导电离子的接点扩散区形成一接点区；具有P型导电离子的第四扩散区形成一隔离的P型井区以防止崩溃，其中隔离的P型井区位于第二扩散区将源极区与接点区围起，
传导信道穿过N型井区，用以连接源极区与漏极区，一多晶硅闸极内嵌于导电通道之上以控制晶体管电流。
P型井区位于N型井区的漏极延伸区之内，用以于N型井区内形成一分开的接面场效(split junction-field)，分开的N型井区与P型井区使漂移区(driftregion)空乏，而该漂移区将电场极大值转移至N型井区的区域内，如此可达到较高的崩溃电压(breakdown voltage)，并且容许N型井区具有较高的掺杂浓度。此外，由第二扩散区形成的N型井区为源极区提供一低阻抗路径，以限制漏极与源极之间的晶体管电流。本发明利用分开井结构，将电场扩展至晶体管的主体，这样可实质地提高晶体管的可靠性。
附图说明
图1为根据本发明的实施例的一高电压LDMOS晶体管的俯视图。
图2为根据本发明的实施例的一高电压LDMOS晶体管的第一剖面图，其中显示一分开的P型井区。
图3为根据本发明的实施例的一高电压LDMOS晶体管的第二剖面图，其中显示一分开的N型井区。
图4为根据本发明的实施例的一高电压LDMOS晶体管的第三剖面图，其中显示分开的N型井区与P型井区。
附图标号说明：
100、高电压LDMOS晶体管  10、漏极      12、焊垫
15、漏极金属接点        20、源极      22、焊垫
25、源极金属接点        30、N型井区   33、第一扩散区
37、第二扩散区      40、多晶硅闸极     42、焊垫
50、漏极延伸区      52、漏极区         53、漏极扩散区
55、源极扩散区      56、源极区         57、接点扩散区
58、接点区          60、P型井区        63、第三扩散区
65、P型井区         67、第四扩散区     71、漏极间隙
72、源极间隙        81、薄闸极氧化层   85、二氧化硅绝缘层
86、二氧化硅绝缘层  87、厚场氧化层     88、厚场氧化层
90、P型基板
具体实施方式
要注意的是，以上的概述与接下来的详细说明皆为示范性质，是为了进一步说明本发明的申请专利范围，而有关本发明的其它特点与优点，将在后续的说明加以阐述。
图1所示为根据本发明的较佳实施例的一高电压LDMOS晶体管100的俯视图，根据本发明，LDMOS晶体管100包含一N型井区30与分开的P型井区60。
LDMOS晶体管100更包含一漏极电极10、一源极电极20、以及一多晶硅闸极(Dolysilicon gate electrode)40，还有漏极电极10所用的焊垫(bonding pad)12、源极电极20所用的焊垫22、以及多晶硅闸极40所用的焊垫42，P型井区60将N型井区30分开，N型井区30由漏极电极10延伸至源极电极20。
图2为根据本发明的较佳实施例的高电压LDMOS晶体管100的第一剖面图，LDMOS晶体管100位于如图1所示的源极电极20与漏极电极10之间，该第一剖面图结构是沿着图1中的W-V虚线线段切开，图3所示则为第二剖面图，第二剖面结构是沿着图1中的X-Y虚线线段切开。
LDMOS晶体管100形成于P型基板90之上，具有N型导电离子的第一扩散区33与具有N型导电离子的第二扩散区37内嵌于P型基板90内形成N型井区30，而第一扩散区33也同样在第一扩散区33的区域内形成漏极延伸区50；具有N+型导电离子的漏极扩散区53于漏极延伸区50内形成漏极区52。
具有P型导电离子的第三扩散区63形成P型井区60，而第三扩散区63分别地位于漏极延伸区50内。
具有N+型导电离子的源极扩散区55形成一源极区56；具有P+型导电离子的接点扩散区57形成一接点区58；具有P型导电离子的第四扩散区67形成一隔离的P型井区65以防止崩溃，其中隔离的P型井区65位于第二扩散区37将源极区56与接点区58围起。
一传导通道穿过N型井区30，用以连接源极区56与漏极区52，一薄闸极氧化层(thin gate oxide)81与厚场氧化层(thick field oxide)87形成于P型基板90之上；多晶硅闸极(polysilicon gate electrode)40位于薄闸极氧化层81与厚场氧化层87的区域之上，以控制传导通道的晶体管电流。一漏极间隙(drain gap)71用以在漏极扩散区53与厚场氧化层87之间维持一空间，源极间隙(source-gap)72用以在厚场氧化层87与隔离的P型井区65之间维持一空间，漏极间隙71与源极间隙72的适当配置可实质上助于提升LDMOS晶体管100的崩溃电压。
二氧化硅(silicon dioxide)绝缘层85与二氧化硅绝缘层86覆盖于多晶硅闸极40、厚场氧化层87与厚场氧化层88之上，漏极金属接点15具有金属电极作用，用以接触漏极扩散区53，源极金属接点25亦具有金属电极的作用，以接触源极扩散区55与接点扩散区57。
参考图1与图2，漏极延伸区50与漏极扩散区53共同形成漏极10，而隔离的P型井区65、源极扩散区55、以及接点扩散区57共同形成源极20，焊垫12连接至漏极金属接点15，焊垫22连接至源极金属接点25，焊垫42连接至多晶硅闸极40。
图4为LDMOS晶体管100的第三剖面图，其中第三剖面图结构是沿着图1的P-Q虚线线段切开，P型井区60位于漏极延伸区50内，以便在N型井区30内形成一分开的接面场效(split junction-field)，其中分开的N型井区30与P型井区60使一漂移区空乏，而该漂移区则将电场极大值扩展至N型井区30的区域内。当该漂移区完全空乏时，传导信道实质上就比较不易崩溃，为了要让LDMOS晶体管100具有高崩溃电压，漏极延伸区50必须在崩溃发生前完全空乏，分开的N型井区30与P型井区60使得漏极延伸区50能够在崩溃前被空乏，尽管漂移区为高掺杂浓度亦同。此外，每一个分开的接面场效可进一步分散电场。
LDMOS晶体管100的空乏区会延伸到传导通道之外，空乏区的面积实质上从N型井区30与P型井区60的垂直接面之上一直延伸到N型井区30与P型基板90的界限之下，如此一来可允许漂移区具备高掺杂浓度与低电阻，为了让LDMOS晶体管100可同时具备低阻抗和高崩溃电压的特性，必须适当地选择分开的N型井区30与P型井区60的宽度与掺杂浓度。
此外，由第二扩散区37形成的N型井区30为源极区56提供一低阻抗路径，被以限制漏极区52与源极区56之间的晶体管电流。
虽然本发明已以具体实施例揭示，但其并非用以限定本发明，任何本领域的技术人员，在不脱离本发明的构思和范围的前提下所作出的等同组件的置换，或依本发明专利保护范围所作的等同变化与修饰，皆应仍属本专利涵盖之范畴。

Claims (7)

1.一种具有一分开井结构的隔离的高电压横向二次扩散MOS晶体管，其特征在于，包括：
一P型基板；
一具有N型导电离子的第一扩散区与第二扩散区，其中该第一扩散区与该第二扩散区于该P型基板内形成一N型井区，而其中该第一扩散区形成一漏极延伸区；
一漏极扩散区，用以形成一漏极区，该漏极扩散区具有N+型导电离子，其中该漏极区位于该漏极延伸区内；
一第三扩散区，用以于该N型井区的该漏极延伸区内形成一P型井区，该第三扩散区具有P型导电离子；
一源极扩散区，用以形成一源极区，该源极扩散区具有N+型导电离子，其中一传导通道穿过该N型井区，而其中该传导通道连接该源极区与该漏极区；
一接点扩散区，用以形成一接点区，该接点扩散区具有N+型导电离子；以及
一第四扩散区，用以形成一隔离的P型井区以防止崩溃，该第四扩散区具有P型导电离子，其中该隔离的P型井区位于该第二扩散区以将该源极区与该接点区围起，其中由该第二扩散区形成的N型井区为该源极区提供一低阻抗路径，而其中该第二扩散区形成的N型井区限制该漏极区与该源极区之间的一晶体管电流。
2.如权利要求1所述的具有一分开井结构的隔离的高电压横向二次扩散MOS晶体管，其特征在于，该漏极延伸区与该漏极扩散区形成一漏极电极。
3.如权利要求1所述的具有一分开井结构的隔离的高电压横向二次扩散MOS晶体管，其特征在于，该隔离的P型井区、该源极扩散区、以及该接点扩散区形成一源极电极。
4.如权利要求1所述的具有一分开井结构的隔离的高电压横向二次扩散MOS晶体管，其特征在于，该N型并区由漏极电极延伸至源极电极。
5.如权利要求1所述的具有一分开井结构的隔离的高电压横向二次扩散MOS晶体管，其特征在于，该P型井区将该N型井区分开。
6.如权利要求1所述的具有一分开井结构的隔离的高电压横向二次扩散MOS晶体管，其特征在于，所述晶体管更包括：
一薄闸极氧化层与厚场氧化层，形成于该P型基板上；
一多晶硅闸极，用以控制该传导通道的该晶体管电流，其中该多晶硅闸极置放在该薄闸极氧化层与该厚场氧化层的区域之上；
一漏极间隙，用以在该漏极扩散区与该厚场氧化层之间维持一空间；
一源极间隙，用以在该厚场氧化层与该隔离的P型井区之间维持一空间，其中该漏极间隙与该源极间隙的适当配置有助于提升该隔离的高电压横向二次扩散MOS晶体管的崩溃电压；
一二氧化硅绝缘层，覆盖于该多晶硅闸极与该厚场氧化层之上；
一漏极金属接点，具有一金属电极以接触该漏极扩散区；以及
一源极金属接点，具有一金属电极以接触该源极扩散区与该接点扩散区。
7.如权利要求1所述的具有一分开井结构的隔离的高电压横向二次扩散MOS晶体管，其特征在于，该P型井区将位于该N型井区中的该漏极延伸区分开，以于该N型井区形成一分开的接面场效，其中该分开的N型井区与该P型井区使一漂移区空乏。
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