CN103199109A - 一种nldmos器件及其制造方法 - Google Patents

一种nldmos器件及其制造方法 Download PDF

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CN103199109A
CN103199109A CN2012100051199A CN201210005119A CN103199109A CN 103199109 A CN103199109 A CN 103199109A CN 2012100051199 A CN2012100051199 A CN 2012100051199A CN 201210005119 A CN201210005119 A CN 201210005119A CN 103199109 A CN103199109 A CN 103199109A
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trap
dusts
nldmos
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段文婷
刘冬华
石晶
胡君
董金珠
韩峰
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

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Abstract

本发明公开了一种NLDMOS器件包括：P型衬底上部并列形成有P阱和N阱，P阱和N阱上部分别形成有N+区，N阱中N+区的旁侧形成有长氧区，场氧形成于P阱、N阱和长氧区的上方，场氧上方形成有多晶硅层，隔离侧墙形成于场氧和多晶硅层的两侧；其中，P型衬底将所述P阱和N阱隔离。本发明还公开了一种NLDMOS器件的制造方法。NLDMOS器件采用P阱作为本地区，N阱作为N漂移区，其他所有工艺条件(比如源和漏)与此5伏CMOS工艺相同。本发明的NLDMOS器件通过控制NLDMOS中的P型本底区(由P阱构成)和N漂移区(由N阱构成)的距离，实现对耐压的调整，能使NLDMOS器件的最高击穿电压达到25伏特以上。

Description

一种NLDMOS器件及其制造方法
技术领域
本发明涉及半导体制造领域，特别是涉及一种NLDMOS器件。本发明还涉及一种NLDMOS器件的制造方法。
背景技术
DMOS与CMOS器件结构类似，也有源、漏、栅等电极，但是漏端击穿电压高。DMOS主要有两种类型，垂直扩散金属氧化物半导体场效应管VDMOSFET和横向扩散金属氧化物半导体场效应管LDMOSFET。在高压功率集成电路中常采用高压LDMOS满足耐高压、实现功率控制等方面的要求，常用于射频功率电路。LDMOS与晶体管相比，在关键的器件特性方面，如增益、线性度、开关性能、散热性能以及减少级数等方面优势很明显。LDMOS由于更容易与CMOS工艺兼容而被广泛采用。
在BCD工艺中，DMOS虽然与CMOS集成在同一块芯片中，但由于高耐压和低导通电阻的要求，DMOS的本底区和漂移区的条件往往无法与CMOS现有的工艺条件共享。其主要原因是，DMOS在高耐压的情况下，需要漂移区的掺杂浓度低，从而实现在漏端有高压偏置时，漂移区全部耗尽来增加漏端到本底之间的耗尽区宽度来分压，并产生平坦的电场分布，使一次击穿电压得以提高。CMOS的要求则是P阱(相对于NMOS)或N阱(相对于PMOS)的浓度要高，这样可以提高器件与器件之间的隔离耐压和抑制Latch-up(闩锁)效应。如图1所示，一种现有的NLDMOS器件，其耐压主要受P阱与N阱之间形成的PN结击穿电压所限制，其耐压能力只有20伏特以下。
发明内容
本发明要解决的技术问题是提供一种5伏CMOS工艺中的NLDMOS器件耐压能达到25伏特以上。本发明还提供了一种NLDMOS器件的制造方法。
为解决上述技术问题，本发明的NLDMOS器件包括：P型衬底上部并列形成有P阱和N阱，P阱和N阱上部分别形成有N+区，N阱中N+区的旁侧形成有长氧区，场氧形成于P阱、N阱和长氧区的上方，场氧上方形成有多晶硅层，隔离侧墙形成于场氧和多晶硅层的两侧；其中，P型衬底将所述P阱和N阱隔离。
所述P阱和N阱间P型衬底宽度是0.5微米～2微米。
所述场氧厚度为115埃～160埃。
所述多晶硅层厚度为2000埃。
所述隔离侧墙厚度为2500埃～3500埃。
本发明NLDMOS器件的制造方法，包括：
(1)在P型衬底上进行局部氧化形成长氧区；
(2)在P型衬底上注入形成不相邻的P阱和N阱；
(3)在P阱、N阱和长氧区的上方生长场氧；
(4)在长氧上方淀积多晶硅层；
(5)淀积二氧化硅，干法刻蚀形成隔离侧墙；
(6)在P阱和N阱中注入形成N+区，N阱中的N+区与长氧区相邻。
余下其他工艺步骤与5伏CMOS工艺相同，完成此NLDMOS的制作。
其中，实施步骤(2)时，形成P阱和N阱之间距离为0.5微米～2微米。
其中，实施步骤(3)时，生长场氧厚度为115埃～160埃。
其中，实施步骤(4)时，淀积多晶硅厚度为2000埃。
其中，实施步骤(5)时，淀积二氧化硅厚度为2500埃～3500埃。
本发明在5伏CMOS工艺中设计了一种NLDMOS器件采用P阱作为本底区(P-Body)，N阱作为N漂移区(N-Drift)，其他所有工艺条件(比如源和漏)与此5伏CMOS工艺相同。本发明的NLDMOS器件通过控制NLDMOS中的P型本底区(由P阱构成)和N漂移区(由N阱构成)之间的距离，实现对耐压的调整。在此5伏CMOS工艺中，P阱和N阱形成的PN结的击穿电压的一般就是20伏左右，因此NLDMOS的击穿电压将受这个电压限制，即使拉大N阱构成的漂移区的长度也对提高耐压没有帮助(除非更改两个阱的工艺，但这样会影响5V CMOS)；本发明中通过调整NLDMOS中N阱和P阱的距离的方法，提高了N阱和P阱在这个NLDMOS中构成的PN结的耐压，从而实现了不改变工艺条件而提高NLDMOS耐压的效果，能使NLDMOS器件的最高击穿电压突破20伏特，达到25伏特以上。
附图说明
下面结合附图与具体实施方式对本发明作进一步详细的说明：
图1是一种现有NLDMOS器件。
图2是本发明的NLDMOS器件。
图3是本发明制造方法的流程图。
图4是本发明制造方法示意图一，显示步骤(1)形成的器件。
图5是本发明制造方法示意图二，显示步骤(2)形成的器件。
图6是本发明制造方法示意图三，显示步骤(3)、(4)形成的器件。
图7是本发明制造方法示意图四，显示步骤(5)形成的器件。
具体实施方式
如图2所示，本发明的NLDMOS器件包括：P型衬底上部并列形成有P阱和N阱，P阱和N阱上部分别形成有N+区，N阱中N+区的旁侧形成有长氧区，场氧形成于P阱、N阱和长氧区的上方，场氧上方形成有多晶硅层，隔离侧墙形成于场氧和多晶硅层的两侧；其中，所述P阱和N阱间P型衬底宽度是0.5微米，所述场氧厚度为115埃，所述多晶硅层厚度为2000埃，所述隔离侧墙厚度为2500埃。
如图3所示，本发明NLDMOS器件的制造方法，包括：
(1)如图4所示，在P型衬底上进行局部氧化形成长氧区；
(2)如图5所示，在P型衬底上注入形成不相邻的P阱和N阱，P阱和N阱之间距离为0.5微米～2微米；
(3)如图6所示，在P阱、N阱和长氧区的上方通过热氧化法生长厚度为115埃～160埃的场氧；
(4)在长氧上方淀积厚度为2000埃的多晶硅层；
(5)如图7所示，淀积厚度为2500埃～3500埃二氧化硅，干法刻蚀形成隔离侧墙；
(6)在P阱和N阱中注入形成N+区，N阱中的N+区与长氧区相邻，形成如图2所示器件。
余下其他工艺步骤与5伏CMOS工艺相同，完成此NLDMOS的制作。
以上通过具体实施方式和实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (10)

1.一种NLDMOS器件，包括P型衬底上部并列形成有P阱和N阱，P阱和N阱上部分别形成有N+区，N阱中N+区的旁侧形成有长氧区，场氧形成于P阱、N阱和长氧区的上方，场氧上方形成有多晶硅层，隔离侧墙形成于场氧和多晶硅层的两侧；其特征是：P型衬底将所述P阱和N阱隔离。
2.如权利要求1所述的NLDMOS器件，其特征是：所述P阱和N阱间P型衬底宽度是0.5微米～2微米。
3.如权利要求2所述的NLDMOS器件，其特征是：所述场氧厚度为115埃～160埃。
4.如权利要求2所述的NLDMOS器件，其特征是：所述多晶硅层厚度为2000埃。
5.如权利要求2所述的NLDMOS器件，其特征是：所述隔离侧墙厚度为2500埃～3500埃。
6.一种NLDMOS器件的制造方法，其特征是，包括：
(1)在P型衬底上进行局部氧化形成长氧区；
(2)在P型衬底上注入形成不相邻的P阱和N阱；
(3)在P阱、N阱和长氧区的上方生长场氧；
(4)在长氧上方淀积多晶硅层；
(5)淀积二氧化硅，干法刻蚀形成隔离侧墙；
(6)在P阱和N阱中注入形成N+区，N阱中的N+区与长氧区相邻。
7.如权利要求6所述的NLDMOS器件制造方法，其特征是：实施步骤(2)时，形成P阱和N阱之间距离为0.5微米～2微米。
8.如权利要求6所述的NLDMOS器件制造方法，其特征是：实施步骤(3)时，生长场氧厚度为115埃～160埃。
9.如权利要求6所述的NLDMOS器件制造方法，其特征是：实施步骤(4)时，淀积多晶硅厚度为2000埃。
10.如权利要求6所述的NLDMOS器件制造方法，其特征是：实施步骤(5)时，淀积二氧化硅厚度为2500埃～3500埃。
CN2012100051199A 2012-01-09 2012-01-09 一种nldmos器件及其制造方法 Pending CN103199109A (zh)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103208519A (zh) * 2012-01-12 2013-07-17 上海华虹Nec电子有限公司 与5伏cmos工艺兼容的nldmos结构及其制法
WO2015021927A1 (zh) * 2013-08-13 2015-02-19 无锡华润上华半导体有限公司 横向双扩散金属氧化物半导体场效应晶体管
CN104538445A (zh) * 2013-12-27 2015-04-22 成都芯源系统有限公司 一种高压pmos器件及其制作工艺流程
CN104716179A (zh) * 2013-12-11 2015-06-17 上海华虹宏力半导体制造有限公司 一种具有深孔的ldmos器件及其制造方法
EP4235797A1 (en) * 2022-02-24 2023-08-30 GLOBALFOUNDRIES Singapore Pte. Ltd. Extended-drain metal-oxide-semiconductor devices with a gap between the drain and body wells

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US6903421B1 (en) * 2004-01-16 2005-06-07 System General Corp. Isolated high-voltage LDMOS transistor having a split well structure
CN101266930A (zh) * 2008-04-11 2008-09-17 北京大学 一种横向双扩散场效应晶体管的制备方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6903421B1 (en) * 2004-01-16 2005-06-07 System General Corp. Isolated high-voltage LDMOS transistor having a split well structure
CN101266930A (zh) * 2008-04-11 2008-09-17 北京大学 一种横向双扩散场效应晶体管的制备方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103208519A (zh) * 2012-01-12 2013-07-17 上海华虹Nec电子有限公司 与5伏cmos工艺兼容的nldmos结构及其制法
CN103208519B (zh) * 2012-01-12 2015-12-09 上海华虹宏力半导体制造有限公司 与5伏cmos工艺兼容的nldmos结构及其制法
WO2015021927A1 (zh) * 2013-08-13 2015-02-19 无锡华润上华半导体有限公司 横向双扩散金属氧化物半导体场效应晶体管
CN104377243A (zh) * 2013-08-13 2015-02-25 无锡华润上华半导体有限公司 一种降低ldmos导通电阻并同时提高开状态崩溃电压的ldmos
CN104716179A (zh) * 2013-12-11 2015-06-17 上海华虹宏力半导体制造有限公司 一种具有深孔的ldmos器件及其制造方法
CN104538445A (zh) * 2013-12-27 2015-04-22 成都芯源系统有限公司 一种高压pmos器件及其制作工艺流程
EP4235797A1 (en) * 2022-02-24 2023-08-30 GLOBALFOUNDRIES Singapore Pte. Ltd. Extended-drain metal-oxide-semiconductor devices with a gap between the drain and body wells

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