WO2015021927A1 - 横向双扩散金属氧化物半导体场效应晶体管 - Google Patents

横向双扩散金属氧化物半导体场效应晶体管 Download PDF

Info

Publication number
WO2015021927A1
WO2015021927A1 PCT/CN2014/084302 CN2014084302W WO2015021927A1 WO 2015021927 A1 WO2015021927 A1 WO 2015021927A1 CN 2014084302 W CN2014084302 W CN 2014084302W WO 2015021927 A1 WO2015021927 A1 WO 2015021927A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
field
drift region
drift
ldmos
Prior art date
Application number
PCT/CN2014/084302
Other languages
English (en)
French (fr)
Inventor
韩广涛
孙贵鹏
黄枫
Original Assignee
无锡华润上华半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Publication of WO2015021927A1 publication Critical patent/WO2015021927A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like

Definitions

  • the invention relates to a lateral double-diffused metal oxide semiconductor field effect transistor (Lateral Double Diffused)
  • LDMOS field of MOSFET
  • LDMOS metal oxide semiconductor field effect transistor
  • the depletion layer in the drift region expands toward the drain, and is easily extended to the high concentration of the drain terminal (such as n+), thereby forming a large electric field at the boundary of the high concentration lead terminal. It is easy to cause breakdown due to impact ionization caused by a large electric field, that is, the breakdown voltage in the open state is low.
  • a lateral double-diffused metal oxide semiconductor field effect transistor comprising: a semiconductor substrate, a body region located within the semiconductor substrate; a drift region located within the semiconductor substrate; located in the body region and a source region and a body lead-out region separated by a drift region; a field region and a drain region located in the drift region; and a portion of the surface of the semiconductor substrate covering the body region, the drift region, and the field a gate of the region; wherein the field region and the drain region are spaced apart by a certain distance.
  • an active region is formed between the field region and the drain region.
  • the gate is between the source region and the drain region.
  • the field area is STI or FOX.
  • the source region and the body lead-out region have opposite doping types.
  • the body region and the drift region are isolated from one another.
  • the size of the field region near the drain end of the drift region is shortened, so that all the drift regions of the field region become A field area and an active area to reduce the on-resistance of the LDMOS while increasing the on-state breakdown voltage.
  • FIG. 1 is a schematic cross-sectional view of an LDMOS device fabricated in accordance with one embodiment
  • Figure 3 is a characteristic curve of the breakdown voltage of the off state of the LDMOS
  • the directional term of "upper”, “lower”, “left” and “right” is defined relative to the orientation of the LDMOS in the drawing (for example, the left and right direction refers to the channel direction of the LDMOS, which is parallel to the substrate surface, and the up and down direction). Perpendicular to the surface of the substrate). Also, it should be understood that these directional terms are relative concepts that are used for relative description and clarification, which may vary accordingly depending on the orientation in which the LDMOS is placed.
  • the present invention proposes an LDMOS semiconductor device structure.
  • FIG. 1 shows a schematic cross-sectional view of an LDMOS device fabricated in accordance with an embodiment of the present invention.
  • the lateral double-diffused metal oxide semiconductor field effect transistor is an N-type device, and the LDMOS structure of the embodiment will be specifically described below with reference to FIG.
  • the LDMOS shown in FIG. 1 includes a substrate 200, a well 201 in the substrate, and a field oxide layer 203 at the interface between the substrate 200 and the surface of the well 201.
  • an LDMOS is formed on a semiconductor substrate 200, which is a silicon substrate.
  • the drift region 204 and the well region 201 are doped in the semiconductor substrate 200.
  • the substrate is a P-type substrate, and the specific doping concentration thereof is not limited.
  • the semiconductor substrate may be formed by epitaxial growth or a wafer substrate.
  • a P well 201 is formed in a semiconductor substrate using a standard well implantation process.
  • the P-well can be formed by a high-energy implantation process, or a P-well can be formed by a low-energy implantation process in conjunction with a high-temperature thermal annealing process.
  • a source region and a body lead-out region of the LDMOS device can be formed in the well.
  • the drift region and the P-well are formed in a similar manner and can be formed by a high-energy implantation process or by a low-energy implantation and a high-temperature thermal annealing process.
  • a P well 201 is formed as a body region on the semiconductor substrate 200.
  • the doping concentration of the body region may range from 1015 atoms/cm 3 to 1018 atoms/cm 3 , for example, the doping concentration is set to 1017 atoms/cm 3 .
  • the drift region is N-type doped.
  • a drift region 204 is also formed in the semiconductor substrate 200. The drift region is located in the semiconductor substrate and is located between the source and the drain. The drift region is generally a lightly doped region, and the presence of the drift region can provide a blow to the LDMOS device. The voltage is applied while reducing the parasitic capacitance between the source and the drain.
  • the drift region is N-type doped, and the doping concentration is generally lower than the doping concentration of the drain.
  • the drift region doping concentration may range from 1015 atoms/cm 3 to 1018 atoms/cm 3 .
  • the subsequently formed drift region field oxide layer is the field region formed over the drift region, which is a shallow trench isolation structure (STI).
  • a silicon nitride layer and a silicon oxide layer are formed on the semiconductor substrate, and the photoresist layer having the drift region is used as a mask, and the nitrogen above the drift region is sequentially etched by dry etching.
  • An isolation region oxide layer 203 is formed on the semiconductor substrate 200 using a shallow trench isolation technique.
  • a well region 201 and a drift region 204 are formed in the semiconductor substrate 200.
  • the well region 201 and the drift region 204 are implanted in the semiconductor liner 200. Both the well region 201 and the drift region 204 may be formed by high energy implantation, or may be formed by low energy implantation and high temperature thermal annealing. .
  • the well region 201 serves as a body region, and a P + -type impurity forming body lead-out region 202 is implanted in the body region, and an N + -type impurity forming source region 205 is implanted.
  • An N+ type impurity is implanted in the drift region to form a drain region 206.
  • the doping concentrations of the source region 205 and the drain region 206 may be the same, and thus, both may be formed by doping in synchronization.
  • the source region 205 and the drain region 206 may have an N-type doping concentration ranging from 1018 atoms/cm 3 to 1021 atoms/cm 3 , for example, a doping concentration of 1020 atoms/cm 3 .
  • a gate 207 covering the body region 201, the drift region 204, and the field region 208 is formed on a surface of the semiconductor substrate 200.
  • an interlayer dielectric layer (not shown) is deposited on the semiconductor substrate, and corresponding via holes are formed on the interlayer dielectric layer, and metal is introduced into the corresponding via holes to connect the gate, the source, the drain, and The body lead-out area is connected to the corresponding gate G, source S, drain D, and Bulk.
  • the LDMOS device includes a semiconductor substrate 200, a body region located within the semiconductor substrate 200, a drift region 204 located within the semiconductor substrate, within the body region and the drift region 204.
  • the source, drain, and gate can be patterned separately at the source, drain, and gate.
  • the gate structure 207 may extend partially onto the field oxide layer 208 of the drift region
  • the embodiment of the lateral double-diffused metal oxide semiconductor field effect transistor is exemplified by an N-type device.
  • the size of the drift region is made as small as possible, thereby causing the on-state breakdown voltage to be generally low.
  • the present invention provides an LDMOS semiconductor device structure capable of reducing on-resistance while improving on-state breakdown voltage, compared with existing LDMOS structures, such as The LDMOS shown in FIG. 1 retracts the size of the field region near the drain end of the drift region while keeping the size of the original drift region unchanged, so that the drift region which is all the field region becomes a field region.
  • the increased N-type impurity reduces the resistance of the drift region, thereby lowering the on-resistance (Rdson).
  • the depletion effect of the entire N-type drift region is small for the off state, and the off-state collapse voltage is substantially unchanged, even after obtaining the drift region of the gradual concentration, the potential and the electric field of the drift region are obtained.
  • the distribution is more uniform and a higher off-state breakdown voltage can be obtained.
  • the invention does not add any difficulty to the process part and can be well compatible with the CMOS/LDMOS integrated circuit manufacturing process.
  • the introduction of the active region increases the total amount of N-type impurities between the drift region and the drain terminal N+, which is equivalent to obtaining a drift region of a concentration gradient, thereby maintaining the off state and the collapse voltage unchanged.
  • the on-state breakdown voltage is effectively increased, and the increased N-type impurity reduces the resistance of the drift region, thereby reducing the on-resistance.
  • the manufacturing method of the lateral double-diffused metal oxide semiconductor field effect transistor is also exemplified by an N-type device, and includes the following steps.
  • Step a forming a P well on a P-type substrate using a standard well implantation process
  • Step b implanting an N-type impurity on the P-type liner to form a drift region
  • Step c defining a active region of the device by using a standard shallow trench isolation process or a thermal oxidation growth process, and forming a field oxide layer in the field region;
  • Step d forming a gate using a standard polysilicon deposition and etching process
  • Step e implanting a P+ type impurity into the well region to form a body lead-in region, and injecting N+ impurities into the well region and the drift region to form a source and a drain;
  • the lateral double-diffused metal oxide semiconductor field effect transistor and the manufacturing method thereof reduce the size of the field region near the drain end of the drift region while maintaining the original drift region size, so that all the original drift regions of the field region are It becomes a field region (STI or FOX) and a segment of active region (TO), so that the total amount of N-type impurities near the drain end of the original drift region is increased, which is equivalent to obtaining a concentration-graded N-type drift region 204, thereby enabling on The state crash voltage is increased.
  • the increased N-type impurity reduces the resistance of the drift region, thereby lowering the on-resistance (Rdson).
  • a curve 301 is a characteristic curve of the existing LDMOS
  • a curve 302 is a characteristic curve of the LDMOS according to the embodiment shown in FIG. 1. Comparing the curve 301 and the curve 302, it is understood that the on-resistance of the LDMOS fabricated according to the present embodiment is smaller than the on-resistance of the LDMOS fabricated in the prior art as compared with the LDMOS fabricated in the prior art.
  • the curve 401 is a characteristic curve of the existing LDMOS
  • the curve 402 is a characteristic curve of the LDMOS of the embodiment shown in FIG. 1. Comparing the curve 401 and the curve 402, it can be seen that the breakdown voltage of the LDMOS fabricated according to the present invention and the LDMOS fabricated in the prior art are substantially unchanged, and the LDMOS fabricated according to the present embodiment has an increased N-type impurity. Close to the drain end, the depletion effect of the entire N-type drift region is small for the off state, and the off-state collapse voltage is basically unchanged. Even after obtaining the drift region of the gradual concentration, the potential and electric field distribution of the drift region are more uniform. A higher off-state breakdown voltage can be obtained.
  • a curve 501 is a characteristic curve of the prior embodiment LDMOS
  • a curve 502 is a characteristic curve of the LDMOS of the embodiment shown in FIG. 1. Comparing the curve 501 and the curve 502, compared with the LDMOS fabricated in the prior art, the Vds of the Id of the LDMOS fabricated in this embodiment starts to rise rapidly, and the value of Vds which starts to rise rapidly by the Ids of the LDMOS fabricated according to the prior art is Curves 501a and 502a are illustrated by way of example.

Abstract

一种横向双扩散金属氧化物半导体场效应晶体管，包括：半导体衬底（200），位于所述半导体衬底（200）内的体区（201）；位于所述半导体衬底（200）内的漂移区（204）；位于所述体区（201）内与所述漂移区（204）相隔开的源区（205）和体引出区（202）；位于所述漂移区（204）内的场区（208）和漏区（206）；以及位于所述半导体衬底（200）表面上部分覆盖所述体区（201）、所述漂移区（204）和所述场区（208）的栅极；其中，所述场区（208）和所述漏区（206）之间间隔一定距离。该半导体器件，在保持原有漂移区（204）尺寸不变的前提下，将漂移区（204）靠近漏端的场区（208）尺寸缩短，使原有全部为场区的漂移区，变为一段场区和一段有源区，以降低LDMOS导通电阻，同时提高开状态崩溃电压。

Description

横向双扩散金属氧化物半导体场效应晶体管
【技术领域】
本发明涉及横向双扩散金属氧化物半导体场效应晶体管（Lateral Double Diffused MOSFET，LDMOS）技术领域，特别涉及一种降低导通电阻并同时提高开状态崩溃电压的LDMOS器件结构。
【背景技术】
随着半导体技术的不断发展，横向双扩散金属氧化物半导体场效应晶体管（LDMOS）器件由于其具有良好的短沟道特性而被广泛的应用于移动电话，尤其应用在蜂窝电话中。随着移动通信市场（尤其是蜂窝通信市场）的不断增加，LDMOS器件的制作工艺日益成熟。LDMOS 作为一种功率开关器件，具有工作电压相对较高、工艺简易，易于同低压CMOS电路在工艺上兼容等特点，在工作时包括有“关态（off-state）”和“开态（on-state）”，与普通MOS器件相比，在漏极有一个轻掺杂注入区，被称为漂移区。由于其通常用于功率电路，需要获得较大的输出功率，因此必须能承受较高的电压。随着LDMOS的广泛应用功率集成电路，对LDMOS的器件性能要求也越来越高。
在现有技术中，为了获得较小的导通电阻，需要尽量将漂移区的尺寸做小。然而，当LDMOS在高压条件下工作时，漂移区中耗尽层向漏极扩展，极易扩展至漏区高浓度的引出端（如n+），从而在高浓度引出端边界形成大电场，很容易发生由于大电场引发碰撞电离导致击穿，也即开状态下的崩溃电压较低。
因此，需要一种新型的LDMOS半导体器件，既能降低导通电阻，同时又能提高开状态崩溃电压。
【发明内容】
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
有鉴于此，有必要提供一种既能降低导通电阻，同时又能提高开状态崩溃电压的横向双扩散金属氧化物半导体场效应晶体管。
一种横向双扩散金属氧化物半导体场效应晶体管，包括：半导体衬底，位于所述半导体衬底内的体区；位于所述半导体衬底内的漂移区；位于所述体区内与所述漂移区相隔开的源区和体引出区；位于所述漂移区内的场区和漏区；以及位于所述半导体衬底表面上部分覆盖所述体区、所述漂移区和所述场区的栅极；其中，所述场区和所述漏区之间间隔一定距离。
在一个实施例中，所述场区和所述漏区之间形成有源区。
在一个实施例中，所述栅极位于所述源区和所述漏区之间。
在一个实施例中，所述场区为STI或者FOX。
在一个实施例中，所述源区和体引出区的掺杂类型相反。
在一个实施例中，所述体区与所述漂移区彼此隔离。
根据上述横向双扩散金属氧化物半导体场效应晶体管，在保持原有漂移区尺寸不变的前提下，将漂移区靠近漏端的场区尺寸缩短，使原有全部为场区的漂移区，变为一段场区和一段有源区，以降低LDMOS导通电阻，同时提高开状态崩溃电压。
【附图说明】
下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。在附图中，
图1为根据一个实施方式制作的LDMOS器件的截面结构示意图；
图2为LDMOS的开状态电流-栅源极电压的特性曲线；
图3为LDMOS的关态的击穿电压的特性曲线；
图4为LDMOS的开状态电流-源漏极电压的特性曲线。
【具体实施方式】
为了彻底了解本发明，将在下列的描述中提出详细的步骤，以便说明本发明是如何改进制作半导体器件结构的工艺来解决现有技术中的问题。显然，本发明的施行并不限定于半导体领域的技术人员所熟习的特殊细节。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。
本文中。“上”“下”“左”“右”的方向型术语是相对于附图中LDMOS的方位来定义的（例如，左右方向是指LDMOS的沟道方向、其平行于衬底表面、上下方向垂直于衬底表面）。并且，应当理解到，这些方向性术语是相对概念，它们用于相对的描述和澄清，其可以根据LDMOS所放置的方位的变化而相应地发生变化。
为了解决现有技术中的问题，本发明提出了一种LDMOS半导体器件结构。
下面结合附图1对本发明的具体实施方式做详细的说明。图1示出根据本发明的一个实施方式制作的LDMOS器件的截面结构示意图。在该实施例中，横向双扩散金属氧化物半导体场效应晶体管为N型器件，以下结合图1对该实施例的LDMOS结构进行具体说明。
图1所示的LDMOS包括衬底200、衬底内的阱201、位于衬底200和阱201表层交界处的场氧化层203。
如图1所示，LDMOS形成于半导体衬底200上，半导体衬底200为硅衬底。在半导体衬底200内掺杂形成漂移区204和阱区201。
在本实施例中，衬底为P型衬底，其具体的掺杂浓度不受限制。半导体衬底具体的可以通过外延生长形成，也可以为晶圆衬底。
采用标准的阱注入工艺在半导体衬底中形成P阱201。可以通过高能量注入工艺形成P阱，也可以通过低能量注入，搭配高温热退火过程形成P阱。在阱中可以形成LDMOS器件的源区和体引出区。漂移区和P阱形成方式相似，可以通过高能量注入工艺形成，也可以通过低能量注入，搭配高温热退火过程形成。
在半导体衬底200上形成P阱201作为体区。在优选的实施例中，体区的掺杂浓度范围可以为1015原子/cm3~1018原子/cm3，例如掺杂浓度设置为1017原子/cm3。对于N沟道LDMOS，漂移区为N型掺杂。同时还在半导体衬底200中形成漂移区204，漂移区位于半导体衬底内，且位于源极和漏极之间，漂移区一般为轻掺杂区，漂移区的存在可提供LDMOS器件的击穿电压，同时减小源、漏极之间的寄生电容，对于N沟槽LDMOS，漂移区为N型掺杂，其掺杂浓度一般低于漏极的掺杂浓度，在优选的实施例中，漂移区掺杂浓度范围可以为1015原子/cm3~1018原子/cm3。后续形成的漂移区场氧化层即是在漂移区上方形成的场区，所述场区为浅沟槽隔离结构（STI）。
在一具体实施方式中，在半导体衬底上形成有氮化硅层和氧化硅层，以具有漂移区的光刻胶层为掩膜，采用干法刻蚀依次刻蚀掉漂移区上方的氮化硅层和氧化硅层，以及硅层，以形成沟槽结构，去除具有漂移区图案的光刻胶层，采用氧化层淀积和磨平方式形成STI区208。
采用浅沟槽隔离技术在半导体衬底200上形成隔离区氧化层203。半导体衬底200内形成有阱区201和漂移区204。
在一具体实施方式中，在半导体衬体200内注入形成阱区201和漂移区204，阱区201和漂移区204都可以通过高能量注入形成，也可以通过低能量注入，搭配高温热退火形成。阱区201作为体区，在体区内注入P+型杂质形成体引出区202，以及注入N+型杂质形成源区205。在漂移区内注入N+型杂质形成漏区206。源区205和漏区206的掺杂浓度可以相同，因此，二者可以同步地掺杂形成。在优选实施例中，源区205和漏区206的N型掺杂浓度范围可以为1018原子/cm3~1021原子/cm3，例如掺杂浓度设置为1020原子/cm3。
在所述半导体衬底200表面上形成覆盖所述体区201、漂移区204和所述场区208的栅极207。
最后在半导体衬底上沉积层间介质层（未示出），并在层间介质层上形成相应的通孔，在所述相应通孔中引入金属可将栅极、源极、漏极和体引出区与相应的栅极G、源极S、漏极D和Bulk相连。
图1为根据一实施方式制作的LDMOS器件的截面结构示意图。如图1所示，LDMOS器件包括半导体衬底200，位于所述半导体衬底200内的体区，位于所述半导体衬底内的漂移区204，位于所述体区内与所述漂移区204相隔开的源区205和体引出区202；位于所述漂移区204内的场区208和漏区206；以及位于所述半导体衬底200表面上部分覆盖所述体区201、漂移区204和所述场区的栅极207；其中，所述场区208和所述漏区206之间间隔一定距离；所述场区208和所述漏区206之间形成有源区209，所述栅极207位于所述源区205和所述场区208之间，所述场区208为STI（浅沟槽隔离结构）或者FOX（field oxide，场氧），所述阱区201（体区）与所述漂移区204彼此隔离，位于衬底200和阱区201表层交界处的场氧化层203。在源区、漏区以及栅极上可以分别构图引出源极、漏极、以及栅极。栅极结构207可以部分的延伸至漂移区204的场氧化物层208上。
横向双扩散金属氧化物半导体场效应晶体管的实施方式以N型器件为例，现有技术为了获得较小的导通电阻，尽量将漂移区尺寸做小，由此导致on状态崩溃电压普遍较低。在传统的漂移区全部为场区的基础上，本发明提供了一种既能降低导通电阻，同时又能提高on状态崩溃电压的LDMOS半导体器件结构，相比与现有的LDMOS结构，如图1中所示的LDMOS在保持原有漂移区尺寸不变的前提下，将漂移区靠近漏端的场区尺寸回缩，使原有全部为场区的漂移区，变为一段场区（场氧化层）208（STI）和一段有源区（TO）209。虚线部分由场区变为有源区后，使原漂移区靠近漏端的N型杂质总量增加，相当于获得了一个浓度渐变的N型漂移区204，从而使on状态崩溃电压提高。增加的N型杂质，使漂移区电阻降低，从而使导通电阻降低（Rdson）。由于增加的N型杂质靠近漏端，对于off态时整个N型漂移区的耗尽影响较小，off态崩溃电压基本不变，甚至在获得渐变浓度的漂移区后，漂移区的电势及电场分布更为均匀，还可以获得更高的off态崩溃电压。本发明对于工艺制程部分没有增加任何难度，可以很好的与CMOS/LDMOS集成电路制造工艺兼容。
在一具体实施方式中，该有源区的引入增加了漂移区与漏端N+之间的N型杂质总量，相当于获得了一个浓度渐变的漂移区，从而在保持off状态崩溃电压不变的前提下，有效提高了on状态崩溃电压，增加的N型杂质使漂移区电阻减小，从而降低了导通电阻。
横向双扩散金属氧化物半导体场效应晶体管的制造方法也以N型器件为例，包括以下步骤
步骤a：在P型衬底上采用标准的阱注入工艺，形成P阱；
步骤b：在P型衬体上注入N型杂质形成漂移区；
步骤c：采用标准的浅沟槽隔离工艺或热氧化生长工艺，定义器件的有源区，并在场区形成场氧化层；
步骤d：利用标准的多晶硅淀积和刻蚀工艺形成栅极；
步骤e：阱区内注入P+型杂质形成体引区，阱区及漂移区内注入N+杂质形成源、漏极；
沉积形成介质层、刻蚀接触孔、在接触孔中沉积金属层、刻蚀金属导线以及钝化等步骤均是本领域的技术人员熟知的技术手段在此就不详细赘述。
横向双扩散金属氧化物半导体场效应晶体管及其制造方法在保持原有漂移区尺寸不变的前提下，将漂移区靠近漏端的场区尺寸回缩，使原有全部为场区的漂移区，变为一段场区（STI或FOX）和一段有源区（TO），使原漂移区靠近漏端的N型杂质总量增加，相当于获得了一个浓度渐变的N型漂移区204，从而使on状态崩溃电压提高。增加的N型杂质，使漂移区电阻降低，从而使导通电阻降低（Rdson）。
图2为制作的LDMOS的开状态电流-栅源极电压的特性曲线，其中曲线301为现有的LDMOS的特性曲线，曲线302为根据图1所示实施例LDMOS的特性曲线。对比曲线301和曲线302可知，与现有技术制作的LDMOS相比，根据本实施例制作的LDMOS的导通电阻比现有技术制作的LDMOS的导通电阻小。
图3为制作的LDMOS的关态的击穿电压的特性曲线，其中曲线401为现有的LDMOS的特性曲线，曲线402为图1所示实施例LDMOS的特性曲线。对比曲线401和曲线402可知，根据本发明制作的LDMOS与现有技术制作的LDMOS处于关态时两者的崩溃电压基本不变，而在根据本实施例制作的LDMOS，由于增加的N型杂质靠近漏端，对于off态时整个N型漂移区的耗尽影响较小，off态崩溃电压基本不变，甚至在获得渐变浓度的漂移区后，漂移区的电势及电场分布更为均匀，还可以获得更高的off态崩溃电压。
图4为LDMOS的开状态电流-源漏极电压的特性曲线，其中曲线501为现有的实施例LDMOS的特性曲线，曲线502为图1所示实施例LDMOS的特性曲线。对比曲线501和曲线502可知，与现有技术制作的LDMOS相比，本实施例制作的LDMOS的Id开始快速上升的Vds大于根据现有技术制作的LDMOS的Ids开始快速上升的Vds的值，以曲线501a和502a为例来说明，对于曲线501a，当Vds到达30伏左右时，Id开始快速上升，表明漏区和漂移区交界处开始发生碰撞电离；对于曲线502a，当Vds到达37伏左右时，Id开始快速上升，表明漏区和漂移区交界处开始发生碰撞电离。因此，在开状态下的崩溃电压得到大大提高。调整图1所示实施例中场区208及有源区209的尺寸搭配，可以获得最优的器件性能。
以上所示实施方式仅是以NMOS为例，也可以应用在PMOS，本领域技术人员仅需做简单变形即可实现。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。

Claims (6)

  1. 一种横向双扩散金属氧化物半导体场效应晶体管，包括：
    半导体衬底；
    位于所述半导体衬底内的体区；
    位于所述半导体衬底内的漂移区；
    位于所述体区内与所述漂移区相隔开的源区和体引出区；
    位于所述漂移区内的场区和漏区；以及
    位于所述半导体衬底表面上部分覆盖所述体区、所述漂移区和所述场区的栅极；
    其中，所述场区和所述漏区之间间隔一定距离。
  2. 如权利要求1所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述场区和所述漏区之间形成有源区。
  3. 如权利要求1所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述栅极位于所述源区和所述漏区之间。
  4. 如权利要求1所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述场区为STI或者FOX。
  5. 如权利要求1所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述源区和所述体引出区的掺杂类型相反。
  6. 如权利要求1所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述体区与所述漂移区彼此隔离。
PCT/CN2014/084302 2013-08-13 2014-08-13 横向双扩散金属氧化物半导体场效应晶体管 WO2015021927A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310351199.8A CN104377243A (zh) 2013-08-13 2013-08-13 一种降低ldmos导通电阻并同时提高开状态崩溃电压的ldmos
CN201310351199.8 2013-08-13

Publications (1)

Publication Number Publication Date
WO2015021927A1 true WO2015021927A1 (zh) 2015-02-19

Family

ID=52468067

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/084302 WO2015021927A1 (zh) 2013-08-13 2014-08-13 横向双扩散金属氧化物半导体场效应晶体管

Country Status (2)

Country Link
CN (1) CN104377243A (zh)
WO (1) WO2015021927A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113746464A (zh) * 2021-09-03 2021-12-03 南京邮电大学 一种ldmos性能优化的自适应衬底电压调节电路

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252278B1 (en) * 1998-05-18 2001-06-26 Monolithic Power Systems, Inc. Self-aligned lateral DMOS with spacer drift region
CN101257047A (zh) * 2008-04-03 2008-09-03 北京大学 一种耐高压的横向双扩散mos晶体管
JP2010258355A (ja) * 2009-04-28 2010-11-11 Sharp Corp 半導体装置及びその製造方法
CN101958346A (zh) * 2009-07-16 2011-01-26 中芯国际集成电路制造(上海)有限公司 横向双扩散金属氧化物半导体场效应管及其制作方法
CN102005452A (zh) * 2009-08-31 2011-04-06 万国半导体股份有限公司 高电压半导体器件中的集成肖特基二极管
CN102088030A (zh) * 2009-12-04 2011-06-08 无锡华润上华半导体有限公司 横向双扩散金属氧化物半导体场效应管及其制造方法
CN103199109A (zh) * 2012-01-09 2013-07-10 上海华虹Nec电子有限公司 一种nldmos器件及其制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7309636B2 (en) * 2005-11-07 2007-12-18 United Microelectronics Corp. High-voltage metal-oxide-semiconductor device and method of manufacturing the same
CN103050528A (zh) * 2011-10-17 2013-04-17 中芯国际集成电路制造(上海)有限公司 Ldmos晶体管及其制作方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252278B1 (en) * 1998-05-18 2001-06-26 Monolithic Power Systems, Inc. Self-aligned lateral DMOS with spacer drift region
CN101257047A (zh) * 2008-04-03 2008-09-03 北京大学 一种耐高压的横向双扩散mos晶体管
JP2010258355A (ja) * 2009-04-28 2010-11-11 Sharp Corp 半導体装置及びその製造方法
CN101958346A (zh) * 2009-07-16 2011-01-26 中芯国际集成电路制造(上海)有限公司 横向双扩散金属氧化物半导体场效应管及其制作方法
CN102005452A (zh) * 2009-08-31 2011-04-06 万国半导体股份有限公司 高电压半导体器件中的集成肖特基二极管
CN102088030A (zh) * 2009-12-04 2011-06-08 无锡华润上华半导体有限公司 横向双扩散金属氧化物半导体场效应管及其制造方法
CN103199109A (zh) * 2012-01-09 2013-07-10 上海华虹Nec电子有限公司 一种nldmos器件及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113746464A (zh) * 2021-09-03 2021-12-03 南京邮电大学 一种ldmos性能优化的自适应衬底电压调节电路
CN113746464B (zh) * 2021-09-03 2023-12-12 南京邮电大学 一种ldmos性能优化的自适应衬底电压调节电路

Also Published As

Publication number Publication date
CN104377243A (zh) 2015-02-25

Similar Documents

Publication Publication Date Title
US6825531B1 (en) Lateral DMOS transistor with a self-aligned drain region
WO2015021944A1 (zh) 横向双扩散金属氧化物半导体场效应晶体管
US8048765B2 (en) Method for fabricating a MOS transistor with source/well heterojunction and related structure
KR20050031914A (ko) 금속 산화물 반도체 장치와 그의 형성 방법 및 집적 회로
US10134641B2 (en) Enhanced integration of DMOS and CMOS semiconductor devices
US20200388695A1 (en) Manufacture of self-aligned power devices
WO2011075989A1 (zh) 形成有沟道应力层的半导体结构及其形成方法
US10998409B2 (en) Transistors having gates with a lift-up region
WO2008147172A1 (en) Mos transistor with a p-field implant overlying each end of a gate thereof
KR100589489B1 (ko) 횡형 디모스의 제조방법
TW200532851A (en) High-voltage MO transistor and method for fabricating the same
KR940000521B1 (ko) 반도체 집적 회로장치 및 그의 제조방법
WO2013120344A1 (zh) 隧穿场效应晶体管及其制备方法
CN110767551A (zh) Ldmos器件及其制作方法及调节其电性参数的方法
CN111785774B (zh) Bcd工艺中cmos器件及其制造方法
WO2015021927A1 (zh) 横向双扩散金属氧化物半导体场效应晶体管
WO2013097608A1 (zh) 横向双扩散金属氧化物半导体场效应晶体管
TWI398951B (zh) 具分離式閘極垂直型金氧半電晶體元件結構及其製造方法
CN109390409B (zh) 一种阈值可调式高压金属氧化物半导体器件及其制备方法
CN105720101A (zh) 半导体装置及其制造方法
CN111370491B (zh) 开关ldmos器件及制造方法
CN113990942B (zh) 圆形对称结构的ldmos器件及其制备方法
KR100388063B1 (ko) 전력 집적 회로 제조 방법
CN107180856B (zh) 一种pmos器件结构
KR100607794B1 (ko) 횡형 디모스 소자

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14836442

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14836442

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 14836442

Country of ref document: EP

Kind code of ref document: A1