CN105097804B - 以锗硅bicmos技术在模拟/射频功率ed-cmos中建立栅极屏蔽的方法 - Google Patents

以锗硅bicmos技术在模拟/射频功率ed-cmos中建立栅极屏蔽的方法 Download PDF

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CN105097804B
CN105097804B CN201510266619.1A CN201510266619A CN105097804B CN 105097804 B CN105097804 B CN 105097804B CN 201510266619 A CN201510266619 A CN 201510266619A CN 105097804 B CN105097804 B CN 105097804B
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gate
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transistor region
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CN105097804A (zh
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J·A·巴伯库克
A·萨多夫尼科夫
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Texas Instruments Inc
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Abstract

本发明涉及以锗硅BICMOS技术在模拟/射频功率ED‑CMOS中建立栅极屏蔽的方法。一种以SiGe BICMOS技术制造MOSFET晶体管的方法，并且得到的结构具有形成在栅极电极116和漏极区106之间的漏栅反馈电容屏蔽112。该屏蔽不与栅极107重叠，由此最小化对晶体管的输入电容的影响。该过程不需要复杂或昂贵的处理，因为该屏蔽由通常用于SiGe BICMOS技术中的双极基极材料组成。

Description

以锗硅BICMOS技术在模拟/射频功率ED-CMOS中建立栅极屏蔽 的方法
技术领域
本发明一般涉及具有由栅极受控沟道连接的源极区和漏极区的MISFET(MOSFET)器件，并且更具体地，本发明涉及具有由栅漏屏蔽提供的减小的漏栅反馈电容从而降低电容耦合的MOSFET器件。
背景技术
MOSFET器件具有许多电学应用，包括用作RF/微波放大器。在这种应用中，栅极到漏极的反馈电容(Cgd或Crss)必须最小化，以最大化RF增益以及最小化信号失真。栅极到漏极的反馈电容是至关重要的，因为它通过器件的电压增益有效倍增或C有效＝Crss(1+gm R1)，其中gm是跨导并且R1是负载阻抗。
迄今，法拉第屏蔽已经应用在栅极电极和漏极电极之间以求最小化反馈电容。Adler等人的美国专利号5252848公开了一种MOSFET结构，其中屏蔽被提供在栅极电极上方并在漏极电极上方终止。屏蔽包括多晶硅层，具有100欧姆/平方米或更少的电阻形成在直接形成在栅极上方的应力减轻氧化层上方的氮化物薄膜上。该结构是有效的，但器件的制造由于需要两个多晶硅层而变得复杂。Weitzel的美国专利号5119149公开了一种砷化镓MESFET结构，其中，屏蔽导体放置于栅极电极和漏极电极之间，但不重叠栅极。栅极到漏极的反馈电容未被最小化，因为金属电极放置在栅极结构的钝化电介质材料上方。
本发明涉及一种制造方法和得到的MOSFET器件，其不需要复杂或昂贵的处理而且在器件的输入电容没有任何增加的情况下减小栅极到漏极的反馈电容。
发明内容
以下提出简化概述以提供本发明的一个或更多方面的基本理解。本概述不是本发明的广泛概述，也不旨在确定本发明的关键或本质要素，也不描述其范围。相反，本概述的主要目的是以简化形式提出本发明的一些概念作为接下来要提出的更详细的描述的序言。
根据本发明的一个实施例，一种具有栅极屏蔽的横向扩散金属氧化物半导体LDMOS，其中，具有栅极屏蔽的横向扩散金属氧化物半导体LDMOS包括：衬底；形成在衬底表面上的有源器件区；形成在有源器件区的LDMOS晶体管区域内的基体(body)阱；也形成在有源器件区的LDMOS晶体管区域内的横向漏极阱，其中基体阱和横向漏极阱彼此隔开且不接触；形成在LDMOS晶体管区域内的源极和漏极，其中源极形成在基体阱内且漏极形成在横向漏极阱内，其中源极和漏极之间具有横向间距；形成在基体阱上的栅极结构，其位于源极和有源器件区之间的空间上；其中栅极结构包括，应用在源极和有源器件区之间的基体阱的顶部上的栅极氧化层；形成在栅极氧化层顶表面上的栅极多晶硅层；形成在栅极多晶硅层的顶表面上的栅极电极；形成在栅极电极和漏极之间的栅极屏蔽，其中该屏蔽与栅极电极由基极(base)屏蔽间隔棒(spacer)分离；其中栅极屏蔽与栅极多晶硅层由栅极多晶间隔棒和屏蔽电介质分离；栅极屏蔽包括用于BICMOS晶片的双极晶体管区域内的双极基极结构，其中栅极屏蔽紧靠但不重叠栅极多晶硅层，且被限制到栅极多晶硅层和横向漏极阱的一部分之间的有限区域；形成在LDMOS晶体管的源极、漏极、栅极、栅极屏蔽和基体上的源极触点、漏极触点、栅极触点、栅极屏蔽触点和基体触点；形成在LDMOS结构上的电介质，其包括用于源极触点、漏极触点、栅极触点和基体触点的开口；和金属层，其被沉积和限定以形成栅极电极、基体电极、源极电极、栅极屏蔽电极和漏极电极。
根据本申请的另一个实施例，一种具有栅极屏蔽的横向扩散金属氧化物半导体LDMOS，其中具有栅极屏蔽的横向扩散金属氧化物半导体LDMOS包括：衬底；形成在衬底表面上的有源器件区；形成在有源器件区的LDMOS晶体管区域内的基体阱；也形成在有源器件区的LDMOS晶体管区域内的横向漏极阱，其中基体阱和横向漏极阱彼此隔开且不接触；形成在LDMOS晶体管区域内的源极和漏极，其中源极形成在基体阱内且漏极形成在横向漏极阱内，其中源极和漏极之间具有横向间距；包含在横向漏极阱内的浅沟槽隔离区域，其从漏极向外横向延伸但不接触横向漏极阱的边缘；形成在基体阱上的栅极结构，其位于源极和有源器件区之间的空间上；其中栅极结构包括应用在源极和有源器件区之间的基体阱的顶部上的栅极氧化层；形成在栅极氧化层顶表面上的栅极多晶硅层；形成在栅极多晶硅层的顶表面上的栅极电极；形成在栅极电极和漏极之间的栅极屏蔽，其中该屏蔽与栅极电极由基极屏蔽间隔棒分离；其中栅极屏蔽与栅极多晶硅层由栅极多晶间隔棒和屏蔽电介质分离；栅极屏蔽包括用于BICMOS晶片的双极晶体管区域中的双极基极结构，其中栅极屏蔽紧靠但不重叠栅极多晶硅层，且被限制到栅极多晶硅层和横向漏极阱的一部分之间的有限区域；形成在LDMOS晶体管的源极、漏极、栅极、栅极屏蔽和基体上的源极触点、漏极触点、栅极触点、栅极屏蔽触点和基体触点；形成在LDMOS结构上的电介质，其包括用于源极触点、漏极触点、栅极触点和基体触点的开口；和金属层，其被沉积和限定以形成栅极电极、基体电极、源极电极、栅极屏蔽电极和漏极电极。
根据本申请的又一个实施例，一种形成具有栅极屏蔽的横向扩散金属氧化物半导体LDMOS的方法，其中形成具有栅极屏蔽的横向扩散金属氧化物半导体LDMOS的方法包括：提供SOI晶片或块状硅晶片，其中SOI晶片包括硅衬底、第一硅层以及硅衬底和第一硅层之间的掩埋氧化层BOX；在完成的晶片中分别指定为NPN或PNP晶体管的区域中，注入N+NBL和P+PBL杂质到第一硅层顶表面中；在NBL、PBL和第一硅层上方沉积第二硅层，其接触NBL、PBL和第一硅层；其中第一硅层和第二硅层结合形成有源(active)器件层；在有源器件层中形成P-阱和N-阱以分别形成N沟道晶体管和P沟道晶体管的基体；在P-阱和N-阱的部分中形成浅沟槽隔离STI区域；沉积栅极氧化层；限定且注入源极和漏极；沉积且限定栅极多晶硅层；在栅极多晶硅层上沉积栅极多晶密封层(seal，密封/绝缘层)；其中栅极多晶密封层氧化物是使用900℃的稀释干O2、在44分钟内生长在多晶上的
Figure GDA0002277793080000041
的SiO2；在栅极多晶密封层上沉积间隔棒材料，其中间隔棒材料是
Figure GDA0002277793080000042
的PECVD TEOS；在间隔棒材料上沉积间隔棒氮化物；在整个晶片上方沉积
Figure GDA0002277793080000043
TEOS层；沉积
Figure GDA0002277793080000044
非晶硅籽晶层；图案化和刻蚀NPN基极氧化层窗口OXWIND，且在刻蚀后除去光刻胶；沉积NPN外延基极；图案化和刻蚀多晶屏蔽，其中NPN多晶基极通过LAM刻蚀器刻蚀；在STI区域上刻蚀基极外延多晶，刻蚀将在氧化层窗口TEOS上停止，其中剩余结构包括基极多晶保护层以形成RF屏蔽LDMOS FET；移除光刻胶；图案化和刻蚀NPN基极；移除光刻胶；在栅极、源极、基体和栅极屏蔽上形成触点且在暴露的触点和栅极屏蔽上方沉积金属层；使用快速热退火RTA在触点和栅极屏蔽上形成硅化物；以及沉积和限定绝缘层材料的最终层和最终金属层以在BICMOS器件上形成互连件和接合焊盘。
附图说明
图1是根据本发明的一个实施例的具有栅极屏蔽的CMOS晶体管结构的横截面图。
图1A是图1的放大截面图，其详述根据本发明的一个实施例的栅极屏蔽结构。
图2是根据本发明的另一个实施例的具有栅极屏蔽的CMOS晶体管结构的横截面图。
图2A是图2的放大截面图，其详述根据本发明的另一个实施例的栅极屏蔽结构。
图3是根据本发明的第三实施例的具有栅极屏蔽的CMOS晶体管结构的横截面图。
图3A是图3的放大截面图，其详述根据本发明的第三实施例的栅极屏蔽结构。
图4是根据本发明的第四实施例的具有栅极屏蔽的CMOS晶体管结构的横截面图。
图4A是图4的放大截面图，其详述根据本发明的第四实施例的栅极屏蔽结构。
图5是在本发明的一个实施例中详述的制造BICMOS器件所需的工艺步骤的流程图。
图5A示出根据本发明的一个实施例的BICMOS晶片的横截面图，其示出在间隔棒刻蚀工艺之后的CMOS区域。
图5B示出根据本发明的一个实施例的BICMOS晶片的横截面图，其示出在籽晶层沉积之后的CMOS区域。
图5C示出根据本发明的一个实施例的BICMOS晶片的横截面图，其示出NPN基极窗口限定工艺之后的双极区域。
图5D示出根据本发明的一个实施例的BICMOS晶片的横截面图，其示出NPN基极EPI沉积工艺之后的双极区域。
图5E示出根据本发明的一个实施例的BICMOS晶片的横截面图，其示出多晶屏蔽刻蚀工艺之后的CMOS区域。
图5F示出根据本发明的一个实施例的BICMOS晶片的横截面图，其示出多晶NPN基极多晶刻蚀工艺之后的双极区域。
图6示出具有使用现有技术的栅极屏蔽(1)的LDMOS晶体管、具有使用根据本发明的一个实施例的金属屏蔽的栅极屏蔽(2)的LDMOS晶体管和具有使用HBT基极屏蔽的栅极屏蔽(3)的LDMOS晶体管的栅极-漏极电容Cgd的比较。
在附图中，相似的附图标记常常用于表示类似的结构元件。还应当理解，附图中的表述是示意性的，并未按比例绘制。
具体实施方式
本发明将参考附图描述。附图未按比例绘制，其被提供以仅用来解释本发明。下文将参考用于示例说明的示例性应用描述本发明的若干方面。应当理解，阐述若干具体细节、关系和方法以提供本发明的理解。然而，相关领域的技术人员将容易理解，在没有一个或更多具体细节或使用其他方法的情况下，能够实现本发明。在其他情况中，已知结构或操作未详细示出以避免模糊本发明。本发明并不受限于所示的行为或事件的顺序，因为一些行为可以以不同的顺序发生和/或与其他行为或事件同时发生。此外，不是所有示出的行为或事件都需要用于实现根据本发明的方法。
本发明包括一种以SiGe BICMOS技术制造的、具有栅极屏蔽的横向扩散金属氧化物半导体LDMOS。SiGe BICMOS晶片能够在SOI衬底上制造，如图1和图2所示，或在块状硅衬底上制造，如图3和图4所示。所公开的本发明的实施例使用块状硅衬底和SOI衬底两者。应当理解，仅通过示例而非限制的方式提出各个实施例。在未偏离本发明的精神或范围的情况下，能够根据本发明对所公开的实施例进行若干变化。因此，本发明的广度和范围不应当被下述实施例的任何一个限制。相反，本发明的范围应当根据下述权利要求和它们的等同体限定。
根据本发明的一个实施例，将参考一种横向扩散金属氧化物半导体LDMOS晶体管阐述SiGe BICMOS技术中的MOSFET晶体管的结构，但应当理解，本发明适用于其他MOSFET晶体管，包括漏极延伸的MOSFET晶体管和纵向DMOS晶体管。图1是根据本发明的一个实施例的LDMOS晶体管的剖视图，并且图1A是图1的屏蔽结构的分解图。在图1和图1A中，器件包括硅衬底101、形成在其上的掩埋氧化层(BOX)102。有源器件区103形成在BOX表面上，其中深沟槽隔离沟道104限定LDMOS晶体管区域。深沟槽隔离沟道从晶片的顶部向下延伸至BOX并与其耦合。基体阱108形成在有源器件区103内。横向漏极阱109也形成在有源器件区103内，其中基体阱108和横向漏极阱109彼此隔开且不接触。光刻胶层用来遮罩源极/漏极区域，之后源极105和漏极106通过注入掺杂物形成。硅化物源极触点124然后形成在源极区域105上，并且硅化物漏极触点123然后形成在漏极区域106上。源极105和漏极106形成在LDMOS晶体管区域内，且它们之间具有横向间距，其中栅极结构形成在基体108上，其位于源极105和有源器件区103之间的空间上。栅极结构包括应用在源极105和有源器件区103之间的基体阱108上的栅极氧化层107，其中屏蔽接触116形成在栅极氧化层的表面上。
栅极屏蔽112形成在栅极触点122和漏极106之间的MOSFET器件的表面之上的籽晶层上，其中，屏蔽电极110、屏蔽接触116和栅极屏蔽112与栅极触点122由基极屏蔽间隔棒120分离。屏蔽112与栅极氧化物107还由栅极多晶间隔棒119和屏蔽电介质118分离。屏蔽112优选是BICMOS技术的P掺杂硅化物，其与双极晶体管的双极基极结构一起形成。在其他实施例中，屏蔽112还能够是使用BICMOS技术的N掺杂硅化物，其与双极晶体管的双极基极结构一起形成。
然后，电介质111形成在LDMOS结构上。光刻胶层用于遮罩电介质，并且接着应用湿式蚀刻或干式刻蚀工艺以从源极触点、漏极触点、栅极触点和基体触点移除层111。刻蚀步骤在源极触点、漏极触点、栅极触点、栅极屏蔽触点和基体触点处停止。
最后，金属沉积以及金属掩膜和刻蚀用于形成栅极电极113、基体电极和源极电极114、栅极屏蔽电极110以及漏极电极115。在此实施例中，屏蔽112紧靠但不重叠栅极107，但被限制到屏蔽接触116和横向漏极阱109的一部分之间的有限区域。
根据本发明的另一个实施例，将参考横向扩散金属氧化物半导体LDMOS晶体管描述SiGe BICMOS技术中的另一个MOSFET晶体管结构，但应当理解，本发明适用于其他MOSFET晶体管，包括漏极延伸的MOSFET晶体管和纵向DMOS晶体管。图2是根据本发明的另一个实施例的LDMOS晶体管的剖视图，并且图2A是图2的屏蔽结构的分解图。在图2和图2A中，器件包括硅衬底101、形成在其上的掩埋氧化层(BOX)102。有源器件区103形成在BOX表面上，其中深沟槽隔离沟道104限定LDMOS晶体管区域。深沟槽隔离沟道从晶片的顶部向下延伸至BOX并与其耦合。基体阱108形成在有源器件区103内。横向漏极阱109也形成在有源器件区103内，其中基体阱108和横向漏极阱109彼此接触。浅沟槽隔离区121包含在横向漏极阱109内，且从漏极106向外横向延伸但不接触横向漏极阱109的边缘。光刻胶层用于遮罩源极/漏极区域，并且之后源极105和漏极106通过注入掺杂物形成。源极105和漏极106形成在LDMOS晶体管区域内，且它们之间具有横向间距，其中栅极结构形成在位于源极105和横向漏极区109之间的基体阱108上的空间上。栅极结构包括应用在源极105和横向漏极区域109之间的基体区上的栅极氧化层107，其中栅极触点122形成在栅极氧化层107的表面上。
栅极屏蔽112形成在栅极触点122和横向漏极区109之间的MOSFET器件的表面之上的籽晶层上，其靠近栅极触点122和横向漏极区域109表面二者，但没有将它们短接。屏蔽112优选是BICMOS技术的P掺杂硅化物，其与双极晶体管的双极基极结构一起形成。在另一个实施例中，屏蔽112能够是BICMOS技术的N掺杂硅化物，其与双极晶体管的双极基极结构一起形成。
接着，电介质111形成在LDMOS结构上。光刻胶层用于遮罩电介质，且接着应用湿式蚀刻或干式刻蚀工艺以从源极触点、漏极触点、栅极触点、屏蔽触点和基体触点移除层111。刻蚀步骤在源极触点、漏极触点、栅极触点、屏蔽触点和基体触点处停止。
最后，金属沉积以及金属掩膜和刻蚀用于形成基体电极114、栅电极113、源极电极114、栅极屏蔽电极110和漏极电极115。在此实施例中，屏蔽112紧靠但不重叠栅极触点122，但重叠横向漏极区109之间的有限区域，包括浅沟槽隔离区117的一部分。
根据本发明的第三实施例，将参考横向扩散金属氧化物半导体LDMOS晶体管描述SiGe BICMOS技术中的MOSFET晶体管结构，但应当理解，本发明适用于其他MOSFET晶体管，包括漏极延伸的MOSFET晶体管和纵向DMOS晶体管。图3是根据本发明的一个实施例的示出LDMOS晶体管的剖视图，以及图3A是图3的屏蔽结构的分解图。在图3和图3A中，器件包括块状硅衬底101和形成在块状衬底101顶表面上的有源器件区103，其中深沟槽隔离沟道104限定LDMOS晶体管区域。基体阱108形成在有源器件区103内。横向漏极阱109也形成在有源器件区103内，其中基体阱108和横向漏极阱109彼此隔开且不接触。光刻胶层用于遮罩源极/漏极区域，并且之后源极105和漏极106通过注入掺杂物形成。源极105和漏极106形成在LDMOS晶体管区域内，它们之间具有横向间距，其中栅极结构形成在基体108上，位于源极105和有源器件区103之间的空间上。栅极结构包括应用在源极105和有源器件区103之间的基体阱108上的栅极氧化层107，其中屏蔽接触116形成在栅极氧化层的表面上。
栅极屏蔽112形成在栅极触点122和漏极106之间的MOSFET器件的表面上，其中，屏蔽电极110、屏蔽接触116和栅极屏蔽112与栅极触点122由基极屏蔽间隔棒120分离。屏蔽112与栅极107还被栅极多晶间隔棒119和屏蔽电介质118分离。屏蔽112优选是使用BICMOS技术的P掺杂硅化物，其与双极晶体管的双极基极结构一起形成。在其他实施例中，屏蔽112还能够是使用BICMOS技术的N掺杂硅化物，其与双极晶体管的双极基极结构一起形成。
接着，电介质111形成在LDMOS结构上。光刻胶层用于遮罩电介质，且接着应用湿式蚀刻或干式刻蚀工艺以从源极触点、漏极触点、栅极触点和基体触点移除层111。刻蚀步骤在源极触点、漏极触点、栅极触点、栅极屏蔽触点和基体触点处停止。
最后，金属沉积以及金属掩膜和刻蚀用于形成栅极电极113、基体电极和源极电极114、栅极屏蔽电极110以及漏极电极115。在此实施例中，屏蔽112紧靠但不重叠栅极氧化物107，但被限制到栅极触点122和横向漏极阱109的一部分之间的有限区域。
根据本发明的第四实施例，将参考横向扩散金属氧化物半导体LDMOS晶体管描述SiGe BICMOS技术中的另一个MOSFET晶体管结构，但应当理解，本发明适用于其他MOSFET晶体管，包括漏极延伸的MOSFET晶体管和纵向DMOS晶体管。图4是根据本发明的另一个实施例的LDMOS晶体管的剖视图，并且图4A是图4的屏蔽结构的分解图。在图4和图4A中，器件包括块状硅衬底101，有源器件区103形成在块状硅衬底101的表面上，其中深沟槽隔离沟道104限定LDMOS晶体管区域。基体阱108形成在有源器件区103内。横向漏极阱109也形成在有源器件区103内，其中基体阱108和横向漏极阱109彼此接触。浅沟槽隔离区117包含在横向漏极阱109内且从漏极106向外横向延伸，但不接触横向漏极阱109的边缘。光刻胶层用于遮罩源极/漏极区域，并且之后源极105和漏极106通过注入掺杂物形成。源极105和漏极106形成在LDMOS晶体管区域内，它们之间具有横向间距，其中栅极结构形成在源极105和横向漏极区域109之间的基体阱108上的空间上。栅极结构包括应用在源极105和横向漏极区域109之间的基体区域上的栅极氧化层107，其中屏蔽接触116形成在栅极氧化层的表面上。
栅极屏蔽112形成在栅极触点122和横向漏极区域109之间的MOSFET器件的表面之上的籽晶层上，其紧靠栅极触点122和横向漏极区域109表面二者但不短接它们。屏蔽112优选是使用BICMOS技术的P掺杂硅化物，其与双极晶体管的双极基极结构一起形成。在另一个实施例中，栅极屏蔽112能够是使用BICMOS技术的N掺杂硅化物，其与双极晶体管的双极基极结构一起形成。
然后，电介质111形成在LDMOS结构上。光刻胶层用于遮罩电介质，且之后应用湿式蚀刻或干式刻蚀工艺以从源极触点、漏极触点、栅极触点、屏蔽触点和基体触点移除层111。刻蚀步骤在源极触点、漏极触点、栅极触点、屏蔽触点和基体触点处停止。
最后，金属沉积以及金属掩膜和刻蚀用于形成基体电极114、栅极电极113、源极电极114、栅极屏蔽电极110和漏极电极115。在此实施例中，屏蔽112紧靠但不重叠栅极触点122，但重叠横向漏极区109之间的有限区域，包括浅沟槽隔离区117的一部分。
使用上述列出的结构改进了LDMOS器件的击穿电压BV和射频性能。此外，使用这种方法将改善这些结构的可靠性和器件稳健性。
实际上，形成BICMOS技术的方法在图5的流程图300中示出。
第一步301是提供能够具有1×1015cm3的均匀掺杂浓度的块状硅P型晶片或绝缘层SOI晶片上的硅。
下一步302是使用常规光刻胶工艺图案化及注入N+掩埋层NBL140和/或P+掩埋层PBL 141。
下一步303是生长外延层以提供有源器件区103。
步骤304是形成深沟槽隔离区104，其在必要位置包围并隔开每个双极晶体管，还提供结隔离141以在必要位置包围CMOS晶体管并隔开CMOS晶体管。
步骤305是沉积和形成栅极氧化物107、栅极多晶图案并且还注入间隔棒。
步骤306是在双极晶体管的基极和LDMOS晶体管的栅极屏蔽将形成的位置形成基极窗口并在晶片上沉积基极EPI层，其中。
步骤307是沉积外延多晶硅层以形成双极晶体管的基极142(见附图5C-5D和5F)以及附图1所示的LDMOS晶体管的栅极屏蔽。
步骤308是使用当个多晶硅基极掩膜511图案化并蚀刻双极晶体管的基极142，并且在相同的操作中，图案化并蚀刻LDMOS晶体管的栅极屏蔽112。
步骤309是在必要位置形成触点并在暴露的触点和栅极屏蔽上方沉积钴Co、钛Ti、镍Ni或铂Pt。使用快速热退火RTA，在触点、栅极屏蔽电极110和其他必要区域上形成硅化物。
步骤310是沉积多层金属铝和绝缘层材料SiO2以在BICMOS器件上形成互连件和接合焊盘。
图5A到图5E是随着BICMOS晶片经历的处理的横截面图。
该过程开始于提供SOI晶片或块状硅晶片。在当前实施例中，选择SOI晶片。SOI晶片包括衬底101、第一硅层103A和衬底101和第一硅层103A之间的掩埋氧化层BOX 102。N+NBL和P+PBL杂质被注入到第一硅层的顶表面中，在完整的晶片中被分别指定为NPN晶体管或PNP晶体管的区域中形成NBL区域140和PBL区域141。第二硅层103B沉积在NBL区域140、PBL区域141和第一硅层103A上方并与它们接触。第一硅层103A和第二硅层103B结合形成有源器件层103。
在有源器件层103内形成P-阱和N-阱以分别形成N沟道晶体管和P沟道晶体管的基体。沉积栅极氧化层，源极和漏极被限定和注入，并且栅极多晶层被沉积且被限定。
多晶密封层被沉积到栅极多晶层上。多晶密封层氧化物能够是使用900℃的稀释干O2、在44分钟内生长在多晶上的
Figure GDA0002277793080000111
的SiO2。
间隔棒材料被沉积在多晶密封层上。间隔棒材料能够是
Figure GDA0002277793080000112
PECVDTEOS。
间隔棒氮化物能够是705℃下、141分钟内沉积的
Figure GDA0002277793080000113
氮化物。使用LAM刻蚀器刻蚀间隔棒。
图5A示出BICMOS晶片的横截面图，其示出间隔棒刻蚀步骤305之后的CMOS区域。
Figure GDA0002277793080000114
TEOS层被沉积到晶片上。
Figure GDA0002277793080000115
TEOS沉积能够在684℃的熔炉中、在160分钟内完成。
在550℃下、27分钟内沉积
Figure GDA0002277793080000116
非晶硅籽晶层。
图5B示出BICMOS晶片的横截面，其示出籽晶层沉积步骤305之后的CMOS区域。
图案化和刻蚀NPN基极氧化层窗口OXWIND，且在刻蚀后除去光刻胶。
图5C示出BICMOS晶片的横截面，其示出NPN基极窗口限定工艺步骤306之后的双极区域。
NPN基极EPI沉积能够在825℃下、在2分钟内、使用双盒SiGe:C分布完成。随后，在基极内提供硼刺突(spike)，且提供轻掺杂硅覆盖层(约40nm)以在有源区103内提供
Figure GDA0002277793080000121
单晶层。
图5D示出BICMOS晶片的横截面图，其示出NPN基极EPI沉积工艺步骤306至308之后的双极区域，基极外延沉积应用于ED-MOSFET区域的籽晶层(见附图5B的籽晶层和附图5E中的屏蔽层112)并提供栅极屏蔽112的形成。
图案化和刻蚀以形成多晶屏蔽112。能够使用LAM刻蚀器掩膜511刻蚀NPN多晶基极层。在STI场氧化层121上刻蚀基极EPI多晶将在氧化层窗口TEOS上停止。这种结构保持基极多晶保护层以形成RF屏蔽的LDMOSFET或ED-MOSFET。
移除光刻胶。
图5E示出BICMOS晶片的横截面图，其示出多晶屏蔽刻蚀工艺步骤307-308之后的CMOS区域。
图案化和刻蚀NPN基极。能够使用LAM刻蚀器掩膜511刻蚀NPN多晶基极。在STI场氧化层121上刻蚀基极EPI多晶将在氧化层窗口TEOS上停止。该图案化和刻蚀步骤与图5E中的步骤同时进行，也从CMOS移除不属于栅极屏蔽112的基极多晶层。
移除光刻胶。
图5F示出BICMOS晶片的横截面图，其示出多晶NPN基极多晶刻蚀工艺步骤308之后的双极区域。
图6示出使用现有技术的具有栅极屏蔽(1)的LDMOS晶体管、使用金属屏蔽的具有栅极屏蔽(2)的LDMOS晶体管和使用HBT基极屏蔽的具有栅极屏蔽(3)的LDMOS晶体管的栅极-漏极电容Cgd的比较。其中屏蔽偏压为3.3伏特。能够看出，栅极屏蔽(3)比栅极屏蔽(1)具有更好性能，且稍微好于栅极屏蔽(2)的性能。
上文已经描述了本发明的各种实施例，应当理解，它们仅通过示例而非限制的方式提出。在未偏离本发明的精神和范围的情况下，能够根据本公开对所公开的实施例做出若干变化。因此，本发明的广度和范围不应当被上述实施例的任何一个所限制。相反，本发明的范围根据下述权利要求和它们的等同体限定。

Claims (18)

1.一种用于形成栅极屏蔽的方法，其包括：
在衬底上形成双极晶体管区域；
在所述衬底上形成金属氧化物半导体晶体管区域即MOS晶体管区域，所述MOS晶体管区域与所述双极晶体管区域间隔开；
在所述双极晶体管区域和所述MOS晶体管区域上方沉积多晶硅层；以及
使用单个掩膜刻蚀所述多晶硅层，从而形成：
位于所述双极晶体管区域之上的基极；和
位于所述MOS晶体管区域之上的栅极屏蔽。
2.根据权利要求1所述的方法，其中所述MOS晶体管区域包括垂直漏极金属氧化物半导体晶体管区域即VDMOS晶体管区域。
3.根据权利要求1所述的方法，其中沉积所述多晶硅层包括：在所述双极晶体管区域和所述MOS晶体管区域上方外延生长所述多晶硅层。
4.根据权利要求1所述的方法，其进一步包括：
在所述衬底上形成掩埋层，
其中形成所述双极晶体管区域包括：在所述掩埋层之上形成所述双极晶体管区域，以及
其中形成所述MOS晶体管区域包括：在所述掩埋层之上形成所述MOS晶体管区域。
5.根据权利要求1所述的方法，其进一步包括：
在所述MOS晶体管区域内形成基体区域；
在所述MOS晶体管区域内形成漏极阱，并且所述漏极阱与所述基体区域间隔开；以及
在所述基体区域之上形成栅极结构，并且所述栅极结构不与所述漏极阱重叠，
其中所述单个掩膜限定横向位于所述栅极结构之上并且延伸以部分重叠所述漏极阱的所述栅极屏蔽。
6.根据权利要求5所述的方法，其进一步包括：
在所述漏极阱内形成漏极区域；
形成耦合至所述栅极结构的栅极电极；以及
形成耦合至所述漏极区域的漏极电极，
其中所述单个掩膜限定位于所述栅极电极和所述漏极电极之间的所述栅极屏蔽。
7.根据权利要求5所述的方法，其进一步包括：
在所述漏极阱内形成漏极区域；
在所述基体区域内形成源极区域；
形成耦合至所述源极区域的源极电极；以及
形成耦合至所述漏极区域的漏极电极，
其中所述单个掩膜限定位于所述源极电极和所述漏极电极之间的所述栅极屏蔽。
8.根据权利要求5所述的方法，其中形成所述栅极结构在沉积所述多晶硅层和刻蚀所述多晶硅层之前进行。
9.根据权利要求1所述的方法，其进一步包括：
在所述MOS晶体管区域内形成基体区域；
在所述MOS晶体管区域内形成漏极阱，并且所述漏极阱与所述基体区域间隔开；
在所述MOS晶体管区域内形成浅沟槽隔离结构即STI结构，所述STI结构在所述漏极阱和所述基体区域之间；以及
在所述基体区域之上形成栅极结构，并且所述栅极结构不与所述漏极阱和所述STI结构重叠，
其中所述单个掩膜限定横向位于所述栅极结构之上并且延伸以部分重叠所述STI结构的所述栅极屏蔽。
10.根据权利要求1所述的方法，其进一步包括：
形成耦合至所述栅极屏蔽并且被配置为接收屏蔽偏压的栅极屏蔽电极。
11.根据权利要求1所述的方法，其中所述多晶硅层包括P掺杂硅化物材料。
12.根据权利要求1所述的方法，其进一步包括：
形成第一深沟槽隔离沟道，其横向围绕所述双极晶体管区域；以及
形成第二深沟槽隔离沟道，其横向围绕所述MOS晶体管区域。
13.一种用于形成栅极屏蔽的方法，其包括：
在衬底上形成双极晶体管区域；
在所述衬底上形成横向扩散金属氧化物半导体晶体管区域即LDMOS晶体管区域，所述LDMOS晶体管区域与所述双极晶体管区域间隔开；
在所述双极晶体管区域和所述LDMOS晶体管区域上方沉积多晶硅层；以及
使用单个掩膜刻蚀所述多晶硅层，从而形成：
位于所述双极晶体管区域之上的基极；和
位于所述LDMOS晶体管区域之上的栅极屏蔽。
14.根据权利要求13所述的方法，其进一步包括：
在所述LDMOS晶体管区域内形成基体区域；
在所述LDMOS晶体管区域内形成漏极阱，并且所述漏极阱与所述基体区域间隔开；以及
在所述基体区域之上形成栅极结构，并且所述栅极结构不与所述漏极阱重叠，
其中所述单个掩膜限定横向位于所述栅极结构之上并且延伸以部分重叠所述漏极阱的所述栅极屏蔽。
15.根据权利要求14所述的方法，其进一步包括：
在所述漏极阱内形成漏极区域；
形成耦合至所述栅极结构的栅极电极；以及
形成耦合至所述漏极区域的漏极电极，
其中所述单个掩膜限定位于所述栅极电极和所述漏极电极之间的所述栅极屏蔽。
16.一种用于形成栅极屏蔽的方法，其包括：
在衬底上形成双极晶体管区域；
在所述衬底上形成扩展漏极金属氧化物半导体晶体管区域即EDMOS晶体管区域，所述EDMOS晶体管区域与所述双极晶体管区域间隔开；
在所述双极晶体管区域和所述EDMOS晶体管区域上方沉积多晶硅层；以及
使用单个掩膜刻蚀所述多晶硅层，从而形成：
位于所述双极晶体管区域之上的基极；和
位于所述EDMOS晶体管区域之上的栅极屏蔽。
17.根据权利要求16所述的方法，其进一步包括：
在所述EDMOS晶体管区域内形成基体区域；
在所述EDMOS晶体管区域内形成漏极阱，并且所述漏极阱与所述基体区域间隔开；
在所述EDMOS晶体管区域内形成浅沟槽隔离结构即STI结构，所述STI结构在所述漏极阱和所述基体区域之间；以及
在所述基体区域之上形成栅极结构，并且所述栅极结构不与所述漏极阱和所述STI结构重叠，以及
其中所述单个掩膜限定横向位于所述栅极结构之上并且延伸以部分重叠所述STI结构的所述栅极屏蔽。
18.根据权利要求17所述的方法，其进一步包括：
在所述漏极阱内形成漏极区域；
形成耦合至所述栅极结构的栅极电极；以及
形成耦合至所述漏极区域的漏极电极，
其中所述单个掩膜限定位于所述栅极电极和所述漏极电极之间的所述栅极屏蔽。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9306013B2 (en) * 2014-05-23 2016-04-05 Texas Instruments Incorporated Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies
US9559199B2 (en) * 2014-12-18 2017-01-31 Silanna Asia Pte Ltd LDMOS with adaptively biased gate-shield
US11171215B2 (en) 2014-12-18 2021-11-09 Silanna Asia Pte Ltd Threshold voltage adjustment using adaptively biased shield plate
US10134641B2 (en) * 2015-05-21 2018-11-20 CoolStar Technology, Inc. Enhanced integration of DMOS and CMOS semiconductor devices
US10825905B2 (en) * 2016-06-01 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Thin poly field plate design
US10229917B2 (en) 2016-07-29 2019-03-12 International Business Machines Corporation Thin SRAM cell having vertical transistors
US10734321B2 (en) * 2017-09-28 2020-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of manufacturing same
JP7102934B2 (ja) * 2018-05-22 2022-07-20 株式会社デンソー 半導体装置
US10461182B1 (en) 2018-06-28 2019-10-29 Texas Instruments Incorporated Drain centered LDMOS transistor with integrated dummy patterns
US11152505B2 (en) 2018-06-28 2021-10-19 Texas Instruments Incorporated Drain extended transistor
US11374124B2 (en) 2018-06-28 2022-06-28 Texas Instruments Incorporated Protection of drain extended transistor field oxide
US20200013880A1 (en) * 2018-07-09 2020-01-09 Silterra Malaysia Sdn. Bhd. Integrated circuit device with faraday shield
US10615252B2 (en) * 2018-08-06 2020-04-07 Nxp Usa, Inc. Device isolation
US11031320B2 (en) 2018-11-30 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structures and methods for reducing process charging damages
CN110112210B (zh) * 2019-03-21 2022-11-25 中国电子科技集团公司第五十五研究所 一种射频ldmos的侧壁栅结构及其制备方法
US11552190B2 (en) 2019-12-12 2023-01-10 Analog Devices International Unlimited Company High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region
US11380759B2 (en) * 2020-07-27 2022-07-05 Globalfoundries U.S. Inc. Transistor with embedded isolation layer in bulk substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661048A (en) * 1995-03-21 1997-08-26 Motorola, Inc. Method of making an insulated gate semiconductor device
CN102656697A (zh) * 2009-11-02 2012-09-05 维西埃-硅化物公司 半导体装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5119149A (en) 1990-10-22 1992-06-02 Motorola, Inc. Gate-drain shield reduces gate to drain capacitance
US5252848A (en) 1992-02-03 1993-10-12 Motorola, Inc. Low on resistance field effect transistor
US5912490A (en) * 1997-08-04 1999-06-15 Spectrian MOSFET having buried shield plate for reduced gate/drain capacitance
US6001710A (en) 1998-03-30 1999-12-14 Spectrian, Inc. MOSFET device having recessed gate-drain shield and method
US6215152B1 (en) 1998-08-05 2001-04-10 Cree, Inc. MOSFET having self-aligned gate and buried shield and method of making same
US7427795B2 (en) * 2004-06-30 2008-09-23 Texas Instruments Incorporated Drain-extended MOS transistors and methods for making the same
US20070029283A1 (en) * 2005-08-02 2007-02-08 Micron Technology, Inc. Etching processes and methods of forming semiconductor constructions
KR101126933B1 (ko) * 2008-09-02 2012-03-20 주식회사 동부하이텍 폴리에미터형 바이폴라 트랜지스터, ｂｃｄ 소자, 폴리에미터형 바이폴라 트랜지스터의 제조 방법 및 ｂｃｄ 소자의 제조 방법
US9029952B2 (en) * 2012-04-19 2015-05-12 Macronix International Co., Ltd. Semiconductor structure and method of manufacturing the same
US9059276B2 (en) * 2013-05-24 2015-06-16 International Business Machines Corporation High voltage laterally diffused metal oxide semiconductor
US9306013B2 (en) * 2014-05-23 2016-04-05 Texas Instruments Incorporated Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661048A (en) * 1995-03-21 1997-08-26 Motorola, Inc. Method of making an insulated gate semiconductor device
CN102656697A (zh) * 2009-11-02 2012-09-05 维西埃-硅化物公司 半导体装置

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