CN102157557B - 一种基于纳米线器件的耐高压横向双向扩散晶体管 - Google Patents

一种基于纳米线器件的耐高压横向双向扩散晶体管 Download PDF

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CN102157557B
CN102157557B CN2011100297067A CN201110029706A CN102157557B CN 102157557 B CN102157557 B CN 102157557B CN 2011100297067 A CN2011100297067 A CN 2011100297067A CN 201110029706 A CN201110029706 A CN 201110029706A CN 102157557 B CN102157557 B CN 102157557B
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黄如
邹积彬
王润声
杨庚雨
艾玉洁
樊捷闻
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Peking University
Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明提供了一种基于纳米线器件的耐高压横向双向扩散晶体管，属于微电子半导体器件领域。该横向双扩散MOS晶体管包括沟道区、栅介质、栅区、源区、漏区、源端外延区以及漏端S型漂移区，沟道区是横向圆柱形硅纳米线结构，上面覆盖一层均匀栅介质，栅介质上层是栅区，栅区和栅介质完全包围沟道区，源端外延区位于源区和沟道区之间，漏端S型漂移区位于漏区和沟道区之间，漏端S型漂移区俯视图呈单个或多个S型结构，S型结构中间填充具有相对介电常数1～4的绝缘材料。本发明可提高基于硅纳米线MOS晶体管的横向双扩散晶体管的耐高压能力。

Description

一种基于纳米线器件的耐高压横向双向扩散晶体管
技术领域
本发明关于微电子半导体器件领域中横向双扩散MOS晶体管，具体涉及一种基于硅纳米线MOS晶体管的适合应用在射频功率放大器或其他高压电路的横向双扩散晶体管。
背景技术
随着射频电路的发展，射频器件在无线通讯如个人/商业无线通讯设备，移动通讯设备甚至是军用雷达等重要领域，受到的关注越来越多，需求量也逐年增大。在射频电路收发器系统中，功率放大器是一个非常重要的模块。而功率放大器通常要求处理较大幅度的信号，并要求其稳定性好，这就是要求功率放大器的电路核心元器件有很好的耐高压能力。通常这部分电路的核心器件采用工艺复杂价格昂贵的特殊材料制作或平面横向双扩散场效应晶体管(planar lateral double-diffused MOS transistor，planar LDMOS)制作。虽然平面横向双扩散场效应晶体管与现有的CMOS工艺兼容，但在CMOS工艺中光刻技术等关键工艺步骤提升有限，且先进技术无法达到批量生产目的的背景下，其平面晶体管的结构决定了其成本的不断提高和成品率的下降。目前，以45nm平面管工艺为例，该技术已经达到了工艺的极限，会对平面管引入严重的短沟道效应，致使器件的关态电流增大、跨导减小等。同时，由于平面结构的横向双扩散场效应晶体管正常工作时有较大的漏/衬底结反向偏压，所以存在较大的漏/衬底泄漏电流，影响输出电流的精度，甚至这个较大的漏/衬底反向偏压会导致器件提前击穿，降低LDMOS的耐高压能力。
硅纳米线MOS场效应晶体管(Silicon Nanowire MOSFET)一方面可以达到优秀的栅控能力、缓解短沟道效应，克服了普通平面晶体管很难缩小器件特征尺寸的问题；另一方面由于其悬浮沟道结构(floating channel)，达到无衬底的效果，由其构成的LDMOS可以克服平面LDMOS大的泄漏电流和提前击穿的问题。
所以，基于纳米线MOS场效应晶体管制作的耐高压横向双扩散场效应晶体管为更进一步增加超大规模集成电路的集成度和性能，尤其为工作可靠稳定的功率放大器模块或其他高压电路提供了一个优良的选择。
发明内容
本发明针对现有技术，提供了一种基于硅纳米线MOS晶体管的适合射频功率放大器或其他高压电路的横向双扩散晶体管。
本发明的技术方案是：
一种基于硅纳米线MOS晶体管的耐高压横向双扩散MOS晶体管，包括沟道区、栅介质、栅区、源区、漏区、源端外延区以及漏端S型漂移区。
所述沟道区是环栅硅纳米线场效应晶体管的核心部分，横向圆柱形结构，上面覆盖一层均匀栅介质，栅介质上层是栅区，栅区和栅介质完全包围硅纳米线。沟道区的长度取值范围是10纳米～10微米。圆柱形半径取值范围是3～5纳米，不掺杂。栅介质厚度取值范围是1～2.5纳米。栅区厚度范围是10纳米～5微米。
所述源区和漏区上下表面齐平，分别连接源端外延区和漏端S型漂移区。采用高浓度掺杂，掺杂浓度取值范围是1020～1021cm-3。
所述源端外延区位于源区和沟道区之间，其特征是其掺杂浓度与源区相同，以达到十分小的电阻。其长度取值范围是20纳米～100纳米。保持一定长度的原因是降低漏区与栅区的寄生电容。其掺杂浓度取值范围是1020～1021cm-3。
所述漏端S型漂移区位于漏区和沟道区之间，其结构特点是：
(1)相比源端外延区，漏端S型漂移区有更低的掺杂浓度1012～1018cm-3。
(2)漏端S型漂移区俯视图呈单个或多个S型结构。整体长度为1微米～2微米。S型结构中每个折回尺度为50纳米～100纳米(纵向)×100纳米～200纳米(横向)。S型折回的个数取值范围是1～5。
(3)S型结构中间填充具有低相对介电常数的绝缘材料。相对介电常数取值范围1～4。
与现有技术相比，本发明的作用是：
基于硅纳米线MOS晶体管制作适合射频功率放大器或其他高压电路的横向双扩散晶体管，避免了平面LDMOS由于较大的漏/衬底电压所引入的漏/衬底电流，避免了漏/衬底结反向击穿缩小LDMOS击穿电压。同时由于硅纳米线器件优秀的栅控能力，减小了关态电流，达到了较大的跨导。漏端S型漂移区的作用是，通过低掺杂浓度的多折回S型结构和填充在S型折回之间的低相对介电常数材料，使得更多的电势降在折回周围的绝缘材料中，从而降低沟道区至漏区载流子路径方向电场的最高强度，使载流子路径方向电场均匀分布，避免了高强度电场可能导致的雪崩击穿效应，有利于提高元器件的击穿电压。
附图说明
图1是本发明中介绍的基于硅纳米线MOS晶体管的横向双扩散晶体管的俯视剖面示意图。图中：
1-沟道区，2-栅介质，3-栅区，4-源端外延区，5-漏端S型漂移区，6-S型漂移区折回周围低相对介电常数绝缘介质，7-源区，8-漏区。
图2是纳米线结构剖面示意图，图中：
1-沟道区，2-栅介质(环形覆盖)，3-栅区(环形覆盖)。
图3至图9为本发明制备流程示意图。
图3中：
12-重掺杂源端，13-重掺杂漏端，14-掩模，15-硅片衬底。
图4中：
16-掩模，17-轻掺杂区。
图5中：
18-S型掩模
图6中：
19-S型掩模，20-轻掺杂区，21-重掺杂源区，22-重掺杂漏区。
图7中：
23-厚氧化层淀积，24-各向同性腐蚀沟道下方，掏空部分。
图8中：
25-源端外延区，26-沟道区，27-漏端S型漂移区，28-氧化层。
图9中：
29-低相对介电常数绝缘介质，30-栅区，31-厚氧化层
具体实施方式
下面结合附图和具体实施方式对本发明作进一步详细描述：
图1结构是本发明中介绍的基于硅纳米线MOS晶体管的横向双扩散晶体管核心部分的俯视剖面示意图。其结构与一般的常规硅纳米线MOS晶体管区别在于：
(1)沟道部分和漏区的连接方式，本发明的以漏端S型漂移区为连接，形状特点为S型。
(2)沟道部分和漏区的连接区，(对比本发明，此连接区为漏端S型漂移区)，掺杂浓度不同，本发明的掺杂浓度要低于常规纳米线MOS晶体管。
(3)本发明强调在S型漂移区折回间填充材料为低相对介电常数绝缘介质，与常规纳米线MOS晶体管只填充二氧化硅不同。
同时，其结构与一般LDMOS晶体管区别在于：
(1)如图2所示，本发明沟道区为围栅结构，这样有利于减小短沟效应，同时避免漏/衬底漏电和击穿。
(2)沟道部分和漏区的连接区载流子流动方向不同，本发明中载流子沿着S型的折回区域流动，而一般LDMOS是平面单方向流动或垂直与硅片方向流动。
上述各种区别有利于提高基于硅纳米线MOS晶体管的横向双扩散晶体管的耐高压能力。
本发明可以实现n型和p型基于硅纳米线MOS晶体管的横向双扩散晶体管。图1中所示，如选择源区，漏区，源端外延区为n型重掺杂，漏端S型漂移区为n型轻掺杂，则可以实现n型基于硅纳米线MOS晶体管的横向双扩散晶体管。如选择源区，漏区，源端外延区为p型重掺杂，漏端S型漂移区为p型轻掺杂，则可以实现p型基于硅纳米线MOS晶体管的横向双扩散晶体管。
下面以制作n型基于硅纳米线MOS晶体管的横向双扩散晶体管为例，说明制作流程：
(1)选取体硅片，利用硬掩模定义源区，漏区，高浓度n型掺杂。掺杂浓度取值范围是1020～1021cm-3。源区，漏区深度为100纳米～1微米。如图3侧面剖面图所示。
(2)去掉(1)中硬掩模，利用另一片硬掩模定义轻掺杂区，并小剂量n型掺杂，为漏端S型漂移区的形成做准备。掺杂浓度1012～1018cm-3。如图4侧面剖面图所示。由于此步骤与(1)中定义的源漏区已有高浓度的n型杂质，此步不会对源漏区产生影响。
(3)去掉(2)中硬掩模，制作S型硬掩模，其侧面剖面图如图5所示，其俯视图如图6所示。漏端S型漂移区俯视图呈单个或多个S型结构。整体长度为1微米～2微米。S型结构中每个折回尺度为50纳米～100纳米(纵向)×100纳米～200纳米(横向)。S型折回的个数取值范围是1～5。
(4)淀积厚氧化层，进行各向同性腐蚀源端外延区，沟道区和漏端S型漂移区下方的硅衬底。下面部分掏空。掏空深度为100纳米～1微米，如图7所示。
(5)去掉硬掩模，氧化减细源端外延区，沟道区和漏端S型漂移区，同时为沟道区形成一层环绕的栅介质。圆柱形半径取值范围是3～5纳米。栅介质厚度取值范围是1～2.5纳米，如图8所示。
(6)制作栅区，栅区厚度范围是10纳米～5微米。在源端外延区填充二氧化硅。去掉漏端S型漂移区上面覆盖的一层二氧化硅，在漏端S型漂移区填充低相对介电常数绝缘介质。其相对介电常数为1～4。如图9所示。
漏端S型漂移区通过低掺杂浓度的多折回S型结构和填充在S型折回之间的低相对介电常数材料，使得更多的电势降在折回间的绝缘材料中，从而降低沟道区至漏区载流子路径方向电场的最高强度，使载流子路径方向电场均匀分布，避免了高强度电场可能导致的雪崩击穿效应，有利于提高元器件的击穿电压。
后面的工艺流程和常规硅纳米线MOS晶体管完全一样。先后进行：平坦化，淀积隔离层，光刻引线孔，淀积金属，光刻引线，钝化等等。
以上通过详细实例描述了本发明所提供的基于硅纳米线MOS晶体管的横向双扩散晶体管，上面描述的应用场景和实施例，并非用于限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，可以做各种的更动和润饰，因此本发明的保护范围视权利要求范围界定。

Claims (7)

1.一种横向双扩散MOS晶体管，其特征在于，包括沟道区、栅介质、栅区、源区、漏区、源端外延区以及漏端S型漂移区，所述沟道区是横向圆柱形硅纳米线结构，上面覆盖一层均匀栅介质，栅介质上层是栅区，栅区和栅介质完全包围沟道区，所述源端外延区位于源区和沟道区之间，所述漏端S型漂移区位于漏区和沟道区之间，漏端S型漂移区呈单个或多个S型结构，S型结构中间填充具有相对介电常数1～4的绝缘材料。
2.如权利要求1所述的晶体管，其特征在于，漏端S型漂移区长度为1微米～2微米，S型结构中每个折回尺度为纵向50纳米～100纳米，横向100纳米～200纳米，S型折回的个数取值范围是1～5。
3.如权利要求2所述的晶体管，其特征在于，漏端S型漂移区的掺杂浓度是1012～1018cm-3。
4.如权利要求1所述的晶体管，其特征在于，沟道区不掺杂，其长度取值范围是10纳米～10微米，其半径取值范围是3～5纳米。
5.如权利要求1所述的晶体管，其特征在于，栅介质厚度取值范围是1～2.5纳米，栅区厚度范围是10纳米～5微米。
6.如权利要求1所述的晶体管，其特征在于，源区和漏区上、下表面齐平，采用高浓度掺杂，掺杂浓度取值范围是1020～1021cm-3。
7.如权利要求1所述的晶体管，其特征在于，源端外延区掺杂浓度与源区相同，其长度取值范围是20纳米～100纳米，其掺杂浓度取值范围是1020～1021cm-3。
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