CN202721131U - 一种垂直型半导体器件 - Google Patents

一种垂直型半导体器件 Download PDF

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CN202721131U
CN202721131U CN2012200225374U CN201220022537U CN202721131U CN 202721131 U CN202721131 U CN 202721131U CN 2012200225374 U CN2012200225374 U CN 2012200225374U CN 201220022537 U CN201220022537 U CN 201220022537U CN 202721131 U CN202721131 U CN 202721131U
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gate
semiconductor device
substrate
electrode
grid
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唐纳德·迪斯尼
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本发明公开了一种垂直型半导体器件。该垂直型半导体器件包括：衬底，具有第一表面以及与第一表面相对的第二表面；外延层，位于衬底的第一表面，具有与衬底的第一表面相对的第三表面；源极区和栅极，位于外延层中并邻近第三表面；源极电极，与源极区耦接并与栅极隔离；漏极电极，位于衬底的第二表面；第一栅极电极，制作于衬底的第二表面附近，与衬底隔离；以及深栅极接触，将栅极耦接至第一栅极电极。

Description

一种垂直型半导体器件
技术领域
本实用新型的实施例涉及一种半导体器件，尤其涉及一种垂直型半导体器件。 
背景技术
在功率管理应用中，为了减小尺寸和成本，将诸如金属氧化物半导体场效应晶体管（MOSFET）、结型场效应晶体管（JFET）等分立的半导体器件或者其他器件与集成电路共同封装在一起已成为主要趋势。在大多数高电压和/或大电流的功率管理应用中通常采用垂直型分立晶体管，例如具有集成肖特基二极管的垂直型功率MOSFET、垂直型JFET或者场效应晶体管（FET）等垂直型功率晶体管，并将该垂直型分立晶体管与其集成控制电路封装在一起，以在减小封装尺寸和节约成本的同时实现良好的功率管理性能。 
具有集成肖特基二极管的垂直型功率MOSFET、JFET、FET或者其他垂直型晶体管的半导体芯片通常包括位于底面的漏极电极或阴极电极，以及位于顶面的栅极电极。在许多电源管理应用中，常将N型垂直型MOSFET用作低侧开关管，这样该垂直型MOSFET的源极电极耦接至最低的电位（例如地），电气负载耦接于漏极电极和较高的电位（例如VDD）之间。当通过调节栅源电压来控制垂直型MOSFET的导通和关断时，源极电压保持相对不变，而漏极电压在高压和低压之间变换。由于漏极电极位于MOSFET芯片的底面，其常常被连接至封装的引线框架。而在实际的大功率器件应用场合，常常将封装的引线框架露出以获得良好的散热性能。引线框架上的高瞬变电压，会导致露出的引线框架成为辐射电磁干扰源并需要电隔离。 
现有的共装解决方案（co-package solution, 即在同一封装中内置控制芯片和垂直型MOSFET)，采用具有底侧漏极的垂直型MOSFET。如前面所述，漏极产生的高瞬变电压会造成EMI和需要电隔离的问题。而且，由于MOSFET的漏极与控制芯片衬底的电压不同，因而不能将它们电连接至同一引线框架。第一种现有技术解决方案采用非导电的环氧树脂将控制芯片附着至引线框架上。这一方案提供了所需的隔离，却影响了散热性能（即将控制芯片所产生的热量耗散出封装的能力）。另一种方案使用一种具有分离引线框架的特殊封装，一部分引线框架位于控制芯片下方，另一部分引线框架与前一部分引线框架分离且隔离，位于MOSFET的下方。这种解决方案增加了封装成本，并使得封装与印制电路板的附着工艺复杂化。 
实用新型内容
为解决上述技术问题，本实用新型提供一种垂直型半导体器件，包括：衬底，具有第一表面以及与第一表面相对的第二表面；外延层，位于衬底的第一表面，具有与衬底的第一表面相对的第三表面；源极区和栅极，位于外延层中并邻近第三表面；源极电极，与源极区耦接并与栅极隔离；漏极电极，位于衬底的第二表面；第一栅极电极，制作于衬底的第二表面附近，与衬底隔离；以及深栅极接触，将栅极耦接至第一栅极电极。 
在一个实施例中，深栅极接触至少延伸穿过衬底并至少延伸穿过一部分外延层，以将栅极电耦接至第一栅极电极。 
在一个实施例中，深栅极接触制作于深沟槽中，在该深沟槽的侧壁制作有绝缘材料，在该深沟槽中填充有导电材料。 
在一个实施例中，栅极制作于多个栅极沟槽中，该多个栅极沟槽位于靠近源极区的外延层中。在进一步的实施例中，其中在每个栅极沟槽的侧壁和底部制作有绝缘材料，在每个栅极沟槽中填充有导电材料。 
在一个实施例中，垂直型半导体器件进一步包括位于外延层中的栅极接触沟槽，其中栅极接触沟槽与栅极沟槽耦接。在进一步的实施例中，其中在栅极接触沟槽的侧壁制作有绝缘材料，在栅极接触沟槽中填充有导电材料。在另一个实施例中，其中栅极接触沟槽比栅极沟槽宽。 
在一个实施例中，其中深栅极接触具有接触第一栅极电极的第一端和接触栅极接触沟槽中导电材料的第二端。 
在一个实施例中，该垂直型半导体器件进一步包括邻近第三表面的第二栅极电极，其中第二栅极电极与栅极耦接并与源极区隔离。在进一步的实施例中，深栅极接触具有接触第一栅极电极的第一端和接触第二栅极电极的第二端。 
根据本实用新型实施例的垂直型半导体器件，通过基本上延伸通过垂直型器件芯片厚度的深沟槽接触，将与漏极电极处于同一表面的栅极电极耦接至埋栅区，或者耦接至与源极电极处于同一表面的栅极电极，不仅可以节约成本，在引线框架露出时不需要隔离，而且可降低产生EMI的风险。 
附图说明
结合以下附图阅读本实用新型实施例的详细描述可以更好地理解本实用新型。应理解，附图的特征不是按比例绘制的，而是示意性的。为了说明清晰，层和区域的尺寸可被放大。 
图1是根据本实用新型一实施例的多芯片半导体器件100的结构示意图； 
图2A-2C是根据本实用新型一实施例的各种垂直型半导体器件的剖视图；
图3A-3D是根据本实用新型一实施例的垂直型半导体器件在制作过程中的剖视图。
具体实施方式
下面参照附图描述本实用新型的各实施例。为了更好地理解本实用新型，在下面的描述中给出了一些具体的细节，例如示例电路以及这些示例电路中元器件的示例值。本领域的技术人员应理解，缺少一个或多个具体细节，或者增加其他的元件或者材料等，本实用新型同样可以实施。此外，为了清楚地阐述本实用新型，在本实用新型的描述中省去了一些公知的结构、材料或步骤的详细描述以及示意图。 
在整个说明书和权利要求书中，对“左”、“右”、“内”、“外”、“前”、 “后”、“向上”、“向下”、“顶部”、“在顶部”、“在底部”、“在正下方”、“在上方”、“在下方”以及其它类似方位词语的使用都只是为了说明的目的，并不是为了表达其相对位置的不可变。本领域普通技术人员应当理解，本实用新型的实施例中提供的方位词语在不同的适用场合下是可以变化的，例如，文中所描述的方向仅仅是示意性的，并不仅限于此方向，其他方向也是可能的。此外，本文所称“耦接”的是指以电或者非电的形式直接或间接连接。 
本实用新型公开了一种垂直型分立器件，该垂直型分立器件的源极电极位于芯片底面，漏极电极和栅极电极位于同一表面。该垂直型分立器件允许将其源极电极连接至封装的引线框架。当该垂直型分立器件作为下侧开关管时，其源极电极接地，因而露出的引线框架不需要任何的专门隔离，而且，与传统的分立垂直型器件相比，本实用新型提供的垂直型分立器件的EMI会减小。 
为描述方便，本实用新型以制作于硅半导体衬底上和/或位于硅半导体衬底中的N沟道垂直型器件为例来进行说明。本领域的技术人员应该理解，具有相反掺杂类型的P沟道垂直型器件同样满足本实用新型的精神和保护范围。在本实用新型的实施例中，常选用多晶硅来填充沟槽。这些实施例并不限制导体和其他材料类型（例如金属、半导体、金属-半导体和或他们的组合）的选择，只要所选的材料与器件制作工艺过程中的其它方面兼容即可。因此，本文所称“填充聚乙烯的”和“填充多晶硅的”可包括除硅之外的其他材料或者其他材料的组合。 
图1是根据本实用新型一实施例的多芯片半导体器件100的结构示意图。多芯片半导体器件100包括垂直型分立晶体管芯片101和集成电路芯片103。垂直型晶体管分立芯片101和集成电路芯片103共装于同一个封装105中。在一个实施例中，垂直型分立晶体管芯片101是功率分立晶体管芯片，例如垂直型双扩散金属氧化物半导体场效应管（VDMOS）。在一个实施例中，集成电路芯片103是控制垂直型分立晶体管101开通与关断的控制芯片。垂直型晶体管芯片101的底面101B用作源极电极。原本制作于底面101B的栅极电极经深沟槽被引到上表面101T。该深沟槽中填充有导电材料，例如钨或重掺杂的多晶硅。这样可将栅极电极与漏极或阴极电极制作在同一表面。 
如图1所示的实施例中，垂直型分立晶体管芯片101和集成电路芯片103均附着于单个引线框架107上，并且均通过引线键合111连接至引脚109。这样垂直型分立晶体管芯片101与集成电路芯片103可被置于同一引线框架107上，与现有的共装器件相比可降低成本。而且，垂直型分立晶体管芯片101的源极电极可附着至引线框架107，因此，在垂直型分立晶体管101作为低侧开关管被用于源极电极接地的场合，在引线框架露出时不需要增加专门的隔离，还同时降低了产生EMI的风险。此外，还可以得到较好的散热性能。如果要将电信号传送给集成电路芯片103和垂直型分立晶体管芯片101的漏极，这种栅极电极与漏极电极处于同一表面的垂直型分立晶体管芯片101可以提供上侧的通道给分立晶体管101的漏极，使得连接方便。 
图2A是根据本实用新型一实施例的垂直型半导体器件200A的剖视图，半导体器件200A的栅极电极和漏极电极位于同一表面。半导体器件200A包括重掺杂的N+衬底202、N-外延层204、P型体区206、栅极沟槽208以及N+源极区214。其中N+衬底202用作半导体器件200A的漏极，具有第一表面S1和与第一表面相对的第二表面S3。N-外延层204制作于N+衬底202的第一表面S1，具有与N+衬底202的第一表面S1相对的第三表面S2。P型体区206位于N-外延层204中。栅极沟槽208制作于P型体区206和N-外延层204中，每个栅极沟槽208中均填充有栅极210和栅氧层212。其中栅极210包括导电材料，例如重掺杂的多晶硅。栅氧层212制作于栅极沟槽208的侧壁和底部，将栅极210与P型体区206以及N-外延层204隔离开来。N+源极区214制作于靠近栅氧层212的P型体区206中、邻近第三表面S2。源极电极216用导电材料制作，例如金属。源极电极216位于半导体器件200A的底侧，电耦接至N+源极区214和P型体区206。层间介电层218位于源极电极216和外延层204的第三表面S2之间，防止源极电极216与栅极210发生短路。 
此外，半导体器件200A还包括位于N-外延层204其他区域中的栅极接触沟槽220，利用栅极接触沟槽220来实现栅极210与底侧栅极电极222的接触。与栅极沟槽208的结构类似，栅极接触沟槽220填充有栅极接触224和绝缘材料226。其中栅极接触224包括导电材料，例如重掺杂的多晶硅。绝缘材料226（例如氧化物）制作于栅极接触沟槽220的侧壁和底部。在一个实施例中，栅极接触224和栅极210包括相同的材料，并在同样的时间制作。在一个实施例中，栅氧化层212和绝缘材料226包括相同的材料，并在同样的时间制作。在一个实施例中，栅极电极222穿过层间介电层218形成栅极接触228。在一个实施例中，为了简化栅极接触228的制作，栅极接触沟槽220比栅极沟槽208宽。栅极接触沟槽220的深度与栅极沟槽208的深度可以不同。栅极沟槽208与栅极接触沟槽220彼此电耦接使得栅极电极222可将电信号传送至栅极210。在一个实施例中，栅极沟槽208和栅极接触沟槽220通过栅极沟槽208或者栅极接触沟槽220的横断面连接在一起。 
半导体器件200A进一步包括深沟槽230，用于将栅极接触224连接至顶侧栅极电极240。深沟槽230位于或者靠近N+衬底202的第二表面S3。深栅极接触236包括导电材料，例如钨或者重掺杂的多晶硅。深栅极接触236延伸穿过深沟槽230并提供顶侧栅极电极240与栅极接触224之间的电接触，将栅极210耦接至栅极电极240。深沟槽绝缘层234包括绝缘材料（例如氧化物），制作于深沟槽230的侧壁，将深栅极接触236与衬底202和外延层204隔离开。 
在一个实施例中，介电层232制作于N+衬底202的第二表面S3上。在介电层232的表面形成金属化层，图案化并蚀刻该金属化层来制作位于半导体器件200A顶侧表面上的分隔的漏极电极238和栅极电极240。形成金属化层时，应采用可实现从封装到漏极电极238和栅极电极240的电连接的金属化工艺。例如，若在封装连接时使用键合线，那么对漏极电极238和栅极电极240采用的金属化工艺应该与引线键合工艺相适应。 
改进的垂直型分立晶体管有多种可变类型，其漏极电极和栅极电极均制作于同一表面上。图2B-2C是根据本实用新型几个实施例的垂直型半导体器件的剖视图。图2B是根据本实用新型一个实施例的垂直型半导体器件200B的剖视图。在图2B所示的实施例中，半导体器件200B不包括位于半导体器件200A（图2A中）底侧的栅极电极，因而半导体器件200B的底面可全部用于制作源极电极216。图2C是根据本实用新型一个实施例的垂直型半导体器件200C的剖视图。在图2C所示的实施例中，半导体器件200C包括深沟槽230。深沟槽230贯穿介电层232、N+衬底202、N-外延层204和层间介电层218以接触底侧的栅极电极222。 
图2A-2C 所示的半导体器件200A-200C均使用沟槽栅MOSFET作为根据本实用新型实施例制作的半导体器件的例子。实际上，其他的垂直型器件，例如传统的平面栅MOSFET、具有薄膜栅的垂直双扩散金属氧化物半导体（VDMOS）、或者具有衬底漏极/阴极，且其源极/阳极以及栅极区靠近器件顶面，并且通过深沟槽使栅极电极与漏极电极位于同一表面的任意半导体器件，也适用于本实用新型。 
图3A-3D是根据本实用新型一实施例的垂直型半导体器件在制作过程中的剖视图。该垂直型半导体器件的漏极电极与栅极电极位于同一表面上。图3A所示垂直型半导体器件300A完成了一部分制作步骤。垂直型器件300A可以是任意底侧衬底被作为器件漏极或阴极的半导体器件，例如垂直型沟槽MOSFET、VDMOS或垂直型JFET。 
图3A中的垂直型半导体器件300A为沟槽栅MOSFET。在一个实施例中，MOSFET包括用作漏极的重掺杂的N+衬底301，衬底301具有第一表面S1和与第一表面相对的第二表面S3。N-外延层303生长于N+衬底301的第一表面S1上。在N-外延层303中制作P型体区305、N+源极区307、栅极沟槽309以及栅极接触沟槽311。栅氧层313形成于栅极沟槽309的侧壁和底部，绝缘材料315形成于栅极接触沟槽311的侧壁和底部。在一个实施例中，绝缘材料315与栅氧层313包括相同的材料，可同时制作。栅极317制作于栅极沟槽309中，栅极接触319制作于栅极接触沟槽311中。在一个实施例中，栅极317和栅极接触319包括相同的材料（例如重掺杂的多晶硅），也可同时制作。介电层321将源极电极323A与栅极电极323B同下面的体区305、源极区307以及栅极317分隔开来。介电层321可包括碲掺杂玻璃（Tellurium doped glass）、磷硅玻璃（Phosphosilicate glass）、硼磷硅玻璃（Borophosphosilicate glass）或者旋压玻璃（Spin-on glass）。源极接触开口325允许源极电极323A和N+源极区307以及P型体区305之间具有电接触。栅极开口327允许栅极电极323B和栅极317之间具有电接触。 
在一个实施例中，制作垂直型器件300A的步骤包括步骤A到步骤K。 
步骤A：在N+衬底301的第一表面S1制作N-外延层303，其中外延层303的露出面S2与N+衬底301的第一表面S1相对。 
步骤B：从外延层303的露出面S2开始蚀刻，制作位于外延层303中的栅极沟槽309。 
步骤C：从外延层303的露出面S2开始蚀刻，制作位于外延层303中的栅极接触沟槽311。在一个实施例中，步骤B和步骤C在同一蚀刻步骤进行。 
步骤D：在栅极沟槽309的侧壁和底部制作栅氧层313，在栅极接触沟槽311的侧壁与底部制作绝缘材料315。在一个实施例中，绝缘材料315与栅氧层313包括相同的材料，并在同一步骤进行制作。 
步骤E：向栅极沟槽309内淀积多晶硅以形成栅极317，向栅极接触沟槽311内淀积导电材料以形成栅极接触319。在一个实施例中，栅极317和栅极接触319都由多晶硅构成，并在同一淀积步骤进行制作。在一个实施例中，栅极317和栅极接触319的制作材料和制作步骤相同，栅极317和栅极接触319可以被统称为栅极。 
步骤F：在N-外延层303中扩散P型掺杂以形成体区305，体区305靠近栅氧层313且不会延伸至栅极沟槽309的底部之下。 
步骤G：在P型体区305的表面区域扩散N型杂质以形成N+源极区307。 
步骤H：在外延层303的露出面S2（即在N-外延层303、N+源极区307、栅极317以及栅极接触319的露出区域之上）制作介电层321。 
步骤I：蚀刻介电层321来制作源极接触开口325和栅极开口327。 
步骤J：在介电层321之上制作金属化层，该金属化层延伸入源极接触开口325和栅极开口327以接触N+源极区307和栅极接触319。 
步骤K：蚀刻上述金属化层以形成源极电极323A和栅极电极323B。 
如图3B所示，通过翻转用于建构器件300A的晶圆将垂直型器件300A颠倒过来。N+衬底301与典型的垂直型半导体器件的衬底一样被减至很薄。在一个实施例中，N+衬底301被做薄后的最终厚度为50μm~150μm。介电层329被淀积于薄衬底301的第二表面S3上，该第二表面S3与第一表面S1平行。然后在介电层329上制作掩膜层来确定位于栅极接触沟槽311上方的开口。利用该掩膜层蚀刻深沟槽331，使深沟槽331贯穿介电层329、衬底301、N-外延层303到达栅极接触319。在另一个实施例中，在介电层329上制作掩膜层以确定开在栅极电极323B顶侧的开口，深沟槽331被蚀刻至到达位于垂直型器件底侧的介电层321。深沟槽331采用长宽比非常高的蚀刻工艺来制作。在一个实施例中，采用高长宽比、高速且对氧化物选择性良好的商用蚀刻机来快速蚀刻衬底301和外延层303，并在蚀刻至位于栅极接触沟槽311底部的栅氧层313时停止蚀刻。例如，商用蚀刻机的长宽比大于50：1，其蚀刻硅的速度大于10μm/min（每分钟10微米）。 
如图3C所示，在深沟槽331的侧壁和底部制作绝缘材料333。蚀刻位于深沟槽331底部的绝缘材料333和位于栅极接触沟槽331底部的绝缘材料315，使得深沟槽311穿通至多晶硅栅极接触319。然后向深沟槽331内填充导电材料335（例如钨或者重掺杂的多晶硅）。在一个实施例中，采用传统的填充技术（例如钨或多晶硅淀积技术）和回蚀技术来填充深沟槽331。在其它实施例中，其他合适的技术也可用于填充深沟槽331。 
如图3D所示，在介电层329中制作漏极接触开口337以露出N+衬底301。在介电层329的上表面淀积金属化层，该金属化层延伸进漏极接触开口337以接触衬底301。然后，金属化层被蚀刻以形成漏极电极339A和栅极电极339B。栅极电极339B与导电材料335电接触以提供电信号给栅极317。 
上述实施例中的器件与制作步骤均涉及N沟道器件，由于P沟道器件的各个掺杂区域的类型与N沟道器件相反，因此本实用新型的实施例仅仅需要稍作改变就可以应用于P沟道器件。具有顶侧栅极电极和漏极电极的垂直型半导体器件及其制作方法均适用于N沟道和P沟道器件。 
本实用新型的实施例公开了一种栅极电极与漏极电极位于同一表面的垂直型分立器件。这种垂直型分立器件包括深沟槽，该深沟槽延伸通过垂直型分立器件芯片的相当一部分厚度，以提供从与漏极电极处于同一表面的栅极电极到埋栅区，或者到与源极电极处于同一表面的栅极电极的接触。其中埋栅区与传统的垂直型分立晶体管一样，制作于源极区附近。 
根据本实用新型一实施例的垂直型分立器件可贴装于封装引线框架上，其中源极电极可通过导电的环氧树脂附着至封装引线框架上，或者该垂直型分立器件包括软焊层（例如铜或银），使得源极电极可被软焊至引线框架。深沟槽的制作方法包括采用各向异性蚀刻能力强的蚀刻工艺来形成深而窄的洞，向这些深而窄的洞部分地填充绝缘材料以将深沟槽与周围的漏极材料隔离开来，然后向深沟槽内填充导电材料（例如钨或重掺杂的多晶硅）。采用这种方法，可将传统的与源极电极位于同一表面的栅极电极制作于漏极电极所在的表面上。漏极电极与栅极电极采用能为垂直型分立器件的漏极区和填充于深沟槽中的导电材料提供良好接触的材料。 
栅极电极与漏极电极位于同一表面的垂直型分立晶体管对高电压和大电流的应用是有帮助的。根据本实用新型实施例的垂直型分立器件，垂直型分立晶体管芯片与其控制芯片可安置于同一引线框架上，可以节约成本，在引线框架露出时不需要隔离，并且可降低产生EMI的风险。此外，根据本实用新型实施例的垂直型分立器件还具有更好的散热性能，并可使得单个电源对分立晶体管的漏极和晶体管控制芯片的供电更加方便。 
上述本实用新型的说明书和实施仅仅以示例性的方式对本实用新型进行了说明，这些实施例不是完全详尽的，并不用于限定本实用新型的范围。对于公开的实施例进行变化和修改都是可能的，其他可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本实用新型所公开的实施例的其他变化和修改并不超出本实用新型的精神和保护范围。 

Claims (11)

1.  一种垂直型半导体器件，包括：
衬底，具有第一表面以及与第一表面相对的第二表面；
外延层，位于衬底的第一表面，具有与衬底的第一表面相对的第三表面；
源极区和栅极，位于外延层中并邻近第三表面；
源极电极，与源极区耦接并与栅极隔离；
漏极电极，位于衬底的第二表面；
第一栅极电极，制作于衬底的第二表面附近，与衬底隔离；以及
深栅极接触，将栅极耦接至第一栅极电极。
2.  如权利要求1所述的垂直型半导体器件，其特征在于，其中深栅极接触至少延伸穿过衬底并至少延伸穿过一部分外延层，以将栅极电耦接至第一栅极电极。
3.  如权利要求1所述的垂直型半导体器件，其特征在于，其中深栅极接触制作于深沟槽中，在该深沟槽的侧壁制作有绝缘材料，在该深沟槽中填充有导电材料。
4.  如权利要求1所述的垂直型半导体器件，其特征在于，其中栅极制作于多个栅极沟槽中，该多个栅极沟槽位于靠近源极区的外延层中。
5.  如权利要求4所述的垂直型半导体器件，其特征在于，其中在每个栅极沟槽的侧壁和底部制作有绝缘材料，在每个栅极沟槽中填充有导电材料。
6. 如权利要求4所述的垂直型半导体器件，其特征在于，该垂直型半导体器件进一步包括位于外延层中的栅极接触沟槽，其中栅极接触沟槽与栅极沟槽耦接。
7.  如权利要求6所述的垂直型半导体器件，其特征在于，其中在栅极接触沟槽的侧壁制作有绝缘材料，在栅极接触沟槽中填充有导电材料。
8.  如权利要求6所述的垂直型半导体器件，其特征在于，其中栅极接触沟槽比栅极沟槽宽。
9.  如权利要求7所述的垂直型半导体器件，其特征在于，其中深栅极接触具有接触第一栅极电极的第一端和接触栅极接触沟槽中导电材料的第二端。
10.如权利要求1所述的垂直型半导体器件，其特征在于，该垂直型半导体器件进一步包括邻近第三表面的第二栅极电极，其中第二栅极电极与栅极耦接并与源极区隔离。
11.如权利要求10所述的垂直型半导体器件，其特征在于，其中深栅极接触具有接触第一栅极电极的第一端和接触第二栅极电极的第二端。
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