JP2016131238A - 原子スケールのald(原子層堆積)プロセスとale(原子層エッチング)プロセスとの統合 - Google Patents
原子スケールのald(原子層堆積)プロセスとale(原子層エッチング)プロセスとの統合 Download PDFInfo
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- JP2016131238A JP2016131238A JP2016002141A JP2016002141A JP2016131238A JP 2016131238 A JP2016131238 A JP 2016131238A JP 2016002141 A JP2016002141 A JP 2016002141A JP 2016002141 A JP2016002141 A JP 2016002141A JP 2016131238 A JP2016131238 A JP 2016131238A
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Abstract
【選択図】 図1C
Description
次に、特定の実施形態における原子層エッチング(ALE)動作及び原子層堆積(ALD)動作に適しているだろう誘導結合プラズマ(ICP)リアクタが説明される。このようなICPリアクタは、あらゆる目的のために参照によって全体を本明細書に組み込まれた、2013年10月12日に出願され発明の名称を「IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING(複数パターン形成のためのAHMギャップ充填を伴う像反転)」とする米国特許出願公開第2014/0170853号でも説明されている。本明細書では、ICPリアクタが説明されているが、実施形態によっては、容量結合プラズマリアクタが使用されてもよいことが理解されるべきである。
実験1:
開示される実施形態にしたがって、実験が行われた。非晶質シリコン基板が提供された。基板は、パターン形成されたマスクも含んでいた。基板は、カリフォルニア州フリーモントのLam Research Corp.から入手可能なKiyo(商標)リアクタに入れられた。基板は、特徴をエッチングするために、50サイクルのALEを施された。これらのALEサイクル後、基板は、次いで、5nmのSiO2を形成するために、真空を破壊することなく同じKiyoリアクタ内で、前駆体としてSiCl4を及び第2の反応剤としてO2を使用して、50サイクルのALDを施された。なお、5nmのSiO2が堆積されたのは、基板の画像に明白に結果を示すためである。
以上の実施形態は、理解を明瞭にする目的で幾分詳細に説明されてきたが、添付の特許請求の範囲内で特定の変更及び修正が加えられてよいことが明らかである。着目すべきは、これらの実施形態のプロセス、システム、及び装置を実現する代替のやり方が、多数存在することである。したがって、これらの実施形態は、例示的なものであって限定的ではないと見なされ、本明細書で与えられる詳細に限定されない。
Claims (30)
- 基板を処理する方法であって、
チャンバ内で、原子層エッチングによって前記基板をエッチングすることと、
前記チャンバ内で、原子層堆積によって膜を堆積させることと、
を備え、前記エッチング及び前記堆積は、真空を破壊することなく実施される、方法。 - 請求項1に記載の方法であって、
前記エッチングは、サイクル単位で実施され、1サイクルは、
基板を、前記基板の表面を改質するためにエッチングガスに暴露することと、
前記改質された表面の少なくとも一部を除去するために、前記基板を除去ガスに暴露することと、
を含む、方法。 - 請求項1に記載の方法であって、
前記堆積は、サイクル単位で実施され、1サイクルは、
前記基板を、前記基板の表面を改質するために堆積前駆体に暴露することと、
前記膜を堆積させるために、前記基板を還元剤に暴露することと、
を含む、方法。 - 請求項2に記載の方法であって、
前記基板をエッチングガスに暴露することは、更に、プラズマを点火することを含む、方法。 - 請求項2に記載の方法であって、更に、
前記基板にバイアスを印可することを備える方法。 - 請求項3に記載の方法であって、更に、
プラズマを点火することを備える方法。 - 請求項2に記載の方法であって、
前記エッチングガスは、塩素含有化合物である、方法。 - 請求項1に記載の方法であって、
前記エッチングは、非共形的に実施される、方法。 - 請求項2に記載の方法であって、
1サイクルは、約1Åから約50Åの膜をエッチングする、方法。 - 請求項3に記載の方法であって、
前記堆積前駆体の少なくとも一部は、前記基板を前記堆積前駆体に暴露している最中に前記基板の表面に吸着する、方法。 - 請求項2又は3のいずれか一項に記載の方法であって、
前記チャンバは、暴露と暴露との間にパージされる、方法。 - 請求項1ないし11のいずれか一項に記載の方法であって、
前記エッチング及び前記堆積は、同じチャンバ内で実施される、方法。 - 請求項1ないし11のいずれか一項に記載の方法であって、
前記エッチング又は前記堆積のいずれか一方は、自己制限的な反応である、方法。 - 請求項1ないし11のいずれか一項に記載の方法であって、
前記エッチング及び前記堆積は、前記基板上に材料を堆積させるために実施される、方法。 - 請求項1ないし11のいずれか一項に記載の方法であって、
前記エッチング及び前記堆積は、前記基板上の材料をエッチングするために実施される、方法。 - 請求項1ないし11のいずれか一項に記載の方法であって、
前記エッチングは、更に、前記基板を指向的にスパッタリングすることを含む、方法。 - 方法であって、
(a)チャンバに収容された基板を、前記基板を一層ずつエッチングするためにエッチングガス及び除去ガスの交互パルスに暴露することと、
(b)前記基板上に膜を堆積させるために、前記基板を第1の反応剤及び第2の反応剤の交互パルスに暴露することと、
(c)同じチャンバ内で(a)及び(b)を繰り返すことと、
を備える方法。 - 請求項17に記載の方法であって、
(a)は、更に、前記基板にバイアスを印可することを含む、方法。 - 請求項17に記載の方法であって、
(a)は、更に、前記基板を指向的にスパッタリングすることを含む、方法。 - 請求項17に記載の方法であって、更に、
前記基板を前記除去ガスに暴露するときにプラズマを点火することを備える方法。 - 請求項17に記載の方法であって、更に、
前記基板を前記第2の反応剤に暴露するときにプラズマを点火することを備える方法。 - 請求項17ないし21のいずれか一項に記載の方法であって、
前記除去ガスは、N2、Ar、He、及びNeからなる群より選択されるキャリアガスである、方法。 - 請求項17ないし21のいずれか一項に記載の方法であって、
(a)及び(b)は、同じチャンバ内で実施され、順次実施される、方法。 - 請求項17ないし21のいずれか一項に記載の方法であって、
前記チャンバは、パルスとパルスとの間でパージされる、方法。 - 請求項17ないし21のいずれか一項に記載の方法であって、
(a)又は(b)の少なくとも1つは、自己制限的な反応である、方法。 - 請求項17ないし21のいずれか一項に記載の方法であって、
(a)及び(b)は、前記基板上に膜を堆積させるために繰り返される、方法。 - 請求項17ないし21のいずれか一項に記載の方法であって、
(a)及び(b)は、前記基板上の膜をエッチングするために繰り返される、方法。 - 請求項17ないし21のいずれか一項に記載の方法であって、
前記基板は、金属及び誘電体からなる群より選択される、方法。 - ;
基板を処理するための装置であって、
それぞれチャックを含む1つ以上のプロセスチャンバと、
前記プロセスチャンバへの1つ以上のガス入口、及び関連の流量制御ハードウェアと、
少なくとも1つのプロセッサ、及びメモリを有するコントローラであって、
前記少なくとも1つのプロセッサ、及び前記メモリは、通信可能方式で互いに接続され、
前記少なくとも1つのプロセッサは、少なくとも動作可能方式で前記流量制御ハードウェアに接続され、
前記メモリは、
チャンバ内で原子層エッチングによって前記基板をエッチングすることと、
前記チャンバ内で原子層堆積によって膜を堆積させることと、に関して、
前記流量制御ハードウェアを少なくとも制御するように前記少なくとも1つのプロセッサを制御するためのコンピュータ実行可能命令を格納し、前記エッチング及び前記堆積は、真空を破壊することなく実施される、
コントローラと、
を備える装置。 - 基板を処理するための装置であって、
それぞれチャックを含む1つ以上のプロセスチャンバと、
前記プロセスチャンバへの1つ以上のガス入口、及び関連の流量制御ハードウェアと、
少なくとも1つのプロセッサ、及びメモリを有するコントローラであって、
前記少なくとも1つのプロセッサ、及び前記メモリは、通信可能方式で互いに接続され、
前記少なくとも1つのプロセッサは、少なくとも動作可能方式で前記流量制御ハードウェアに接続され、
前記メモリは、
(a)基板を、前記基板を一層ずつエッチングするためにエッチャント及びパージガスの交互パルスに暴露することと、
(b)前記エッチングされた基板上に膜を堆積させるために、還元剤及び前駆体の交互パルスに前記基板を暴露することと、
(c)(a)及び(b)を、(a)の実施と(b)の実施の間に真空を破壊することなく繰り返すことと、に関して、
前記流量制御ハードウェアを少なくとも制御するように前記少なくとも1つのプロセッサを制御するためのコンピュータ実行可能命令を格納する、コントローラと、
を備える装置。
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US14/696,254 US9576811B2 (en) | 2015-01-12 | 2015-04-24 | Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch) |
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Publication number | Publication date |
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CN108807128B (zh) | 2020-11-24 |
SG10201600099VA (en) | 2016-08-30 |
US20190139778A1 (en) | 2019-05-09 |
US9576811B2 (en) | 2017-02-21 |
TW201641731A (zh) | 2016-12-01 |
US20170117159A1 (en) | 2017-04-27 |
CN105789027A (zh) | 2016-07-20 |
KR102570795B1 (ko) | 2023-08-24 |
CN112530789A (zh) | 2021-03-19 |
TWI694166B (zh) | 2020-05-21 |
KR20160087348A (ko) | 2016-07-21 |
US9805941B2 (en) | 2017-10-31 |
US20200161139A1 (en) | 2020-05-21 |
JP6935985B2 (ja) | 2021-09-15 |
US20160203995A1 (en) | 2016-07-14 |
US20180033635A1 (en) | 2018-02-01 |
US10515816B2 (en) | 2019-12-24 |
CN108807128A (zh) | 2018-11-13 |
US10186426B2 (en) | 2019-01-22 |
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