JP2021504974A - 粗さを低減するための原子層堆積及びエッチング - Google Patents
粗さを低減するための原子層堆積及びエッチング Download PDFInfo
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- JP2021504974A JP2021504974A JP2020545228A JP2020545228A JP2021504974A JP 2021504974 A JP2021504974 A JP 2021504974A JP 2020545228 A JP2020545228 A JP 2020545228A JP 2020545228 A JP2020545228 A JP 2020545228A JP 2021504974 A JP2021504974 A JP 2021504974A
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Classifications
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/3065—Plasma etching; Reactive-ion etching
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- C23C16/45536—Use of plasma, radiation or electromagnetic fields
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- C—CHEMISTRY; METALLURGY
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- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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Abstract
Description
本出願は、米国特許出願第15/820,110号、2017年11月21日出願、名称「ATOMIC LAYER DEPOSITION AND ETCH FOR REDUCING ROUGHNESS」に対する優先権の利益を主張するものであり、その全体が全ての目的で参照により本明細書に組み込まれる。
以下の説明では、多数の特定の詳細を示し、本実施形態に対する完全な理解を提供する。開示する実施形態は、これら特定の詳細の一部又は全てを伴わずに実行してよい。他の例では、周知の工程動作は、開示する実施形態を不必要に曖昧にしないように、詳細に説明していない。開示する実施形態は、特定の実施形態と共に説明するが、開示する実施形態を限定する意図ではないことは理解されよう。
フィーチャのサイズが縮小し、ピッチがより小さくなり、相補型金属酸化物半導体(CMOS)技術のスケールがより小さなノードになるにつれて、薄型共形堆積技法は、重要性を増し続けている。原子層堆積法(ALD)は、膜形成技法であり、ALDが単一薄型材料層を堆積するため、薄型共形膜の堆積にかなり適している。薄型共形膜の厚さは、膜形成化学反応自体の前に、基板表面上に吸着し得る1つ又は複数の前駆体反応物の量によって制限される(即ち、吸着制限層)。ALDによって形成される各層は、薄く、共形であり、得られる膜は、下にあるデバイス構造体及びフィーチャの形状に実質的に適合する。
パターニング方法は、所望のフィーチャを達成するため、多くの半導体製造工程で使用されている。フォトレジスト・パターニング等のマスクは、下にある層をパターニングし、1−Dフィーチャ(線、トレンチ等)及び2−Dフィーチャ(例えば、穴、正方形等)を含む所望のフィーチャを形成するように働く。しかし、マスクの縁部は、通常、まっすぐではなく、直線性からの偏差につながる。直線性からの偏差は、パターン・フィーチャ内に非直線性の生成をもたらし、デバイスの性能に悪影響を与えることがある。そのような偏差は、ライン・ワイズ・ラフネス(LWR)及び/又はライン・エッジ・ラフネス(LER)として特徴付け得る。
本開示の実装形態は、原位置でのALD及びエッチングを使用して粗さを低減する方法に関する。いくつかの実装形態では、原位置でのALD動作及びエッチング動作は、LWR及び/又はLERが低減したフィーチャを形成するために、マスク上に共形層を堆積し、マスクの下にある層をエッチングすることによって実施してよい。いくつかの実装形態では、原位置でのALD動作及びエッチング動作は、側壁粗さが改善した高い縦横比のフィーチャを形成するために、1つ又は複数の構造体上に不活性化層を堆積し、1つ又は複数の構造体の下にある層をエッチングすることによって実施してよい。いくつかの実装形態では、ALDステップ及びエッチング・ステップのサイクルは、図1で説明したプラズマ処理装置内で実施される。エッチングと同じプラズマ処理装置内で実施されるALDのサイクルは、共形の堆積をもたらし、半導体デバイスのフィーチャ内の粗さの低減に使用される。
上記の実施形態は、理解を明快にする目的である程度詳細に説明してきたが、特定の変更及び修正を添付の特許請求の範囲内で行ってよいことは明らかであろう。本実施形態の方法、システム及び装置を実施する多くの代替様式があることに留意されたい。したがって、本実施形態は、限定的ではなく、例示的とみなすべきであり、実施形態は、本明細書で示す詳細に限定すべきではない。
Claims (26)
- 方法であって、
プラズマ室において、原子層堆積(ALD)によって基板のパターン・マスク層上に第1の共形層を堆積することであって、前記基板は、第1の材料層及び前記第1の材料層の上にある前記パターン・マスク層を含み、前記パターン・マスク層は、前記第1の共形層を堆積する前、第1の粗さを有する、堆積することと、
前記プラズマ室において、前記パターン・マスク層によって画定される前記第1の材料層の複数の第1のパターン・フィーチャを形成するため、前記第1の材料層をエッチングすることと
を含み、前記複数の第1のパターン・フィーチャは、前記第1の材料層をエッチングした後、前記パターン・マスク層の前記第1の粗さよりも小さい第2の粗さを有する、方法。 - 請求項1に記載の方法であって、前記第1の粗さは、第1のライン・エッジ・ラフネス(LER)及び第1のライン・ワイズ・ラフネス(LWR)に対応し、前記第2の粗さは、第2のLER及び第2のLWRに対応し、前記第2のLERは、約2.0nm以下であり、前記第2のLWRは、約2.0nm以下である、方法。
- 請求項1に記載の方法であって、前記第1の共形層の厚さは、約0.5nmから約5nmの間である、方法。
- 請求項1に記載の方法であって、
前記パターン・マスク層を形成するため、マスク層上でリソグラフィ動作及びエッチング動作を実施すること
を更に含む方法。 - 請求項1に記載の方法であって、前記パターン・マスク層は、フォトレジスト材料を含む、方法。
- 請求項1に記載の方法であって、前記パターン・マスク層は、ハード・マスク材料を含む、方法。
- 請求項1に記載の方法であって、前記パターン・マスク層は、前記第1の材料層からの1つ又は複数の1次元(1−D)フィーチャ及び前記第1の材料層からの1つ又は複数の2次元(2−D)フィーチャを画定するように構成され、前記1つ又は複数の1−Dフィーチャと前記1つ又は複数の2−Dフィーチャとの間の限界寸法(CD)バイアスは、前記第1の材料層をエッチングした後、実質的に同様である、方法。
- 請求項1に記載の方法であって、前記パターン・マスク層は、疎フィーチャ領域内の1つ又は複数の疎フィーチャ、及び前記疎フィーチャ領域よりも大きいフィーチャ密度を有する密フィーチャ領域内の1つ又は複数の密フィーチャを含み、前記1つ又は複数の疎フィーチャと前記1つ又は複数の密フィーチャとの間のCDバイアスは、前記第1の材料層をエッチングした後、実質的に同様である、方法。
- 請求項1〜8のいずれか一項に記載の方法であって、前記基板は、前記第1の材料層の下にある第2の材料層を更に含み、前記方法は、
前記プラズマ室において、ALDによって、前記複数の第1のパターン・フィーチャ、前記パターン・マスク層及び前記第2の材料層の露出表面上に第2の共形層を堆積することと、
前記プラズマ室において、前記複数の第1のパターン・フィーチャによって画定される複数の第2のパターン・フィーチャを形成するため、前記基板の前記第2の材料層をエッチングすることと
を更に含む、方法。 - 請求項9に記載の方法であって、前記複数の第2のパターン・フィーチャは、前記第1の粗さ及び前記第2の粗さのそれぞれよりも小さい第3の粗さを有する、方法。
- 請求項10に記載の方法であって、前記第3の粗さは、第3のLER及び第3のLWRに対応し、前記第3のLERは、約1.5nm以下であり、前記第3のLWRは、約1.5nm以下である、方法。
- 請求項1〜8のいずれか一項に記載の方法であって、前記複数の第1のパターン・フィーチャの限界寸法は、約20nm以下である、方法。
- 請求項1〜8のいずれか一項に記載の方法であって、前記第1の共形層は、シリコン酸化物(SiOx)を含む、方法。
- 請求項1〜8のいずれか一項に記載の方法であって、ALDによる前記第1の共形層の堆積は、
(a)前記プラズマ室に、前記パターン・マスク層上に吸着する前駆体を導入することと、
(b)ある吸着制限量の前記第1の共形層を形成するため、プラズマにより前記前駆体を変換することと、
(c)所望の厚さの前記第1の共形層が前記パターン・マスク層上に堆積されるまで、前記前駆体を導入し、前記前駆体を変換する動作を繰り返すことと
を含む、方法。 - 方法であって、
プラズマ室において、第1の深さで複数のフィーチャを形成するため、基板の前記第1の深さまでエッチングすることと、
前記プラズマ室において、原子層堆積(ALD)によって前記複数のフィーチャの側壁上に第1の不活性化層を堆積することと、
前記プラズマ室において、前記複数のフィーチャを前記第1の深さよりも大きい第2の深さまでエッチングすることと
を含み、前記第1の不活性化層は、前記第2の深さまでエッチングした後、側壁粗さを実質的に低減させるように構成される、方法。 - 請求項15に記載の方法であって、前記側壁のLWR及びLER値の一方又は両方は、前記複数のフィーチャを前記第2の深さまでエッチングした後、約1.5nm以下である、方法。
- 請求項15に記載の方法であって、前記複数のフィーチャは、シャロー・トレンチ・アイソレーション(STI)フィーチャを含む、方法。
- 請求項15に記載の方法であって、前記複数のフィーチャのそれぞれの深さ対幅の縦横比は、10:1以上である、方法。
- 請求項15に記載の方法であって、前記複数のフィーチャの限界寸法は、約20nm以下である、方法。
- 請求項15に記載の方法であって、前記第1の深さ及び前記第2の深さのそれぞれは、約100nm以上である、方法。
- 請求項15〜20のいずれか一項に記載の方法であって、前記複数のフィーチャは、疎フィーチャ領域内の1つ又は複数の疎フィーチャ、及び前記疎フィーチャ領域よりも大きいフィーチャ密度を有する密フィーチャ領域内の1つ又は複数の密フィーチャを含み、前記複数のフィーチャの側壁に沿った前記第1の不活性化層の厚さは、前記疎フィーチャ領域及び前記密フィーチャ領域内で実質的に同様である、方法。
- 請求項15〜20のいずれか一項に記載の方法であって、前記複数のフィーチャは、複数の構造体によって画定され、1つ又は複数の第1の構造体は、第1の材料を含み、1つ又は複数の第2の構造体は、前記第1の材料とは異なる第2の材料を含み、前記複数のフィーチャの側壁に沿った前記第1の不活性化層の厚さは、前記1つ又は複数の第1の構造体及び前記1つ又は複数の第2の構造体で実質的に同様である、方法。
- 請求項15〜20のいずれか一項に記載の方法であって、前記複数のフィーチャは、複数の構造体によって画定され、前記構造体のそれぞれは、シリコン、ゲルマニウム又はそれらの組合せを含む、方法。
- 請求項15〜20のいずれか一項に記載の方法であって、
前記プラズマ室において、ALDによって前記複数のフィーチャの側壁上に第2の不活性化層を堆積することと、
前記プラズマ室において、前記複数のフィーチャを前記基板内の前記第2の深さよりも大きい第3の深さまでエッチングすることと
を更に含み、前記第2の不活性化層は、前記複数のフィーチャを前記第3の深さまでエッチングした後、側壁粗さを実質的に低減させるように構成される、方法。 - 請求項15から20のいずれか一項に記載の方法であって、前記プラズマ室において前記複数のフィーチャをALDによって堆積し、エッチングする動作は、前記動作の間に真空破壊を導入せずに実施される、方法。
- 請求項15〜20のいずれか一項に記載の方法であって、前記第1の不活性化層は、シリコン酸化物(SiOx)を含む、方法。
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US20190157066A1 (en) | 2019-05-23 |
US11170997B2 (en) | 2021-11-09 |
JP2023179679A (ja) | 2023-12-19 |
TW201933439A (zh) | 2019-08-16 |
KR20200079346A (ko) | 2020-07-02 |
WO2019103878A1 (en) | 2019-05-31 |
US10658174B2 (en) | 2020-05-19 |
CN111630638A (zh) | 2020-09-04 |
JP7399864B2 (ja) | 2023-12-18 |
US20200243326A1 (en) | 2020-07-30 |
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