US20130189845A1 - Conformal amorphous carbon for spacer and spacer protection applications - Google Patents

Conformal amorphous carbon for spacer and spacer protection applications Download PDF

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US20130189845A1
US20130189845A1 US13/354,129 US201213354129A US2013189845A1 US 20130189845 A1 US20130189845 A1 US 20130189845A1 US 201213354129 A US201213354129 A US 201213354129A US 2013189845 A1 US2013189845 A1 US 2013189845A1
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nitrogen
substrate
amorphous carbon
method
patterned features
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Sungjin Kim
Deenesh Padhi
Song Hyun Hong
Bok Hoen Kim
Derek R. Witty
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Applied Materials Inc
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Applied Materials Inc
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Abstract

A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to a method for protecting sidewalls of hard mask spacers during an etching process.
  • 2. Description of the Related Art
  • Reducing the size of integrated circuits (ICs) results in improved performance, increased capacity and/or reduced cost. Each size reduction requires more sophisticated techniques to form the ICs. Photolithography is commonly used to pattern ICs on a substrate. An exemplary feature of an IC is a line of a material which may be a metal, semiconductor or insulator. Linewidth is the width of the line and the spacing is the distance between adjacent lines. Pitch is defined as the distance between a same point on two neighboring lines. The pitch is equal to the sum of the linewidth and the spacing. Due to factors such as optics and light or radiation wavelength, however, photolithography techniques have a minimum pitch below which a particular photolithographic technique may not reliably form features. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction.
  • Self-aligned double patterning (SADP) is one method for extending the capabilities of photolithographic techniques beyond the minimum pitch. Such a method is illustrated in FIGS. 1A-1F. With reference to FIG. 1A, patterned core features 102 are formed from sacrificial structural material above a dielectric layer 114 on a substrate 100 using standard photo-lithography and etching techniques. The patterned features are often referred to as placeholders or cores and have linewidths and/or spacings near the optical resolution of a photolithography system using a high-resolution photomask. As shown in FIG. 1B, a conformal layer 106 of hard mask material such as silicon oxide is subsequently deposited over core features 102. Hard mask spacers 108 are then formed on the sides of core features 102 by preferentially etching the hard mask material from the horizontal surfaces with an anisotropic plasma etch to open the hard mask material deposited on top of the patterned core features 102 as well as remove the hard mask material deposited at the bottom between the two sidewalls, as shown in FIG. 1C. The patterned core features 102 may then be removed, leaving behind hard mask spacers 108 (FIG. 1D). At this point hard mask spacers 108 may be used as an etch mask for transferring the pattern to the dielectric layer 114 to form dielectric ribs 116, as shown in FIG. 1E. The hard mask spacers 108 are subsequently removed (FIG. 1F). Therefore, the density of the dielectric ribs 116 is twice that of the photo-lithographically patterned core features 102, and the pitch of the dielectric ribs 116 is half the pitch of the patterned core features 102.
  • Currently, hard mask spacers 108 are formed by an atomic layer deposition (ALD) using an etchable material such as silicon oxides. These oxides are typically deposited at very low temperature (e.g., less than 200° C.). As a result, the material quality is poor, with low density and poor mechanical strength and degraded chemical resistance to subsequent etching chemistries. During the etching of the hard mask material, the spacer sidewalls, e.g., sidewalls 107 (FIG. 1D) are exposed to the plasma. Due to the poor material quality of typical ALD hard mask spacers, the sidewalls are damaged and thus causing higher line edge roughness. This issue becomes serious with shrinking feature size.
  • Therefore, there is a need for a method of protecting the sidewalls of the hard mask spacers such that the patterning integrity is greatly improved.
  • SUMMARY OF THE INVENTION
  • Embodiments of the present invention provide a method for protecting sidewalls of hard mask spacers during an etching process. In one embodiment, a method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.
  • In another embodiment, a method of forming a device in a processing chamber is provided. The method generally includes forming patterned features on an upper surface of a substrate, depositing conformally a predetermined thickness of a sacrificial dielectric layer on the patterned features and an exposed upper surface of the substrate, selectively removing the sacrificial dielectric layer from an upper surface of the patterned features and the exposed upper surface of the substrate to provide the patterned features filled within first sidewall spacers formed from the sacrificial dielectric layer, forming second sidewall spacers adjacent to the first sidewall spacers, the second sidewall spacers being formed from a nitrogen-doped amorphous carbon material having a carbon:nitrogen ratio of between about 0.1% nitrogen to about 4.0% nitrogen, and removing the patterned features filled within the first sidewall spacers.
  • In yet another embodiment, a method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing conformally a nitrogen-doped amorphous carbon layer on patterned features formed on the substrate, wherein the deposition is performed, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and an upper surface of the substrate using an anisotropic etching process to provide patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
  • FIGS. 1A-1F illustrate cross-sectional views representing a conventional double patterning process.
  • FIG. 2 is a flowchart depicting steps associated with an exemplary patterning process according to one embodiment of the invention.
  • FIGS. 3A-3E illustrate cross-sectional views of a structure formed by the steps set forth in FIG. 2.
  • FIG. 4 is a flowchart depicting steps associated with an exemplary patterning process according to another embodiment of the invention.
  • FIGS. 5A-5H illustrate cross-sectional views of a structure formed by the steps set forth in FIG. 4.
  • DETAILED DESCRIPTION
  • Embodiments of the present invention relate to an ultra-conformal strippable spacer process. In various embodiments, an ultra-conformal carbon-based material, such as amorphous carbon, is deposited over features of sacrificial structure material patterned using a high-resolution photomask. The ultra-conformal carbon-based material serves as a protective layer during an ashing or etching process, leaving the sacrificial structure material with an upper surface exposed and sidewalls protected by the carbon-based spacers. Upon removal of the sacrificial structure material, the remaining carbon-based spacers may perform as a hardmask layer for etching the underlying layer or structure. In one example, the carbon-based material may be an undoped or a nitrogen-doped amorphous carbon material.
  • Embodiments of the present invention may be performed using any suitable processing chamber such as a plasma enhanced chemical vapor deposition (PECVD) chamber. The processing chamber may be incorporated into a substrate processing system. An exemplary substrate processing system that may be used to practice the invention is described in commonly assigned U.S. Pat. No. 6,364,954 issued on Apr. 2, 2002, to Salvador et. al. and is herein incorporated by reference. Examples of suitable systems include the CENTURA® systems which may use a DxZ™ processing chamber, PRECISION 5000® systems, PRODUCER™ systems, PRODUCER GT™ and the PRODUCER SE™ processing chambers which are commercially available from Applied Materials, Inc., Santa Clara, Calif. It is contemplated that other processing system, including those available from other manufacturers, may be adapted to practice the embodiments described herein.
  • Exemplary Fabrication Sequence Employing a-C Protective Layer
  • FIG. 2 is a process flowchart depicting steps associated with an exemplary self-aligned double patterning process according to one embodiment of the invention. FIGS. 3A-3E illustrate cross-sectional views of a structure formed by the steps set forth in FIG. 2. It is contemplated that the self-aligned double patterning process is chosen for illustration purpose. The concept of the invention is equally applicable to other processes, single or dual patterning scheme, such as via/hole shrink process, self-aligned triple patterning (SATP) process, or self-aligned quadruple patterning (SAQP) process, etc. that may require the use of protective spacers with variable line width and spacing or protective sacrificial layer as needed in various semiconductor processes such as NAND flash application, DRAM application, or CMOS application, etc. In addition, the number or sequence of steps illustrated in FIG. 2 is not intended to limiting as to the scope of the invention described herein, since one or more steps can be added, deleted and/or reordered without deviating from the basic scope of the invention described herein.
  • The process 200 starts at box 202 by forming a sacrificial structural layer 320 on a substrate 300. The sacrificial structural layer 320 may be a silicon-based material such as silicon oxide, silicon nitride, or polysilicon. Alternatively, the sacrificial structural layer 320 may be a carbon-based material such as amorphous carbons. In cases where a carbon-based sacrificial structural layer is desired, the sacrificial structural layer 320 may be a combination of amorphous carbon and hydrogen (hydrogenated amorphous carbon film). One exemplary amorphous carbon film may be a strippable Advanced Patterning Film™ (APF) material commercially available from Applied Materials, Inc. of Santa Clara, Calif. It is contemplated that the choice of materials used for the sacrificial structural layer 320 may vary depending upon the etching/ashing rate relative to the conformal protective layer to be formed thereon. While not shown, in certain embodiments where a carbon-based sacrificial structural layer is used, one or more anti-reflective coating layers may be deposited on the carbon-based sacrificial structural layer to control the reflection of light during a lithographic patterning process. Suitable anti-reflective coating layer may include silicon dioxide, silicon oxynitride, silicon nitride, or combinations thereof. One exemplary anti-reflective coating layer may be a DARC™ material commercially available from Applied Materials, Inc. of Santa Clara, Calif.
  • The substrate 300 may have a substantially planar surface 323 as shown. Alternatively, the substrate 300 may have patterned structures, a surface having trenches, holes, or vias formed therein. While the substrate 300 is illustrated as a single body, the substrate 300 may contain one or more materials used in forming semiconductor devices such as metal contacts, trench isolations, gates, bitlines, or any other interconnect features. In one embodiment, the substrate 300 may include one or more metal layers, one or more dielectric materials, semiconductor material, and combinations thereof utilized to fabricate semiconductor devices. For example, the substrate 300 may include an oxide material, a nitride material, a polysilicon material, or the like, depending upon application. In cases where a memory application is desired, the substrate 300 may include the silicon substrate material, an oxide material, and a nitride material, with or without polysilicon sandwiched in between.
  • In some embodiments, the substrate 300 may include a plurality of alternating oxide and nitride materials (i.e., oxide-nitride-oxide (ONO)), one or more oxide or nitride materials, polysilicon or amorphous silicon materials, oxides alternating with amorphous silicon, oxides alternating with polysilicon, undoped silicon alternating with doped silicon, undoped polysilicon alternating with doped polysilicon, or updoped amorphous silicon alternating with doped amorphous silicon deposited on a surface of the substrate (not shown). The substrate 300 may be a material or a layer stack comprising one or more of the following: crystalline silicon, silicon oxide, silicon oxynitride, silicon nitride, strained silicon, silicon germanium, tungsten, titanium nitride, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitrides, doped silicon, germanium, gallium arsenide, glass, sapphire, low k dielectrics, and combinations thereof.
  • At box 204, a resist layer 330, such as a photoresist material, is deposited on the sacrificial structural layer 320 as shown in FIG. 3A.
  • At box 206, patterned features 321 formed from the sacrificial structural layer 320 are produced on the substrate 300 using standard photo-lithography and etching techniques, as shown in FIG. 3B. The patterned features may be formed from any suitable material, for example oxides, such as silicon dioxide, silicon oxynitride, or nitrides such as silicon nitride. The patterned features are sometimes referred to as placeholders, mandrels or cores and have specific linewidths and/or spacings based upon the photoresist material used. The width of the patterned features 321 may be adjusted by subjecting the resist layer 330 to a trimming process. After the pattern has been transferred into the sacrificial structural layer 320, any residual photoresist and hard mask material (if used) are removed using a suitable photoresist stripping process.
  • At box 208, a carbon-based protective layer 340 is deposited conformally or substantially conformally on the patterned features 321 and the exposed surfaces of the substrate 300, as shown in FIG. 3C. The thickness of the carbon-based protective layer 340 may be between about 5 Å and about 200 Å. In one embodiment, the carbon-based protective layer is an amorphous carbon (a-C) layer. The amorphous carbon may be undoped or doped with nitrogen. In one example, the carbon-based protective layer 340 is a nitrogen-doped amorphous carbon layer. The nitrogen-doped amorphous carbon layer may be deposited by any suitable deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) process. In one embodiment, the nitrogen-doped amorphous carbon layer may be deposited by flowing, among others, a hydrocarbon source, a nitrogen-containing gas such as N2 or NH3, and a plasma-initiating gas in a PECVD chamber. In another embodiment, the nitrogen-doped amorphous carbon layer may be deposited by flowing, among others, a hydrocarbon source, such as a gas-phase hydrocarbon or a liquid-phase hydrocarbon that has been entrained in a carrier gas, a nitrogen-containing hydrocarbon source, and a plasma-initiating gas into a PECVD chamber. The hydrocarbon source may be a mixture of one or more hydrocarbon compounds. In some embodiments, the hydrocarbon source may not be required. Instead, a nitrogen-containing hydrocarbon source and a plasma-initiating gas are flowed into the PECVD chamber to form the nitrogen-doped amorphous carbon protective layer on the patterned features 321 and the exposed surfaces of the substrate 300.
  • The hydrocarbon compounds may be partially or completely doped derivatives of hydrocarbon compounds, including fluorine-, oxygen-, hydroxyl group-, and boron-containing derivatives of hydrocarbon compounds. Hydrocarbon compounds or derivatives thereof that may be included in the hydrocarbon source may be described by the formula CxHy, where x has a range of between 1 and 10 and y has a range of between 2 and 30. Suitable hydrocarbon compounds may include, but are not limited to, acetylene (C2H2), ethane (C2H6), propylene (C3H6), propyne (C3H4), propane (C3H8), butane (C4H10), butylene (C4H8), butyne (C4H6), vinylacetylene, phenylacetylene (C8H6), benzene, styrene, toluene, xylene, ethylbenzene, acetophenone, methyl benzoate, phenyl acetate, phenol, cresol, furan, alpha-terpinene, cymene, 1,1,3,3,-tetramethylbutylbenzene, t-butylether, t-butylethylene, methyl-methacrylate, and t-butylfurfurylether, compounds having the formula C3H2 and C5H4, monofluorobenzene, difluorobenzenes, tetrafluorobenzenes, hexafluorobenzene, and the like. Additional suitable hydrocarbons may include ethylene, pentene, butadiene, isoprene, pentadiene, hexadiene, monofluoroethylene, difluoroethylenes, trifluoroethylene, tetrafluoroethylene, monochloroethylene, dichloroethylenes, trichloroethylene, tetrachloroethylene, and the like.
  • Nitrogen containing hydrocarbon compounds or derivatives thereof that may be included in the nitrogen containing hydrocarbon source can be described by the formula CxHyNz, where x has a range of between 1 and 12, y has a range of between 2 and 20, and z has a range of between 1 and 10. Suitable nitrogen containing hydrocarbon compounds may include one or more of the following compounds methylamine, dimethylamine, trimethylamine (TMA), triethylamine, aniline, quinoline, pyridine, acrilonitrile, and benzonitrile.
  • In certain embodiments, the nitrogen doped amorphous carbon deposition process may include the use of a plasma-initiating gas that is introduced into the PECVD chamber at before and/or same time as the hydrocarbon compound and a plasma is initiated to begin deposition. The plasma-initiating gas may be a high ionization potential gas including, and not limited to, helium gas, hydrogen gas, nitrogen gas, argon gas and combinations thereof. The plasma-initiating gas may also be a chemically inert gas, such as helium gas, nitrogen gas, or argon gas. Suitable ionization potentials for gases are from about 5 eV (electron potential) to 25 eV. The plasma-initiating gas may be introduced into the PECVD chamber prior to the nitrogen containing hydrocarbon source and/or the hydrocarbon source, which allows a stable plasma to be formed and reduces the chances of arcing. An inert gas used as a diluent gas or a carrier gas, such as argon, may be introduced with the plasma-initiating gas, the nitrogen containing hydrocarbon source, the hydrocarbon source, or combinations thereof. Suitable dilution gases such as helium (He), hydrogen (H2), nitrogen (N2), ammonia (NH3), or combinations thereof, among others, may be added to the gas mixture, if desired. Ar, He, and N2 are used to control the density and deposition rate of the amorphous carbon layer. In some cases, the addition of H2 and/or NH3 can be used to control the hydrogen ratio of the amorphous carbon layer. Alternatively, dilution gases may not be used during the deposition.
  • In cases where the nitrogen-doped amorphous carbon is deposited using a hydrocarbon source and a nitrogen-containing gas, the nitrogen-containing gas may be introduced into the PECVD chamber at a nitrogen-containing gas to hydrocarbon source ratio of about 1:100 to about 10:1.
  • In various embodiments, the nitrogen doped amorphous carbon layer may be deposited at a chamber pressure of about 0.5 Torr or greater, such as from about 0.5 Torr to about 20 Torr, and in one embodiment, about 2 Torr or greater, for example, from about 2 Torr to about 12 Torr, and a substrate temperature from about 25° C. to about 800° C., such as at a temperature from about 200° C. to about 400° C. The electrode spacing between a showerhead and substrate surface when depositing the layer may be between 200 mils and 5,000 mils spacing, for example, about 500 mils spacing. In certain embodiments, where a plasma is used, the hydrocarbon source, the nitrogen doped amorphous carbon source, and the plasma-initiating gas are introduced into the PECVD chamber and a plasma is initiated to begin the deposition.
  • Plasma may be generated by applying RF power at a power density to substrate surface area of from about 0.01 W/cm2 to about 5 W/cm2, such as from about 0.8 W/cm2 to about 2.3 W/cm2, for example, about 2 W/cm2. The power application may be from about 1 Watt to about 2,000 watts, such as from about 10 W to about 100 W, for a 300 mm substrate. It is noted that the RF power can be either single frequency or dual frequency. If a single frequency power is used, the frequency power may be between about 10 KHz and about 30 MHz. If a dual-frequency RF power is used to generate the plasma, a mixed RF power may be used. The mixed RF power may provide a high frequency power in a range from about 10 MHz to about 30 MHz, for example, about 13.56 MHz, as well as a low frequency power in a range of from about 10 KHz to about 1 MHz, for example, about 350 KHz. A dual frequency RF power application is believed to provide independent control of flux and ion energy since the energy of the ions hitting the film surface influences the film density. The applied RF power and use of one or more frequencies may be varied based upon the substrate size and the equipment used. In certain embodiments, a single frequency RF power application may be used, and is typically, an application of the high frequency power as described herein.
  • An exemplary deposition process for processing 300 mm circular substrates may employ, among others, a plasma-initiating gas, a nitrogen containing hydrocarbon source, and a dilution gas. The deposition process may include supplying a plasma-initiating gas, such as helium and/or argon, at a flow rate from about 0 sccm to about 50,000 sccm, for example, between about 400 sccm to about 8,000 sccm, supplying a nitrogen containing hydrocarbon source, at a flow rate from about 10 sccm to about 2,000 sccm, for example, from about 500 sccm to about 1,500 sccm. In case the nitrogen containing hydrocarbon source is a liquid precursor, then the nitrogen containing hydrocarbon source flow can be between 15 mg/min and 2,000 mg/min, for example between 100 mg/min and 1,000 mg/min. A dilution gas, such as NH3, He, Ar, H2, or N2, may be supplied at a flow rate from about 0 sccm to about 5,000 sccm, for example about 500 sccm to about 1,000 sccm. The deposition process may be performed with a dual frequency RF power from about 5 W to about 1,600 W, for example between about 10 W and about 100 W, at a chamber pressure from about 0.5 Torr to about 50 Torr, for example between about 5 torr and about 15 Torr, and a substrate temperature from about 25° C. to about 650° C., for example between about 200° C. and about 400° C. This process range provides a deposition rate for a nitrogen doped amorphous carbon layer in the range of about 10 Å/min to about 30,000 Å/min. One skilled in the art, upon reading the disclosure herein, can calculate appropriate process parameters in order to produce a nitrogen doped amorphous carbon film of different deposition rates. The as-deposited nitrogen-doped amorphous carbon layer has an adjustable carbon:nitrogen ratio that ranges from about 0.1% nitrogen to about 4.0% nitrogen, such as about 1.5% to about 2%. An example of nitrogen doped amorphous carbon materials deposited by the processes described herein is provided as follows.
  • A nitrogen doped amorphous carbon deposition process may include providing a flow rate of helium to the processing chamber at about 200 sccm to 1,500 sccm, for example about 500 sccm, providing a flow rate of benzonitrile to the processing chamber at about 100 mg/min to about 1,000 mg/min, and providing a flow rate of ammonia to the processing chamber at about 0 sccm to about 2,000 sccm, applying a high frequency RF power (13.56 MHz) at about 30 W to 200 W (for a 200 mm wafer), maintaining a deposition temperature of about 200° C. to about 550° C., maintaining a chamber pressure of about 2 Torr to 15 Torr, with a spacing of about 100 mils to about 800 mils to produce a nitrogen doped amorphous carbon layer having a thickness of about 10 Å to about 1,000 Å.
  • Referring back to FIG. 2, at box 210, after the carbon-based protective layer 340 has been deposited conformally on the patterned features 321, the carbon-based protective layer 340 is anisotropically etched (a vertical etch) to expose an upper surface of the substrate 300 in areas 311 and expose an upper surface of patterned features 321, resulting in patterned features 321 (formed from the sacrificial structural layer 320) protected by carbon-based sidewall spacers 341, as shown in FIG. 3D.
  • At box 212, the patterned features 321 (formed from the sacrificial structural layer 320) are removed using a conventional plasma etching process or other suitable wet stripping process, leaving non-sacrificial carbon-based sidewall spacers 341 as shown in FIG. 3E. The plasma etching process may be done by introducing a fluorine-based etching chemistry into a plasma above the substrate. Due to the improved material quality and coverage, the carbon-based sidewall spacers 341 are not damaged because they have very good selectivity to the fluorine-based reactive etching chemistry or the wet strip-based chemistry. Upon removal of the patterned features 321, the remaining carbon-based sidewall spacers 341 may be used as a hardmask for etching the underlying layer, layer stack, or structure. Particularly, the density of the carbon-based sidewall spacers 341 in accordance with this patterning process is twice that of the photo-lithographically patterned features 321, the pitch of carbon-based sidewall spacer 341 is half the pitch of the patterned features 321.
  • FIG. 4 is a flowchart depicting steps associated with an exemplary patterning process according to another embodiment of the invention. FIGS. 5A-5H illustrate cross-sectional views of a structure formed by the steps set forth in FIG. 4. It is noted that the concept of this embodiment is equally applicable to other processes, single or dual patterning scheme, such as via/hole shrink process, back end of line (BEOL) self-aligned double patterning (SADP) process, or self-aligned quadruple patterning (SAQP) process, etc. that may require the use of protective spacers with variable line width and spacing or protective sacrificial layer as needed in various semiconductor processes such as NAND flash application, DRAM application, or CMOS application, etc.
  • The process 400 starts at box 402 by providing a substrate 500 into a processing chamber, such as a PECVD chamber. The substrate 500 may be one or more materials used in forming semiconductor devices including a silicon material, an oxide material, a polysilicon material, or the like, as discussed above with respect to substrate 300 shown in FIG. 3A.
  • At box 404, a non-sacrificial structural layer 520 is deposited on the substrate 500 as shown in FIG. 5B. The non-sacrificial structural layer 520 may be a carbon-based material such as amorphous carbons. In one example, the non-sacrificial structural layer 520 is an Advanced Patterning Film™ (APF) material commercially available from Applied Materials, Inc. of Santa Clara, Calif. While not shown, in certain embodiments where a carbon-based non-sacrificial structural layer is used, one or more anti-reflective coating layers may be deposited on the carbon-based non-sacrificial structural layer to control the reflection of light during a lithographic patterning process. Suitable anti-reflective coating layer may include silicon dioxide, silicon oxynitride, silicon nitride, or combinations thereof. One exemplary anti-reflective coating layer may be a DARC™ material commercially available from Applied Materials, Inc. of Santa Clara, Calif.
  • At box 406, a bottom anti-reflective coating (BARC) layer 540 is deposited over the non-sacrificial structure layer 520. The BARC layer 540 may be an organic material such as polyamides and polysulfones. The BARC layer 540 is believed to reduce reflection of light during patterning of the subsequent resist layer and is also helpful for thinner resist layers because the BARC layer 540 increases the total thickness of the multi-layered mask for improved etch resistance during etch of underlying layer or structure. In certain embodiments, the BARC layer 540 may further include a light absorbing layer 530 deposited between the BARC layer 540 and the non-sacrificial structure layer 520 as shown in FIG. 5C, to improve photolithography performance. The light absorbing layer 530 may be a metal layer, such as nitrides. In one example, the light absorbing layer 530 is titanium nitride.
  • At box 408, a resist layer, such as a photoresist material, is then deposited on the BARC layer 540. The resist layer is then patterned by a lithographic process producing a patterned resist layer 550 with a desired etch pattern 551, as shown in FIG. 5D. The etch pattern 551 is shown to have different pattern width for exemplary purpose.
  • At box 410, the BARC layer 540, the light absorbing layer 530, and the non-sacrificial structure layer 520 are patterned respectively using conventional photolithography and etching processes to transfer the desired etch pattern 551 into the non-sacrificial structure layer 520, leaving patterned non-sacrificial features 521, as shown in FIG. 5E.
  • At box 412, a first conformal layer is deposited conformally or substantially conformally on the patterned non-sacrificial features 521 and the exposed surfaces of the substrate 500. The first conformal layer may comprise a strippable material having an etching rate different from the patterned sacrificial features 521. Suitable materials for the first conformal layer may include, for example, oxides such as silicon dioxide, silicon oxynitride, or nitride such as silicon nitride. The first conformal layer is then anisotropically etched to expose an upper surface of the substrate 500 in areas 511 and expose an upper surface of patterned non-sacrificial features 521, resulting in patterned non-sacrificial features 521 (formed from the non-sacrificial structural layer 520) protected by strippable sidewall spacers 561 formed from the first conformal layer, as shown in FIG. 5F.
  • At box 414, non-sacrificial carbon-based sidewall spacers 571 are then formed adjacent the patterned non-sacrificial features 521 in a manner similar to the sidewall spacers 561 as shown in FIG. 5G. The non-sacrificial carbon-based sidewall spacers 571 may be an amorphous carbon (a-C) undoped or doped with nitrogen formed by the processes as described above with respect to boxes 208 and 210. In one embodiment, the non-sacrificial carbon-based sidewall spacers 571 are nitrogen-doped amorphous carbon.
  • At box 416, the strippable sidewall spacers 561, located between the patterned non-sacrificial features 521 and the non-sacrificial carbon-based sidewall spacers 571, are removed using a conventional wet stripping process or other suitable process, leaving patterned non-sacrificial features 521 and non-sacrificial carbon-based sidewall spacers 571 as shown in FIG. 5H. The remaining patterned non-sacrificial features 521 and non-sacrificial carbon-based sidewall spacers 571 may then be used as a hardmask for etching the underlying layer, layer stack, or structure. Particularly, the density of the resulting hardmask (i.e., patterned non-sacrificial features 521 and non-sacrificial carbon-based sidewall spacers 571) in accordance with this patterning process is triple that of the patterned resist layer 550, the pitch of resulting hardmask (i.e., patterned non-sacrificial features 521 and non-sacrificial carbon-based sidewall spacers 571) is half the pitch of the patterned resist layer 550.
  • Carbon-based protective layers or sidewall spacers deposited in accordance with the present invention have been observed to be able to provide excellent conformality higher than 95% with an improved film uniformity of about 1.5%, high film density of about 1.25-1.60 g/cc, and a compressive film stress less than 50 MPa. Since the sidewalls of hard mask spacers are not damaged during the ashing or anisotropic plasma etching process, the line edge roughness is significantly reduced as compared to the conventional ALD grown spacers using silicon oxide materials. Therefore, the resulting hard mask spacers can provide superior etch profile and etch selectivity with little or no microloading.
  • While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (21)

1. A method of forming an amorphous carbon layer on a substrate in a processing chamber, comprising:
depositing a predetermined thickness of a sacrificial dielectric layer over a substrate;
forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate;
depositing conformally a predetermined thickness of an amorphous carbon layer on the patterned features and the exposed upper surface of the substrate;
selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the amorphous carbon layer; and
removing the patterned features from the substrate.
2. The method of claim 1, wherein the amorphous carbon layer is formed by introducing a hydrocarbon source, a nitrogen-containing gas, and a plasma initiating gas into the processing chamber.
3. The method of claim 2, wherein the hydrocarbon source comprises one or more hydrocarbon compounds having the general formula CxHy, wherein x has a range of between 1 and 20, and y has a range of between 1 and 20.
4. The method of claim 3, wherein one or more hydrocarbon compounds is selected from the group consisting of acetylene (C2H2), ethylene (C2H4), ethane (C2H6), propylene (C3H6), propyne (C3H4), propane (C3H8), butane (C4H10), butylene (C4H8), butadiene (C4H6), phenylacetylene (C8H6), and combinations thereof.
5. The method of claim 1, wherein the amorphous carbon layer is formed by introducing a nitrogen-containing hydrocarbon source and a plasma-initiating gas into the processing chamber.
6. The method of claim 5, wherein the nitrogen-containing hydrocarbon source is described by the formula CxHyNz, where x has a range of between 1 and 12, y has a range of between 2 and 20, and z has a range of between 1 and 10.
7. The method of claim 6, wherein the nitrogen-containing hydrocarbon source comprises one or more nitrogen containing hydrocarbon compounds selected from the group consisting of methylamine, dimethylamine, trimethylamine (TMA), triethylamine, aniline, quinoline, pyridine, acrilonitrile, benzonitrile, and combinations thereof.
8. The method of claim 1, wherein the amorphous carbon layer is a nitrogen-doped amorphous carbon having a carbon:nitrogen ratio of between about 0.1% nitrogen to about 4.0% nitrogen.
9. The method of claim 1, wherein the sacrificial dielectric layer comprises silicon oxide, silicon nitride, polysilicon, or amorphous carbon.
10. The method of claim 1, wherein the substrate comprises a plurality of alternating oxide and nitride materials, one or more oxide materials or nitride materials, polysilicon or amorphous silicon materials, oxides alternating with amorphous silicon, oxides alternating with polysilicon, undoped silicon alternating with doped silicon, undoped polysilicon alternating with doped polysilicon, or updoped amorphous silicon alternating with doped amorphous silicon.
11. A method of forming a device in a processing chamber, comprising:
forming patterned features on an upper surface of a substrate;
depositing conformally a predetermined thickness of a sacrificial dielectric layer on the patterned features and an exposed upper surface of the substrate;
selectively removing the sacrificial dielectric layer from an upper surface of the patterned features and the exposed upper surface of the substrate to provide the patterned features filled within first sidewall spacers formed from the sacrificial dielectric layer;
forming second sidewall spacers adjacent to the first sidewall spacers, the second sidewall spacers being formed from a nitrogen-doped amorphous carbon material having a carbon:nitrogen ratio of between about 0.1% nitrogen to about 4.0% nitrogen; and
removing the patterned features filled within the first sidewall spacers.
12. The method of claim 11, wherein the patterned features are formed from amorphous carbon.
13. The method of claim 11, wherein the sacrificial dielectric layer comprises silicon dioxide, silicon oxynitride, or silicon nitride.
14. The method of claim 11, wherein the nitrogen-doped amorphous carbon material is formed by introducing a nitrogen-containing hydrocarbon source and a plasma-initiating gas into the processing chamber.
15. The method of claim 14, wherein the nitrogen-containing hydrocarbon source is described by the formula CxHyNz, where x has a range of between 1 and 12, y has a range of between 2 and 20, and z has a range of between 1 and 10.
16. The method of claim 15, wherein the nitrogen-containing hydrocarbon source comprises one or more nitrogen containing hydrocarbon compounds selected from the group consisting of methylamine, dimethylamine, trimethylamine (TMA), triethylamine, aniline, quinoline, pyridine, acrilonitrile, benzonitrile, and combinations thereof.
17. The method of claim 11, wherein the substrate comprises a plurality of alternating oxide and nitride materials, one or more oxide materials or nitride materials, polysilicon or amorphous silicon materials, oxides alternating with amorphous silicon, oxides alternating with polysilicon, undoped silicon alternating with doped silicon, undoped polysilicon alternating with doped polysilicon, or updoped amorphous silicon alternating with doped amorphous silicon.
18. The method of claim 11, wherein the nitrogen-doped amorphous carbon material is formed by introducing a hydrocarbon source and a nitrogen-containing gas into the processing chamber.
19. The method of claim 18, wherein the hydrocarbon source comprises one or more hydrocarbon compounds having the general formula CxHy, wherein x has a range of between 1 and 20, and y has a range of between 1 and 20.
20. A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber, comprising:
depositing conformally a nitrogen-doped amorphous carbon layer on patterned features formed on the substrate, wherein the deposition is performed;
selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and an upper surface of the substrate using an anisotropic etching process to provide patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer; and
removing the patterned features from the substrate.
21. The method of claim 20, wherein the nitrogen-doped amorphous carbon layer is deposited by introducing into the processing chamber a nitrogen-containing hydrocarbon source at a flow rate of about 100 ring/min to about 1,000 mg/min, a nitrogen-containing gas at a flow rate of 0 sccm to about 2,000 sccm, by applying an RF power of about 30 W to about 200 W (for a 200 mm substrate), and at an electrode spacing of about 100 mils to about 800 mils.
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130034963A1 (en) * 2011-08-02 2013-02-07 Chung Byung-Hong Methods of forming fine patterns for semiconductor device
US20130157468A1 (en) * 2010-08-27 2013-06-20 Tokyo Electron Limited Etching method, substrate processing method, pattern forming method, method for manufacturing semiconductor element, and semiconductor element
US20140083972A1 (en) * 2012-09-27 2014-03-27 Tokyo Electron Limited Pattern forming method
US8828839B2 (en) * 2013-01-29 2014-09-09 GlobalFoundries, Inc. Methods for fabricating electrically-isolated finFET semiconductor devices
US20140315380A1 (en) * 2013-04-19 2014-10-23 International Business Machines Corporation Trench patterning with block first sidewall image transfer
US20150061087A1 (en) * 2013-09-04 2015-03-05 Semiconductor Manufacturing International (Shanghai) Corporation Triple patterning method
US20160027658A1 (en) * 2013-10-25 2016-01-28 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography using Multilayer Spacer for Reduced Spacer Footing
WO2016200498A1 (en) * 2015-06-11 2016-12-15 Applied Materials, Inc. Conformal strippable carbon film for line-edge-roughness reduction for advanced patterning
US9698015B2 (en) 2013-10-21 2017-07-04 Applied Materials, Inc. Method for patterning a semiconductor substrate
US9721784B2 (en) 2013-03-15 2017-08-01 Applied Materials, Inc. Ultra-conformal carbon film deposition
US9935012B1 (en) 2016-11-28 2018-04-03 Globalfoundries Inc. Methods for forming different shapes in different regions of the same layer
US10074543B2 (en) 2016-08-31 2018-09-11 Lam Research Corporation High dry etch rate materials for semiconductor patterning applications
US10134579B2 (en) 2016-11-14 2018-11-20 Lam Research Corporation Method for high modulus ALD SiO2 spacer
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI555082B (en) * 2015-05-15 2016-10-21 Powerchip Technology Corp Patterning method
WO2018052760A1 (en) 2016-09-13 2018-03-22 Applied Materials, Inc. Borane mediated dehydrogenation process from silane and alkylsilane species for spacer and hardmask application
US10276379B2 (en) * 2017-04-07 2019-04-30 Applied Materials, Inc. Treatment approach to improve film roughness by improving nucleation/adhesion of silicon oxide

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3751651T2 (en) * 1986-10-14 1996-10-17 Minolta Camera Kk An electrophotographic light-sensitive element containing a coating
JPH07131009A (en) * 1993-11-04 1995-05-19 Toshiba Corp Semiconductor device and preparation thereof
JPH07161657A (en) * 1993-12-08 1995-06-23 Fujitsu Ltd Formation of pattern
US6596599B1 (en) * 2001-07-16 2003-07-22 Taiwan Semiconductor Manufacturing Company Gate stack for high performance sub-micron CMOS devices
US6500756B1 (en) * 2002-06-28 2002-12-31 Advanced Micro Devices, Inc. Method of forming sub-lithographic spaces between polysilicon lines
US6893967B1 (en) * 2004-01-13 2005-05-17 Advanced Micro Devices, Inc. L-shaped spacer incorporating or patterned using amorphous carbon or CVD organic materials
US7390746B2 (en) * 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US8852851B2 (en) * 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7560784B2 (en) * 2007-02-01 2009-07-14 International Business Machines Corporation Fin PIN diode
KR20100039847A (en) 2007-06-15 2010-04-16 어플라이드 머티어리얼스, 인코포레이티드 Oxygen sacvd to form sacrificial oxide liners in substrate gaps
KR100955265B1 (en) * 2007-08-31 2010-04-30 주식회사 하이닉스반도체 Method for forming micropattern in semiconductor device
JP2009130035A (en) * 2007-11-21 2009-06-11 Toshiba Corp Method of manufacturing semiconductor device
US20090311634A1 (en) * 2008-06-11 2009-12-17 Tokyo Electron Limited Method of double patterning using sacrificial structure
US7709396B2 (en) * 2008-09-19 2010-05-04 Applied Materials, Inc. Integral patterning of large features along with array using spacer mask patterning process flow
JP2012506151A (en) * 2008-10-14 2012-03-08 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Method for depositing conformal amorphous carbon films by plasma enhanced chemical vapor deposition (PECVD)
US8084310B2 (en) 2008-10-23 2011-12-27 Applied Materials, Inc. Self-aligned multi-patterning for advanced critical dimension contacts
US7935464B2 (en) 2008-10-30 2011-05-03 Applied Materials, Inc. System and method for self-aligned dual patterning
US7972959B2 (en) 2008-12-01 2011-07-05 Applied Materials, Inc. Self aligned double patterning flow with non-sacrificial features
US7842622B1 (en) 2009-05-15 2010-11-30 Asm Japan K.K. Method of forming highly conformal amorphous carbon layer
JP5356516B2 (en) * 2009-05-20 2013-12-04 株式会社東芝 Concave and convex pattern forming method
US8404592B2 (en) * 2009-07-27 2013-03-26 GlobalFoundries, Inc. Methods for fabricating FinFET semiconductor devices using L-shaped spacers
US8242560B2 (en) * 2010-01-15 2012-08-14 International Business Machines Corporation FinFET with thin gate dielectric layer
US20110244142A1 (en) * 2010-03-30 2011-10-06 Applied Materials, Inc. Nitrogen doped amorphous carbon hardmask
JP4982582B2 (en) * 2010-03-31 2012-07-25 株式会社東芝 Mask manufacturing method
US20130109198A1 (en) * 2011-10-26 2013-05-02 American Air Liquide, Inc. High carbon content molecules for amorphous carbon deposition

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130157468A1 (en) * 2010-08-27 2013-06-20 Tokyo Electron Limited Etching method, substrate processing method, pattern forming method, method for manufacturing semiconductor element, and semiconductor element
US9117764B2 (en) * 2010-08-27 2015-08-25 Tokyo Electron Limited Etching method, substrate processing method, pattern forming method, method for manufacturing semiconductor element, and semiconductor element
US20130034963A1 (en) * 2011-08-02 2013-02-07 Chung Byung-Hong Methods of forming fine patterns for semiconductor device
US8889560B2 (en) * 2011-08-02 2014-11-18 Samsung Electronics Co., Ltd. Methods of forming fine patterns for semiconductor device
US20140083972A1 (en) * 2012-09-27 2014-03-27 Tokyo Electron Limited Pattern forming method
US8828839B2 (en) * 2013-01-29 2014-09-09 GlobalFoundries, Inc. Methods for fabricating electrically-isolated finFET semiconductor devices
US10074534B2 (en) 2013-03-15 2018-09-11 Applied Materials, Inc. Ultra-conformal carbon film deposition
US9721784B2 (en) 2013-03-15 2017-08-01 Applied Materials, Inc. Ultra-conformal carbon film deposition
US20140315380A1 (en) * 2013-04-19 2014-10-23 International Business Machines Corporation Trench patterning with block first sidewall image transfer
US9064813B2 (en) * 2013-04-19 2015-06-23 International Business Machines Corporation Trench patterning with block first sidewall image transfer
US9034762B2 (en) * 2013-09-04 2015-05-19 Semiconductor Manufacturing International (Shanghai) Corporation Triple patterning method
US20150061087A1 (en) * 2013-09-04 2015-03-05 Semiconductor Manufacturing International (Shanghai) Corporation Triple patterning method
US9698015B2 (en) 2013-10-21 2017-07-04 Applied Materials, Inc. Method for patterning a semiconductor substrate
US20160027658A1 (en) * 2013-10-25 2016-01-28 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography using Multilayer Spacer for Reduced Spacer Footing
US9892933B2 (en) * 2013-10-25 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography using multilayer spacer for reduced spacer footing
WO2016200498A1 (en) * 2015-06-11 2016-12-15 Applied Materials, Inc. Conformal strippable carbon film for line-edge-roughness reduction for advanced patterning
US9659771B2 (en) 2015-06-11 2017-05-23 Applied Materials, Inc. Conformal strippable carbon film for line-edge-roughness reduction for advanced patterning
US10014174B2 (en) 2015-06-11 2018-07-03 Applied Materials, Inc. Conformal strippable carbon film for line-edge-roughness reduction for advanced patterning
US10074543B2 (en) 2016-08-31 2018-09-11 Lam Research Corporation High dry etch rate materials for semiconductor patterning applications
US10134579B2 (en) 2016-11-14 2018-11-20 Lam Research Corporation Method for high modulus ALD SiO2 spacer
US9935012B1 (en) 2016-11-28 2018-04-03 Globalfoundries Inc. Methods for forming different shapes in different regions of the same layer
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer

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US20170170015A1 (en) 2017-06-15
WO2013109645A1 (en) 2013-07-25
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KR20140115353A (en) 2014-09-30

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