DE3854421D1 - Dynamische Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür. - Google Patents

Dynamische Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür.

Info

Publication number
DE3854421D1
DE3854421D1 DE3854421T DE3854421T DE3854421D1 DE 3854421 D1 DE3854421 D1 DE 3854421D1 DE 3854421 T DE3854421 T DE 3854421T DE 3854421 T DE3854421 T DE 3854421T DE 3854421 D1 DE3854421 D1 DE 3854421D1
Authority
DE
Germany
Prior art keywords
manufacturing
random access
access memory
memory array
dynamic random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3854421T
Other languages
English (en)
Other versions
DE3854421T2 (de
Inventor
Taiji Ema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62296669A external-priority patent/JP2772375B2/ja
Priority claimed from JP62302464A external-priority patent/JPH07118520B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3854421D1 publication Critical patent/DE3854421D1/de
Publication of DE3854421T2 publication Critical patent/DE3854421T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
DE3854421T 1987-11-25 1988-11-24 Dynamische Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür. Expired - Lifetime DE3854421T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62296669A JP2772375B2 (ja) 1987-11-25 1987-11-25 半導体記憶装置
JP62302464A JPH07118520B2 (ja) 1987-11-30 1987-11-30 半導体記憶装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE3854421D1 true DE3854421D1 (de) 1995-10-12
DE3854421T2 DE3854421T2 (de) 1996-02-15

Family

ID=26560793

Family Applications (2)

Application Number Title Priority Date Filing Date
DE3854421T Expired - Lifetime DE3854421T2 (de) 1987-11-25 1988-11-24 Dynamische Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür.
DE3856543T Expired - Lifetime DE3856543T2 (de) 1987-11-25 1988-11-24 Dynamische Spreicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE3856543T Expired - Lifetime DE3856543T2 (de) 1987-11-25 1988-11-24 Dynamische Spreicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür

Country Status (4)

Country Link
US (5) US4953126A (de)
EP (2) EP0661752B1 (de)
KR (1) KR910009805B1 (de)
DE (2) DE3854421T2 (de)

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JP2746730B2 (ja) * 1990-05-17 1998-05-06 富士通株式会社 半導体記憶装置
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Also Published As

Publication number Publication date
DE3856543D1 (de) 2002-11-28
DE3856543T2 (de) 2003-03-20
US6114721A (en) 2000-09-05
DE3854421T2 (de) 1996-02-15
KR910009805B1 (ko) 1991-11-30
US5128273A (en) 1992-07-07
US6046468A (en) 2000-04-04
KR890008991A (ko) 1989-07-13
EP0318277A2 (de) 1989-05-31
EP0318277A3 (en) 1990-10-31
EP0661752A2 (de) 1995-07-05
US5572053A (en) 1996-11-05
EP0318277B1 (de) 1995-09-06
EP0661752B1 (de) 2002-10-23
EP0661752A3 (de) 1996-06-12
US4953126A (en) 1990-08-28

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