DE69132998D1 - Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür - Google Patents

Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür

Info

Publication number
DE69132998D1
DE69132998D1 DE69132998T DE69132998T DE69132998D1 DE 69132998 D1 DE69132998 D1 DE 69132998D1 DE 69132998 T DE69132998 T DE 69132998T DE 69132998 T DE69132998 T DE 69132998T DE 69132998 D1 DE69132998 D1 DE 69132998D1
Authority
DE
Germany
Prior art keywords
manufacturing
random access
access memory
memory array
method therefor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69132998T
Other languages
English (en)
Other versions
DE69132998T2 (de
Inventor
Takanori Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69132998D1 publication Critical patent/DE69132998D1/de
Publication of DE69132998T2 publication Critical patent/DE69132998T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
DE69132998T 1990-09-27 1991-09-23 Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür Expired - Fee Related DE69132998T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2257779A JP2666549B2 (ja) 1990-09-27 1990-09-27 半導体記憶装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE69132998D1 true DE69132998D1 (de) 2002-06-06
DE69132998T2 DE69132998T2 (de) 2002-11-14

Family

ID=17310986

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132998T Expired - Fee Related DE69132998T2 (de) 1990-09-27 1991-09-23 Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür

Country Status (5)

Country Link
US (1) US5135881A (de)
EP (1) EP0478262B1 (de)
JP (1) JP2666549B2 (de)
KR (1) KR960001334B1 (de)
DE (1) DE69132998T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5324680A (en) * 1991-05-22 1994-06-28 Samsung Electronics, Co. Ltd. Semiconductor memory device and the fabrication method thereof
KR960003771B1 (ko) * 1992-08-08 1996-03-22 삼성전자주식회사 반도체 메모리장치
US5362666A (en) * 1992-09-18 1994-11-08 Micron Technology, Inc. Method of producing a self-aligned contact penetrating cell plate
US5377139A (en) * 1992-12-11 1994-12-27 Motorola, Inc. Process forming an integrated circuit
KR100305123B1 (ko) * 1992-12-11 2001-11-22 비센트 비.인그라시아, 알크 엠 아헨 정적랜덤액세스메모리셀및이를포함하는반도체장치
US5270243A (en) * 1993-03-22 1993-12-14 Industrial Technology Research Institute Dram peripheral circuit contact aspect ratio improvement process
JPH06349826A (ja) * 1993-04-13 1994-12-22 Toshiba Corp 半導体装置およびその製造方法
KR0150252B1 (ko) * 1993-07-13 1998-10-01 모리시다 요이치 반도체 기억장치의 제조방법
DE4330471C1 (de) * 1993-09-08 1994-10-20 Siemens Ag Herstellverfahren für ein Bitleitungskontaktloch einer Speicherzelle
US5545926A (en) 1993-10-12 1996-08-13 Kabushiki Kaisha Toshiba Integrated mosfet device with low resistance peripheral diffusion region contacts and low PN-junction failure memory diffusion contacts
JP3261435B2 (ja) 1995-01-19 2002-03-04 マイクロン・テクノロジー・インコーポレイテッド 周辺回路内にトランジスタを形成する方法
JP2663900B2 (ja) * 1995-02-28 1997-10-15 日本電気株式会社 半導体装置の製造方法
KR100192521B1 (ko) * 1996-07-19 1999-06-15 구본준 반도체장치의 제조방법
JPH1187653A (ja) * 1997-09-09 1999-03-30 Fujitsu Ltd 半導体装置およびその製造方法
JP4931267B2 (ja) 1998-01-29 2012-05-16 ルネサスエレクトロニクス株式会社 半導体装置
US6524895B2 (en) 1998-12-25 2003-02-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6159818A (en) * 1999-09-02 2000-12-12 Micron Technology, Inc. Method of forming a container capacitor structure
KR100353804B1 (ko) * 1999-12-28 2002-09-26 주식회사 하이닉스반도체 반도체 소자의 강유전체 캐패시터 형성방법
US6498088B1 (en) * 2000-11-09 2002-12-24 Micron Technology, Inc. Stacked local interconnect structure and method of fabricating same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183952A (ja) * 1985-02-09 1986-08-16 Fujitsu Ltd 半導体記憶装置及びその製造方法
JPH0712058B2 (ja) * 1985-06-27 1995-02-08 株式会社東芝 半導体装置およびその製造方法
JP2960936B2 (ja) * 1987-07-13 1999-10-12 日本電信電話株式会社 係り受け解析装置
JPS6428424A (en) * 1987-07-22 1989-01-31 Sharp Kk Electric carpet with remote controller
JP2906405B2 (ja) * 1987-09-19 1999-06-21 株式会社日立製作所 半導体集積回路装置の製造方法
JP2749072B2 (ja) * 1988-08-12 1998-05-13 株式会社日立製作所 半導体集積回路装置の製造方法
JP2518359B2 (ja) * 1988-09-13 1996-07-24 三菱電機株式会社 半導体記憶装置の製造方法
JPH02122563A (ja) * 1988-10-31 1990-05-10 Nec Corp 半導体装置の製造方法
JP2742272B2 (ja) * 1988-11-11 1998-04-22 株式会社日立製作所 半導体記憶装置の製造方法
DE4034169C2 (de) * 1989-10-26 1994-05-19 Mitsubishi Electric Corp DRAM mit einem Speicherzellenfeld und Herstellungsverfahren dafür
JP2932549B2 (ja) * 1989-12-21 1999-08-09 ソニー株式会社 半導体メモリの製造方法
JP2987882B2 (ja) * 1990-05-28 1999-12-06 ソニー株式会社 半導体メモリの製造方法

Also Published As

Publication number Publication date
KR960001334B1 (ko) 1996-01-26
DE69132998T2 (de) 2002-11-14
EP0478262B1 (de) 2002-05-02
US5135881A (en) 1992-08-04
KR920007191A (ko) 1992-04-28
EP0478262A1 (de) 1992-04-01
JPH04134859A (ja) 1992-05-08
JP2666549B2 (ja) 1997-10-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee