F.DOC/002 A7 B7 五、發明説明（/ ) 本發明是有關於一種具有電容器的半導體記憶體元 件（Semiconductor Memory Device )，且特別是有關於一 種動態隨機存取記憶體（Dynamic Random Access Memory; DRAM )的一記憶單元（Memory Cell )結構，其包含一 轉移電晶體（Transfer Transistor )和一樹型（tree-type ) 儲存電容器。 第1圖是一 DRAM元件的一記憶單元之電路示意圖。 如圖所示，一個記憶單元是由一轉移電晶體T和一儲存電 容器C組成。轉移電晶體T的源極係連接到一對應的位元 線BL，汲極連接到儲存電容器C的一儲存電極6 ( storage electrode )，而閘極則連接到一對應的字元線WL。儲存 電容器C的一相對電極8 ( opposed electrode )係連接到 一固定電壓源，而在儲存電極6和相對電極8之間則設置 一介電膜層7。 經濟部中央標準局員工消費合作社印裝 在傳統DRAM的儲存電容量少於1M ( mega=百萬） 位元時，於積體電路製程中，主要是利用二度空間的電容 器來實現，亦即泛稱的平坦型電容器（Planar type capacitor )。一平坦型電容器需佔用半導體基底的一相當 大的面積來儲存電荷，故並不適合應用於高度的積集化。 高度積集化的DRAM，例如大於4M位元的儲存電容量者’ 需要利用三度空間的電容器來實現，例如所謂的堆疊型 (stacked type )或溝槽型（trench type )電容器。 與平坦型電容器比較，堆疊型或溝槽型電容器可以在 記憶單元的尺寸已進一步縮小的情況下，仍能獲得相當大 3 本紙張尺度適用中國國家標準（CNS ) A4現格（2IOX297公釐） WF.DOC/002 A7 WF.DOC/002 A7 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（工） 的電容量。雖然如此’當記憶體元件再進入更高度的積集 化時，例如具有64M位元容量的DRAM，單純的三度空間 電容器結構已不再適用。 解決之道之一是利用所謂的籍型（fin type )堆疊電容 器。鰭型堆疊電容器之相關技術可參考Ema等人的論文 “3-Dimensional Stacked Capacitor Cell f〇r 16M and 64M DRAMs55, International Electron Devices Meeting, pp. 592-595，Dec. 1988。鰭型堆疊電容器主要是其電極和介電膜層 係由複數個堆疊層，延伸成一水平鰭狀結構，以便增加電 極的表面積。DRAM的鰭型堆疊電容器的相關美國專利 可以參考第 5,071，783 號、第 5，126,810 號、第 5，196,365 號、以及第5,206,787號。 另一種解決之道是利用所謂的筒型（cylindrical type ) 堆疊電容器。筒型堆疊電容器之相關技術可參考Wakamiya 等人的論文 “Novel Stacked Capacitor Cell for 64-Mb DRAM”，1989 Symposium on VLSI Technology Digest of Technical Papers，pp. 69-70。筒型堆疊電容器主要是其電 極和介電膜層係延伸成一垂直筒狀結構，以便增加電極的 表面積。DRAM的筒型堆疊電容器的相關美國專利可以 參考第5,077,688號。 隨著積集度的不斷增加，DRAM記憶單元的尺寸仍會 再縮小。如熟習此藝者所知，記憶單元尺寸縮小，儲存電 容器的電容値也會減少。電容値的減少將導致因α射線入 射所引起的軟錯誤（soft error )機會增加。因此，此藝者 4 本纸張尺度適财關家縣（CNS ) A4規格（210X297公釐) ~ (請先閲讀背面之注意事項再填寫本頁) •裝. 訂 03 I 8TWF.DOC/002 A7 03 I 8TWF.DOC/002 A7 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（3> ) 仍不斷在尋找新的儲存電容器結構及其製造方法，希望在 儲存電容器所佔的平面尺寸被縮小的情況，仍能維持所要 的電容値。 緣此，本發明的一主要目的就是在提供一種具有電容 器的半導體記憶體元件，其電容器具有一樹狀結構，以增 加電容器的儲存電極之表面積。 依照本發明之一較佳實施例，提供一種具有電容器的 半導體記憶體元件，該元件包括：一基底；一轉移電晶體， 形成在基底上，並包括汲極和源極區；以及一儲存電容器， 電性耦接到轉移電晶體的汲極和源極區之一上。其中，儲 存電容器又包括： 一類樹幹狀導電層，具有一底部，電性耦接到轉移電 晶體的汲極和源極區之一上，類樹幹狀導電層又具有一向 上延伸部，以一大致向上的方向從底部延伸出； 至少一類樹枝狀導電層，具有一似L形的剖面，類樹 枝狀導電層的一末端連接在類樹幹狀導電層的外表面 上，類樹幹狀導電層和類樹枝狀導電層構成儲存電容器的 一儲存電極； 一介電層，形成在類樹幹狀導電層和第一類樹枝狀導 電層暴露出的表面上；以及 一上導電層，形成在介電層上，以構成儲存電容器的 一相對電極。 依照本發明之另一較佳實施例，本發明之類樹幹狀導 電層係一體的構件，電性耦接到轉移電晶體的汲極和源極 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ---------i -¾------IT------ - (請先閲讀背面之注意事項再填寫本頁) 312&2Φ F.DOC/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（y) 區之一上，其可以爲T型剖面，也可以爲實心筒狀。 依照本發明之又一較佳實施例，本發明之類樹幹狀導 電層包括一下樹幹部，電性耦接到轉移電晶體的汲極和源 極區之一上，其具有一似T型的剖面；一上樹幹部，大致 以垂直方向自下樹幹部的上表面往上延伸出，其可以爲實 心筒狀，也可以具有一似T型的剖面。又，類樹枝狀導電 層的一末端係連接在上樹幹部的外表面上。 依照本發明之再一較佳實施例，提供一種具有電容器 的半導體記憶體元件，該元件包括：一基底；一轉移電晶 體，形成在基底上，並包括汲極和源極區；以及一儲存電 容器，電性耦接到轉移電晶體的汲極和源極區之一上。 儲存電容器又包括： 一類樹幹狀導電層，具有一底部，電性耦接到轉移電 晶體的汲極和源極區之一上，類樹幹狀導電層又具有一向 上延伸部，以一大致向上的方向從底部延伸出； 至少一第一類樹枝狀導電層，包括一第一延伸段和一 第二延伸段，第一延伸段的一末端連接在類樹幹狀導電層 的外表面上’大致以一水平方向往外延伸出，第二延伸段 大致以一垂直方向，從第一延伸段的另一末端往下延伸 出； 一第二類樹枝狀導電層，具有一似“―”型的剖面，第 二類樹枝狀導電層的一末端連接在類樹幹狀導電層的外 表面上，大致以一水平方向往外延伸出，類樹幹狀導電層 和弟一•'第一類樹枝狀導電層構成儲存電容器的一儲存電 6 I I I I I 丄 I n I ^ II 4 级 (½先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 03 1 8TWF.DOC/002 A7 B7 五、發明説明（Γ) 極； 一介電層，形成在類樹幹狀導電層和第一、第二類樹 枝狀導電層暴露出的表面上；以及 一上導電層，形成在介電層上，以構成儲存電容器的 一相對電極。 依照本發明之又一較佳實施例，第一類樹枝狀導電層 之第一延伸段的一末端連接在類樹幹狀導電層的外表面 上，大致以一水平方向往外延伸出；而第二延伸段則大致 以一垂直方向，從其中一側之第一延伸段的另一末端往下 延伸出。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉若干較佳實施例，並配合所附圖式，作 詳細說明如下= 圖式之簡單說明： 第1圖是一 DRAM元件的一記憶單元之電路示意圖。 第2A至21圖係一系列剖面圖，用以解釋本發明的一 種半導體記憶元件製造方法之第一較佳實施例，以及本發 明的一種半導體記憶元件之第一較佳實施例。 第3A至3E圖係一系列剖面圖，用以解釋本發明的一 種半導體記憶元件製造方法之第二較佳實施例，以及本發 明的一種半導體記憶元件之第二較佳實施例。 第4圖係一剖面圖，用以解釋本發明的一種半導體記 憶元件製造方法之第三較佳實施例，以及本發明的一種半 導體記憶元件之第三較佳實施例。 7 ---------< Ί------1T------ί 4 (t先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） 03 1 8TWF.DOC/002 A7 B7 五、發明説明（/〇 第5A至5E圖係一系列剖面圖，用以解釋本發明的— 種半導體記憶元件製造方法之第四較佳實施例，以及本發 明的一種半導體記憶元件之第四較佳實施例。 第6A至6E圖係一系列剖面圖，用以解釋本發明的— 種半導體記憶元件製造方法之第五較佳實施例，以及本發 明的一種半導體記憶元件之第五較佳實施例。 實施例 首先請參照第2A至21圖，以詳述本發明的一種具有 樹型儲存電容器的半導體記憶元件之第一較佳實施例。 請參照第2A圖，首先將一矽基底10的表面進行熱氧 化製程，例如以矽的局部氧化（LOCOS )技術來達成， 因而形成場區氧化層12 ，其厚度例如約3000人 (angstroms )。接著，再將矽基底1〇進行熱氧化製程， 以形成一閘極氧化層14，其厚度例如約150A。然後，利 用一 CVD (化學氣相沈積）或LPCVD (低壓CVD )法， 在矽基底10的整個表面上沈積一複晶矽層，其厚度例如約 2〇ooA。爲了提高複晶矽層的導電性，可將磷離子植入到 複晶矽層中。較佳是可再沈積一耐火金屬（refractory metal )層’然後施行退火（anneai )步驟，即形成金屬 複晶矽化合物層（polycide )，以更提高其導電性。該耐 火金屬可例如爲鎢（Tungsten)，沈積厚度例如約2000A。 之後’利用傳統的光罩製版（photolithography )和f虫刻 技術定義（pattern )金屬複晶矽化合物層，因而形成如第 2A圖所示的閘極（或稱字元線）WL1與WL2。接著，例 8 本紙張尺度適用中國國家標隼（CNS ) Λ4規格（210X29*7公釐） ---------一 >裝------訂------ -· (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 03 1 8TWF.DOC/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（勹） 如以砷離子植入到矽基底10中，以形成汲極區16以及源 極區18。在此步驟中，字元線WL1與WL2係當作罩幕層， 而離子植入的劑量例如約1 X 1015 atoms/cm2，能量則約 70KeV。 請參照第2B圖，接著以CVD法沈積一絕緣層20，其 例如爲BPSG (硼磷矽玻璃），厚度約7000A。然後，再 以 CVD 法沈積一蝕刻保護層（etching protection layer ) 22，其例如爲砂氮化物層（silicon nitride )，厚度約 1000A。 請參照第2C圖，接著以CVD法沈積一厚的絕緣層24， 其例如爲二氧化矽層，厚度例如約7000A。之後再以CVD 法在絕緣層24表面依序沈積一絕緣層與一犧牲複晶矽 層’並利用傳統的光罩製版和蝕刻技術定義絕緣層與犧牲 複晶矽層，因而形成如圖所示的絕緣層26與犧牲複晶矽層 28 °其中，絕緣層26例如爲矽氮化物層，厚度例如約是 1000A，而犧牲複晶矽層28之厚度例如約是ιοοοΑ。絕緣 層26與犧牲複晶矽層28結構成一堆疊層26; 28，其具有 一凹口 30，凹口 30的較佳位置大致係對應於汲極區16的 上方。 請參照第2D圖，接著分別在堆疊層26; 28的側壁 (sidewal丨s )上形成二氧化砂邊牆（spacers ) 32。在本 較佳實施例中，二氧化矽邊牆32可以以下列步驟形成：沈 積一二氧化矽層，其厚度例如約1000A ;再回蝕刻（etch back )。之後，以CVD法沈積一絕緣層34 ’使其大致塡 9 本紙張尺度適用中國國家標隼（CNS ) A4規格（210 X 297公釐） ---------ί ------ίτ------ J (請先閱讀背面之注意事項再填寫本頁) 03 18TWF.DOC/002 A7 B7 經濟部中央標隼局員工消費合作社印製 五、發明説明（？） 滿凹口 30的空間。絕緣層34例如爲矽氮化物層，厚度例 如約2000A。再來，利用機械化學式硏磨（chemical mechanical polish; CMP )技術硏磨絕緣層34，至少直到 堆疊層26; 28上方的部份露出爲止。 請參照第2E圖，接著以堆疊層26; 28和絕緣層34爲 蝕刻罩幕層，蝕刻去除二氧化矽邊牆32。之後，仍以堆疊 層26; 28和絕緣層34爲蝕刻罩幕層，繼續蝕刻絕緣層24， 但不蝕刻至蝕刻保護層22表面。然後以犧牲複晶矽層28 爲蝕刻罩幕層，蝕刻去除絕緣層34，形成一開口 36。開 口 36的深度可依實際需求加以調整，只要與蝕刻保護層 22保持一段距離即可。 請參照第2F圖，接著在堆疊層26; 28和絕緣層24的 表面沈積一複晶矽層38，厚度例如約1000A，以大致塡滿 開口 36。爲了提高複晶矽層38的導電性，可將例如砷離 子植入到複晶矽層38中。之後，利用機械化學式硏磨技術 硏磨複晶矽層’至少直到絕緣層26上方的部份露出爲止， 形成如圖所示的複晶矽層38。在此步驟中，犧牲複晶矽層 28會被去除。然後以複晶矽層π與絕緣層24爲蝕刻保護 層’利用濕式蝕刻法去除堆疊層26; 28，亦即去除剩餘的 絕緣層26。之後，以CVD法沈積一絕緣層40，其例如是 二氧化砍層，厚度例如約2000A。 請參照第2G圖’接著利用傳統的光罩製版和蝕刻技 術’依序蝕刻絕緣層4〇、複晶矽層38、絕緣層24、蝕刻 保護層22、絕緣層20和閘極氧化層14，以形成儲存電極 -----------------1T------{.^ (#-先閱讀背面之注意事項再填寫本頁) 本紙張尺度賴巾關家縣（CNS)八4規格（2歐297公董） WF. DOC/002 Α7 Β7 五、發明説明（q ) 接觸窗（storage electrode contact holes ) 42，其係由絕 緣層40的上表面延伸到汲極區丨6的表面。之後，以CVD 法在絕緣層40表面沈積一複晶矽層44。複晶矽層44大致 填滿儲存電極接觸窗42且覆蓋絕緣層40的表面。 請參照第2H圖，接著利用傳統的光罩製版與蝕刻技 術’定義複晶砂層44，以界定出記憶單元的儲存電容器之 儲存電極。之後利用濕式蝕刻法，並以蝕刻保護層22爲蝕 刻終點，將暴露出的二氧化矽層去除，亦即去除絕緣層40 與24。藉此步驟即完成動態隨機存取記憶體的儲存電容器 之儲存電極，其如圖所示係由類樹幹狀的複晶矽層44以及 一具有似L形剖面的類樹枝狀複晶矽層38所一起構成。類 樹幹狀的複晶矽層44連接到DRAM的轉移電晶體之汲極 區16，且具有一似T形的剖面。類樹枝狀複晶矽層38從 類樹幹狀的複晶矽層44的外表面，先以約水平方向往外延 伸一段距離後，再以約垂直方向往下延伸出。由於本發明 的儲存電極之形狀非常特殊，故在本說明書中乃以“樹型儲 存電極”稱之，且因而製成之電容器則稱爲“樹型儲存電容 器，，。F.DOC / 002 A7 B7 5. Description of the invention (/) The present invention relates to a semiconductor memory device (Semiconductor Memory Device) with a capacitor, and particularly relates to a dynamic random access memory (Dynamic Random Access Memory) ; DRAM) a memory cell (Memory Cell) structure, which includes a transfer transistor (Transfer Transistor) and a tree-type (tree-type) storage capacitor. Figure 1 is a schematic circuit diagram of a memory cell of a DRAM device. As shown in the figure, a memory cell is composed of a transfer transistor T and a storage capacitor C. The source of the transfer transistor T is connected to a corresponding bit line BL, the drain is connected to a storage electrode 6 (storage electrode) of the storage capacitor C, and the gate is connected to a corresponding word line WL. An opposed electrode 8 of the storage capacitor C is connected to a fixed voltage source, and a dielectric film layer 7 is provided between the storage electrode 6 and the opposite electrode 8. When the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed on the traditional DRAM has a storage capacity of less than 1M (mega = million) bits, in the integrated circuit manufacturing process, it is mainly realized by using capacitors of two degrees of space, that is, Generally known as flat type capacitor (Planar type capacitor). A flat capacitor requires a considerable area of the semiconductor substrate to store charge, so it is not suitable for high accumulation. Highly integrated DRAMs, such as those with a storage capacity greater than 4M bits, need to be realized with three-dimensional capacitors, such as so-called stacked type or trench type capacitors. Compared with flat capacitors, stacked or trench capacitors can still obtain a considerable size even when the size of the memory cell has been further reduced. 3 paper sizes are applicable to the Chinese National Standard (CNS) A4 (2IOX297mm) WF.DOC / 002 A7 WF.DOC / 002 A7 B7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. The electric capacity of the invention description (work). Nonetheless, when the memory device enters a higher degree of integration, such as a DRAM with a capacity of 64M bits, the simple three-dimensional capacitor structure is no longer suitable. One of the solutions is to use so-called fin type stacked capacitors. For the related technology of fin-type stacked capacitors, please refer to the paper “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs 55, International Electron Devices Meeting, pp. 592-595, Dec. 1988 by Ema et al. The electrode and the dielectric film layer are composed of a plurality of stacked layers, extending into a horizontal fin structure, in order to increase the surface area of the electrode. For DRAM fin-type stacked capacitors, related US patents can refer to No. 5,071,783, 5,126,810 , No. 5, 196,365, and No. 5,206,787. Another solution is to use the so-called cylindrical type (cylindrical type) stacked capacitors. For the related technology of cylindrical stacked capacitors, please refer to the paper "Novel Stacked Capacitor Cell for Wakamiya et al. "64-Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. The cylindrical stacked capacitor mainly has its electrode and dielectric film layer extended into a vertical cylindrical structure in order to increase the surface area of the electrode. For related US patents of cylindrical stacked capacitors, please refer to No. 5,077,688. With accumulation The size of the DRAM memory cell will continue to shrink again as the skilled person knows. As the size of the memory cell shrinks, the capacitance value of the storage capacitor will also decrease. The decrease in the capacitance value will cause the softness caused by the incidence of α rays The chance of a soft error increases. Therefore, this artist's 4 paper size is suitable for the Guanjia County (CNS) A4 specification (210X297mm) ~ (please read the precautions on the back before filling this page) • Install. Order 03 I 8TWF.DOC / 002 A7 03 I 8TWF.DOC / 002 A7 Printed B7 by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention description (3 >) Still looking for new storage capacitor structures and manufacturing methods, It is hoped that in the case where the plane size occupied by the storage capacitor is reduced, the desired capacitance value can still be maintained. Therefore, a main object of the present invention is to provide a semiconductor memory device having a capacitor, the capacitor having a tree structure, In order to increase the surface area of the storage electrode of the capacitor. According to a preferred embodiment of the present invention, a semiconductor memory device having a capacitor is provided. Including: a substrate; a transfer transistor formed on the substrate and including the drain and source regions; and a storage capacitor electrically coupled to one of the drain and source regions of the transfer transistor. The storage capacitor further includes: a type of trunk-like conductive layer with a bottom, electrically coupled to one of the drain and source regions of the transfer transistor, and a trunk-like conductive layer with an upward extension to A direction extending generally upward from the bottom; at least one kind of dendritic conductive layer, having an L-shaped cross section, one end of the dendritic conductive layer is connected to the outer surface of the trunk-like conductive layer, the trunk-like conductive layer and The dendritic conductive layer constitutes a storage electrode of the storage capacitor; a dielectric layer formed on the exposed surface of the trunk-like conductive layer and the first dendritic conductive layer; and an upper conductive layer formed on the dielectric layer To constitute a counter electrode of the storage capacitor. According to another preferred embodiment of the present invention, the trunk-like conductive layer of the present invention is an integral component electrically coupled to the drain and source of the transfer transistor. 5 This paper scale is applicable to the Chinese National Standard (CNS) A4 Specifications (210X 297mm) --------- i -¾ ------ IT -------(Please read the precautions on the back before filling this page) 312 & 2Φ F .DOC / 002 A7 B7 Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. One of the invention description (y) areas. It can be a T-shaped profile or a solid tube. According to yet another preferred embodiment of the present invention, the trunk-like conductive layer of the present invention includes a trunk portion electrically coupled to one of the drain and source regions of the transfer transistor, which has a T-like shape A section; an upper trunk portion, extending upward from the upper surface of the lower trunk portion in a vertical direction, which may be a solid tube or may have a T-shaped section. In addition, one end of the dendritic conductive layer is connected to the outer surface of the upper trunk portion. According to yet another preferred embodiment of the present invention, a semiconductor memory device having a capacitor is provided. The device includes: a substrate; a transfer transistor formed on the substrate and including a drain and a source region; and a storage The capacitor is electrically coupled to one of the drain and source regions of the transfer transistor. The storage capacitor further includes: a type of trunk-like conductive layer with a bottom, electrically coupled to one of the drain and source regions of the transfer transistor, and a trunk-like conductive layer with an upward extension, generally upward The direction extends from the bottom; at least a first type of dendritic conductive layer, including a first extension and a second extension, one end of the first extension is connected to the outer surface of the trunk-like conductive layer It extends out in a horizontal direction, and the second extension section extends in a vertical direction from the other end of the first extension section downward; a second type of dendritic conductive layer with a "-" shaped cross section , One end of the second type dendritic conductive layer is connected to the outer surface of the trunk-like conductive layer, and extends out in a horizontal direction. The trunk-like conductive layer and the first type dendritic conductive layer constitute A storage capacitor for storage capacitors 6 IIIII 丄 I n I ^ II Level 4 (½ read the precautions on the back and then fill out this page) The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy 03 1 8TWF.DOC / 002 A7 B7 V. Description of the invention (Γ) pole; a dielectric layer formed on the trunk-like conductive layer and the first and second dendritic conductive The exposed surface of the layer; and an upper conductive layer formed on the dielectric layer to form an opposite electrode of the storage capacitor. According to yet another preferred embodiment of the present invention, one end of the first extension of the first type of dendritic conductive layer is connected to the outer surface of the trunk-like conductive layer, extending outward in a generally horizontal direction; and the second The extending section extends in a vertical direction from the other end of the first extending section on one side downward. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are described below in conjunction with the accompanying drawings, which are described in detail as follows: = A brief description of the drawings: Figure 1 It is a circuit schematic diagram of a memory unit of a DRAM device. 2A to 21 are a series of cross-sectional views for explaining a first preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a first preferred embodiment of a semiconductor memory device of the present invention. Figures 3A to 3E are a series of cross-sectional views for explaining a second preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a second preferred embodiment of a semiconductor memory device of the present invention. Fig. 4 is a cross-sectional view for explaining a third preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a third preferred embodiment of a semiconductor memory device of the present invention. 7 --------- < Ί ------ 1T ------ ί 4 (t read the precautions on the back before filling out this page) This paper scale is applicable to the Chinese National Standard (CNS ) Λ4 specification (210X 297 mm) 03 1 8TWF.DOC / 002 A7 B7 V. Description of the invention (/ 〇 Figures 5A to 5E are a series of cross-sectional views to explain the method of manufacturing semiconductor memory devices of the present invention The fourth preferred embodiment and the fourth preferred embodiment of a semiconductor memory device of the present invention. Figures 6A to 6E are a series of cross-sectional views for explaining the fifth method of manufacturing a semiconductor memory device of the present invention The preferred embodiment and the fifth preferred embodiment of a semiconductor memory device of the present invention. For the embodiment, please refer to FIGS. 2A to 21 to describe in detail the present invention of a semiconductor memory device with a tree-shaped storage capacitor. A preferred embodiment. Referring to FIG. 2A, first, a surface of a silicon substrate 10 is subjected to a thermal oxidation process, for example, by local oxidation of silicon (LOCOS) technology, thereby forming a field oxide layer 12 with a thickness of, for example, about 3000 people (angstroms). Then, the silicon substrate 1 A thermal oxidation process is performed to form a gate oxide layer 14 having a thickness of about 150 A. Then, a CVD (chemical vapor deposition) or LPCVD (low pressure CVD) method is used to deposit a complex on the entire surface of the silicon substrate 10 The thickness of the crystalline silicon layer is, for example, about 20 ooA. In order to improve the conductivity of the polycrystalline silicon layer, phosphorus ions can be implanted into the polycrystalline silicon layer. Preferably, a refractory metal layer can be deposited. Then an annealing (anneai) step is performed to form a metal polycrystalline silicon compound layer (polycide) to further improve its conductivity. The refractory metal can be, for example, tungsten (Tungsten), and the deposition thickness is, for example, about 2000 A. Afterwards, use conventional light The photolithography and fetching patterns define the metal polycrystalline silicon compound layer, thus forming the gates (or word lines) WL1 and WL2 as shown in Figure 2A. Next, Example 8 This paper scale Applicable to China National Standard Falcon (CNS) Λ4 specification (210X29 * 7mm) --------- one> installed ------ ordered ------ (Please read the back first Please pay attention to this page and fill out this page.) Printed by the company 03 1 8TWF.DOC / 002 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (Yi) If arsenic ions are implanted into the silicon substrate 10 to form the drain region 16 and the source Region 18. In this step, the word lines WL1 and WL2 are used as mask layers, and the dose of ion implantation is, for example, about 1 × 1015 atoms / cm2, and the energy is about 70KeV. Please refer to FIG. 2B, and then deposit an insulating layer 20 by CVD, such as BPSG (borophosphosilicate glass), with a thickness of about 7000A. Then, an etching protection layer (etching protection layer) 22 is deposited by CVD, which is, for example, a silicon nitride layer (silicon nitride) with a thickness of about 1000A. Please refer to FIG. 2C, and then deposit a thick insulating layer 24 by CVD, which is, for example, a silicon dioxide layer, and has a thickness of about 7000A, for example. Afterwards, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer 24 by CVD method, and the insulating layer and the sacrificial polycrystalline silicon layer are defined using traditional photomask patterning and etching techniques, thus forming as shown in the figure The insulating layer 26 and the sacrificial polycrystalline silicon layer 28 ° Wherein, the insulating layer 26 is, for example, a silicon nitride layer with a thickness of, for example, about 1000A, and the thickness of the sacrificial polycrystalline silicon layer 28 is, for example, about ιοοοΑ. The insulating layer 26 and the sacrificial polycrystalline silicon layer 28 are structured as a stacked layer 26; 28, which has a notch 30, and the preferred position of the notch 30 corresponds approximately to the top of the drain region 16. Please refer to FIG. 2D, and then form spacers 32 on the side walls (side walls) of the stacked layers 26; 28 respectively. In the preferred embodiment, the silicon dioxide sidewall spacer 32 can be formed by the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000 A; and etching back. Afterwards, an insulating layer 34 'was deposited by CVD method to make it roughly 9 sheets of paper. The Chinese standard Falcon (CNS) A4 specification (210 X 297 mm) --------- ί ---- --ίτ ------ J (Please read the precautions on the back before filling out this page) 03 18TWF.DOC / 002 A7 B7 Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs V. Invention Instructions (?) Full Notch 30 space. The insulating layer 34 is, for example, a silicon nitride layer, and the thickness is, for example, about 2000A. Next, the insulating layer 34 is polished using a chemical mechanical polish (CMP) technique, at least until the portion above the stacked layers 26; 28 is exposed. Please refer to FIG. 2E, and then use the stacked layer 26; 28 and the insulating layer 34 as an etching mask layer to etch and remove the silicon dioxide side wall 32. After that, the stacked layer 26; 28 and the insulating layer 34 are still used as the etching mask layer, and the insulating layer 24 is continuously etched, but the surface of the protective layer 22 is not etched. Then, the sacrificial polycrystalline silicon layer 28 is used as an etching mask layer, and the insulating layer 34 is etched away to form an opening 36. The depth of the opening 36 can be adjusted according to actual needs, as long as it is kept away from the etching protection layer 22. Please refer to FIG. 2F, and then deposit a polycrystalline silicon layer 38 on the surfaces of the stacked layers 26; 28 and the insulating layer 24, with a thickness of, for example, about 1000 A to substantially fill the opening 36. In order to improve the conductivity of the polycrystalline silicon layer 38, for example, arsenic ions can be implanted into the polycrystalline silicon layer 38. After that, the polycrystalline silicon layer 'is polished using a mechanochemical polishing technique until at least the portion above the insulating layer 26 is exposed, and a polycrystalline silicon layer 38 as shown in the figure is formed. In this step, the sacrificial polycrystalline silicon layer 28 is removed. Then, the polycrystalline silicon layer π and the insulating layer 24 are used as etching protective layers' to remove the stacked layer 26; 28, that is, the remaining insulating layer 26 is removed by wet etching. After that, an insulating layer 40 is deposited by CVD, which is, for example, a chopped dioxide layer, and has a thickness of about 2000A, for example. Please refer to FIG. 2G 'Continue to etch the insulating layer 40, the polycrystalline silicon layer 38, the insulating layer 24, the etch protection layer 22, the insulating layer 20 and the gate oxide layer 14 in this order by using traditional photomask patterning and etching techniques' To form a storage electrode ----------------- 1T ------ {. ^ (# -Read the precautions on the back before filling out this page) Guanjia County (CNS) 8.4 specifications (2 Euros 297 dong) WF. DOC / 002 Α7 Β7 5. Description of invention (q) Storage electrode contact holes 42 which extend from the upper surface of the insulating layer 40 To the surface of the dipole region 丨 6. Thereafter, a polycrystalline silicon layer 44 is deposited on the surface of the insulating layer 40 by CVD. The polycrystalline silicon layer 44 substantially fills the storage electrode contact window 42 and covers the surface of the insulating layer 40. Please refer to FIG. 2H, and then use the conventional photolithography and etching technology to define the polycrystalline sand layer 44 to define the storage electrode of the storage capacitor of the memory cell. Then, the wet etching method is used, and the etching protection layer 22 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layers 40 and 24 are removed. With this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed. As shown in the figure, the trunk-like polycrystalline silicon layer 44 and a dendritic polycrystalline silicon layer 38 having an L-shaped cross section are shown. Posed together. The trunk-like polycrystalline silicon layer 44 is connected to the drain region 16 of the DRAM transfer transistor, and has a T-like cross-section. The dendritic polycrystalline silicon layer 38 extends outward from the outer surface of the trunk-like polycrystalline silicon layer 44 in a horizontal direction, and then extends downward in a vertical direction. Since the shape of the storage electrode of the present invention is very special, it is referred to as a "tree-shaped storage electrode" in this specification, and the resulting capacitor is referred to as a "tree-shaped storage capacitor."
請參照第21圖，接著分別在儲存電極44與38裸露的 表面上分別形成一介電膜層46。介電膜層46例如可爲二 氧化矽層、矽氮化物層的NO (矽氮化物/二氧化矽）結構、 0N0 (二氧化矽/矽氮化物/二氧化矽）結構、或任何類似 者。然後’在介電膜層46的表面上，形成由複晶矽製成的 相對電極48。相對電極的製程可由下列步驟達成：以CVD 本纸張尺度適用中國國家榡準（CNS ) Λ4規格（210X 297公釐） --------{-裝------訂------ί (t先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼扃員工消費合作杜印製 03 1 8TWF.DOC/002 A7 B7 五、發明説明（丨？） 法沈積一複晶矽層，其厚度例如爲1000A ;再摻入例如N 型雜質，以提高其導電性；最後以傳統光罩製版和蝕刻技 術定義複晶矽層，完成DRAM各記憶單元的儲存電容器。 雖然第21圖未顯示，然熟習此藝者應瞭解，第21圖的 結構可依傳統製程技術製作位兀線、焊塾（bonding pad )、互連導線（interconnection )、隔絕保護層 (passivation )、以及包裝等等，以完成DRAM積體電路。 由於這些製程非關本發明之特徵，故於此不多作贅述。 在第一較佳實施例中，儲存電極只具有一層似L形剖 面的類樹枝狀電極層。然而，本發明並不限於此，儲存電 極似L形剖面的類樹枝狀電極層之層數可爲二層、三層、 或更多。下一個較佳實施例即將描述具有二層似L形剖面 的類樹枝狀電極層的儲存電極。 接著將參照第3A至3E圖，詳述本發明的一種具有樹 型儲存電容器的半導體記憶元件之第二較佳實施例，半導 體記憶元件的此一較佳實施例，係由本發明的一種半導體 記憶元件製造方法之第二較佳實施例所製造的。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 本較佳實施例係以第2F圖所示的較佳實施例之結構 爲基礎，再以不同的製程製作不同結構的DRAM儲存電 極。在第5A至5D圖中，與第2F圖相似的部份係以相同 的編號標示。 請參照第2F和3A圖，接著以CVD法在絕緣層40表 面依序沈積一絕緣層與一犧牲複晶矽層，並利用傳統的光 罩製版和鈾刻技術定義絕緣層與犧牲複晶矽層’因而形成 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 03 18TWF.DOC/002 s___B7___ 五、發明説明（丨| ) 如圖所示的絕緣層50與犧牲複晶矽層52。其中，絕緣層 5〇例如爲矽氮化物層，厚度例如約是1000A，而犧牲複晶 矽層52之厚度例如約是1000A。絕緣層50與犧牲複晶矽 層52結構成一堆疊層50; 52，其具有一凹口 54，凹口 54 較圖2C中的凹口 30大且較佳位置大致係對應於汲極區16 的上方。 請參照第3B圖，接著分別在堆疊層50; 52的側壁上形 成二氧化矽邊牆56。在本較佳實施例中，二氧化矽邊牆 56可以以下列步驟形成：沈積一二氧化矽層，其厚度例如 約1000A;再回蝕刻。之後，以CVD法沈積一絕緣層58， 使其大致塡滿凹口 54的空間。絕緣層58例如爲矽氮化物 層’厚度例如約2000A。再來，利用機械化學式硏磨技術 研1磨絕緣層58，至少直到堆疊層5〇; 52上方的部份露出爲 止。 請參照第3C圖，接著以堆疊層50; 52和絕緣層58爲 触刻罩幕層，蝕刻去除二氧化矽邊牆56。之後，仍以堆疊 層50; 52和絕緣層58爲蝕刻罩幕層，繼續蝕刻絕緣層4〇 與24 ’但不蝕刻至蝕刻保護層22表面。然後以犧牲複晶 砂層52爲蝕刻罩幕層，蝕刻去除絕緣層58，形成一開口 60 °開口 60的深度可依實際需求加以調整，只要與蝕刻 保護層22保持一段距離即可。 請參照第3D圖，接著在堆疊層50; 52和絕緣層40的 表面沈積一複晶矽層62，厚度例如約ιοοοΑ，以大致塡滿 開口 00。爲了提高複晶矽層62的導電性，可將例如砷離 13 本紙張尺度適用中國國豕CNS ) A4規格（210X297公釐) · ---------ί 1裝------訂-----i纸 ' (t先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印^ 03 1 8TWF.DOC/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（P) 子植入到複晶矽層62中。之後，利用機械化學式硏磨技術 硏磨複晶矽層’至少直到絕緣層50上方的部份露出爲止， 形成如圖所示的複晶矽層62。在此步驟中，犧牲複晶砂層 52會被去除。然後以複晶矽層62與絕緣層40爲蝕刻保護 層，利用濕式触刻法去除堆疊層50; 52 ’亦即去除剩餘的 絕緣層50。之後’以CVD法沈積一絕緣層64，其例如是 二氧化矽層’厚度例如約2000A。 請參照第3E圖，接著利用傳統的光罩製版和蝕刻技 術，依序触刻絕緣層64、複晶砂層62、絕緣層4〇、複晶 矽層38、絕緣層24、蝕刻保護層22、絕緣層2〇和閘極 氧化層14，以形成儲存電極接觸窗66，其係由絕緣層64 的上表面延伸到汲極區16的表面。之後，以CVD法在絕 緣層64表面沈積一複晶矽層68。複晶矽層68大致塡滿儲 存電極接觸窗66且覆蓋絕緣層64的表面。接著利用傳統 的光罩製版與蝕刻技術，定義複晶矽層68，以界定出記憶 單元的儲存電容器之儲存電極。之後利用濕式蝕刻法，並 以触刻保護層22爲触刻終點，將暴露出的二氧化矽層去 除，亦即去除絕緣層64、40與24。藉此步驟即完成動態 隨機存取記憶體的儲存電容器之儲存電極，其如圖所示係 由類樹幹狀的複晶砂層68以及兩層具有似L形剖面的類 樹枝狀複晶矽層62、38所一起構成。類樹幹狀的複晶矽 層68連接到DRAM的轉移電晶體之汲極區16，且具有一 似τ形的剖面。類樹枝狀複晶矽層62與38均從類樹幹狀 的複晶砂層68的外表面，先以約水平方向往外延伸一段距 i i------IT------{.^ (請先閱讀背面之注意事項再填寫本頁) ;紙張尺㈤“見格(1^^-- 03 1 8TWF.DOC/002 A7 B7 經濟部中央標隼局員工消費合作社印裝 五、發明説明（丨5 ) 離後，再以約垂直方向往下延伸出。接下來之後續製程因 無異於傳統製程，故在此不再贅述。 上述第一、第二較佳實施例中之類樹幹狀電極層從剖 面觀之，均具有似T型的剖面’然而’本發明並不限於此’ 下一個較佳實施例即將描述呈柱狀結構的類樹幹狀電極 層的儲存電極。 接著將參照第4圖，詳述本發明的一種具有樹型儲存 電容器的半導體記憶元件之第三較佳實施例，半導體記億 元件的此一較佳實施例，係由本發明的一種半導體記憶元 件製造方法之第三較佳實施例所製造的。 本較佳實施例係以第2G圖所示的較佳實施例之結構 爲基礎，再以不同的製程製作不同結構的DRAM儲存電 極。在第4圖中，與第2G圖相似的部份係以相同的編號 標示。 請參照第2G圖與第4圖，接著利用機械化學式硏磨技 術硏磨複晶矽層44，至少直到絕緣層40上方的部份露出 爲止，形成如圖所示的複晶矽層44。再來利用濕式蝕刻 法，並以蝕刻保護層22爲蝕刻終點，將暴露出的二氧化砂 層去除，亦即去除絕緣層40、24。藉此步驟即完成動態 隨機存取記憶體的儲存電容器之儲存電極，其如圖所示係 由類樹幹狀的複晶矽層44以及一具有似L形剖面的類樹 枝狀複晶砂層38所一起構成。類樹幹狀的複晶砂層44連 接到DRAM的轉移電晶體之汲極區16，且呈實心筒狀。 類樹枝狀複晶砂層從類樹幹狀的複晶砂層44的外表面，先 本紙張尺度適用中國國家榡準（CNS ) Λ4規格（210X297公釐） ---------{-裝------訂-----i線 (t先閲讀背面之注意事項再填寫本頁) 03 1 8TWF.DOC/002 A7 03 1 8TWF.DOC/002 A7 經濟部中央梯隼局員工消費合作社印製 ____B7___ 五、發明説明（#) 以約水平方向往外延伸一段距離後，再以約垂直方向往下 延伸出。接下來之後續製程因無異於傳統製程，故在此不 再贅述。在本較佳實施例中係以機械化學式硏磨技術形成 類樹幹狀導電層，然熟悉此藝者應知也可利用回蝕刻技 術，定義圖2G中的複晶矽層44，而形成實心筒狀類樹幹 狀導電層。或者在圖2G中，於形成儲存電極接觸窗42後’ 以磊晶（Epitaxy)方式形成一複晶矽層，使之塡滿儲存電極 接觸窗42，以結構成實心筒狀類樹幹狀導電層。 在上述第一、第二和第三較佳實施例中，儲存電極的 類樹幹狀電極層均係一體的構件，且自剖面觀之，儲存電 極的每一層類樹枝狀電極層均具有二支似L型樹枝。然 而，本發明並不限於此，下一個較佳實施例即將描述類樹 幹狀電極層係由複數個部份構成的儲存電極’且儲存電極 的類樹枝狀電極層自剖面觀之，其中一支樹枝係似L型’ 而另一支只具有水平延伸段。 接著將參照第5A至5E圖，詳述本發明的一種具有樹 型儲存電容器的半導體記憶元件之第四較佳實施例’半導 體記憶元件的此一較佳實施例，係由本發明的一種半導體 記憶元件製造方法之第四較佳實施例所製造的。 本較佳實施例係以第2B圖所示的較佳實施例之結構 爲基礎，再以不同的製程製作不同結構的DRAM儲存電 極。在第5A至5E圖中，與第2B圖相似的部份係以相同 的編號標Tpc。 請參照第2B圖與第5A圖，接著利用傳統的光罩製版 16 本紙張尺度適用中國國家橾準（CNS ) Λ4規格（210X297公釐） ---------< 裝------訂-----i線 (會先閱讀背面之注意事項再填寫本頁) 03 18TWF.DOC/002 A7 B7 經濟部中央標準局員工消費合作杜印裝 五、發明説明（/y) 和餓刻技術’依序蝕刻餓刻保護層22、絕緣層2〇、和閘 極氧化層I4，以形成儲存電極接觸窗％，其係分別由蝕 刻保護層22的上表面延伸到汲極區16的表面。接著，以 CVD法在蝕刻保護層22的表面沈積—複晶砂層72。爲了 提高複晶矽層72的導電性，可將例如砷離子植入到複晶矽 層72中。如圖所不’複晶砂層72塡滿儲存電極接觸窗7〇， 且覆蓋蝕刻保護層22的表面。之後，在複晶砂層72表面 沈積一厚的絕緣層74，其例如爲二氧化砂層，厚度例如約 7000A。然後再以CVD法在絕緣層Μ表面依序沈積一絕 緣層與一犧牲複晶矽層’並利用傳統的光罩製版和蝕刻技 術定義絕緣層與犧牲複晶矽層，因而形成如圖所示的絕緣 層76與犧牲複晶矽層78。其中，絕緣層76例如爲矽氮化 物層’厚度例如約是1000A，而犧牲複晶矽層78之厚度例 如約是1000A。絕緣層76與犧牲複晶矽層78結構成一堆 疊層76; 78，其具有一凹口 80，凹口 80的中心往下對應 的較佳位置大致係偏向汲極區16的某一側。在本較佳實施 例中，凹口 80係偏向汲極區16的左側。 請參照第5B圖，接著分別在堆疊層76; 78的側壁上形 成二氧化矽邊牆82。在本較佳實施例中，二氧化矽邊牆 82可以以下列步驟形成：沈積一二氧化矽層’其厚度例如 約1000A;再回蝕刻。之後，以CVD法沈積一絕緣層84， 使其大致塡滿凹口 80的空間。絕緣層84例如爲砂氮化物 層，厚度例如約2000A。再來’利用機械化學式硏磨技術 硏磨絕緣層84，至少直到堆疊層76; 78上方的部份露出爲 ---------ί -裝------訂-----i 線 (*'先閲讀背面之注意事項再填寫本頁) 本紙浪尺度適用中國國家標準（CNS ) Λ4規格（210X：297公釐） 312獅 F.DOC/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明说明（A ) 止。 請參照第5C圖，接著以堆疊層76; 78和絕緣層84爲 蝕刻罩幕層，蝕刻去除二氧化矽邊牆82。之後，仍以堆疊 層76; 78和絕緣層M爲蝕刻罩幕層，繼續鈾刻絕緣層74 , 但不蝕刻至複晶矽層72表面。然後以犧牲複晶矽層78爲 蝕刻罩幕層，蝕刻去除絕緣層料，形成一開口 86。開口 86的涞度可依實際需求加以調整，只要與複晶矽層72保 持一段距離即可。之後在堆疊層76;78和絕緣層74的表面 沈積一複晶矽層88，厚度例如約1〇〇〇A，以大致塡滿開口 86。爲了提咼複晶矽層88的導電性，可將例如砷離子植 入到複晶矽層88中。之後，利用機械化學式硏磨技術硏磨 複晶矽層，至少直到絕緣層76上方的部份露出爲止，形成 如圖所不的複晶砂層88。在此步驟中，犧牲複晶砂層78 會被去除。 SR參照第5D圖’接著以複晶矽層88與絕緣層74爲蝕 刻保護層’利用濕式蝕刻法去除堆疊層76; 78，亦即去除 剩餘^絕緣層76。之後，以CVD法沈積-絕緣層90，其 例如疋一氧化矽層，厚度例如約2〇〇〇人。然後利用傳統的 光罩製版和義贿’咖於漏區16的上方處，依序飽 刻絕緣層90、複晶矽層88與絕緣層74，直到複晶矽層72 的表f爲止’以形成_開口 92。再來在開日％中形成一 ’期彡成方式麵是縣晶方式或 以沈積後再回蝕刻方式形成。 請參照第5Ε圖’接著利用傳統的光罩製版與蝕刻技 本紙。度適用中國 ---------ί ------,订------^ ^ (t先閲讀背面之注意事項再填寫本頁) A7 03 I 8TWF.DOC/002 B7 五、發明説明（/'1) 術，定義複晶矽層88與72，以界定出記憶單元的儲存電 容器之儲存電極，形成如圖所示的複晶矽層88與72。亦 即藉此步驟將複晶矽層88其中一側的垂直延伸段去除。之 後利用濕式蝕刻法’並以蝕刻保護層22爲蝕刻終點，將暴 露出的二氧化矽層去除，亦即去除絕緣層90與74。藉此 步驟即完成動態隨機存取記憶體的儲存電容器之儲存電 極，其如圖所示係由類樹幹狀的上複晶矽層94、類樹幹狀 的下複晶矽層72以及一僅有單邊具有似l形剖面的類樹 枝狀複晶矽層88所一起構成。類樹幹狀的下複晶矽層72 連接到DRAM的轉移電晶體之汲極區16，且具有一似τ 形的剖面。類樹幹狀的上複晶矽層94係從類樹幹狀的下複 晶矽層72的上表面’大致以垂直的方向往上延伸出。類樹 枝狀複晶砂層88係從類樹幹狀的上複晶砂層94的外表 面’先以約水平方向往外延伸一段距離，之後，其中一側 的水平延伸段的一末端再以約垂直方向往下延伸出。 在上述第一至第四較佳實施例中，儲存電極的類樹枝 狀電極層均只有似L形剖面。然而，本發明並不限於此， 儲存電極的類樹枝狀電極層可以包括有其他剖面形狀。下 一個較佳實施例即將描述具有一層似！^形剖面與一似“一” 型剖面的類樹枝狀電極層的儲存電極。另外，在上一個較 佳實施例中’類樹幹狀的下複晶矽層的水平部份之下表面 係與其下方的蝕刻保護層接觸。然而，本發明亦不限於此， 下一個較佳實施例即將描述類樹幹狀的下複晶矽層的水 平部份之下表面未與其下方的蝕刻保護層接觸，而相距一 --------i i------IT------ (t先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本纸張尺度適财家縣（CNS) Λ4規格（2|Gx297公着） 03 I 8TWF.D〇C/°°2 A7 B7 經濟部中央標準局員工消費合作杜印製 五、發明説明（好） 釋受^離，以更增加儲存電極的表面積之作法。 X接著將參照第6A至6E圖’詳述本發明的一種具有樹 开^1§#電容器的半導體記憶元件之第五較佳實施例’半導 3§己億元件的此一較佳實施例’係由本發明的一種半導體 §己^、^件製造方法之第五較佳實施例所製造的。 ° ^本較佳實施例係以第2B圖所示的較佳實施例之結構 爲基礎，再以不同的製程製作不同結構的DRAM儲存電 極。在第6A至6E圖中，與第2B圖相似的部份係以相同 的編號標不° 請參照第2B圖和第6A圖’接著以CVD法在蝕刻保護 層22表面沈積一絕緣層96，其例如爲二氧化矽層’厚度 約1000A。之後，利用傳統的光罩製版和蝕刻技術’依序 蝕刻絕緣層96、蝕刻保護層22 '絕緣層20和閘極氧化層 14，以形成儲存電極接觸窗98 ’其係分別由絕緣層96的 上表面延伸到汲極區16的表面。接著’在絕緣層96的表 面沈積一複晶矽層100。爲了提高複晶矽層的導電性，可 將例如砷離子植入到複晶矽層中。如圖所示，複晶矽層100 塡滿儲存電極接觸窗98，且覆蓋住絕緣層96的表面。之 後，在複晶矽層1〇〇的表面沈積一厚的絕緣層102，其例 如爲二氧化矽層，厚度例如約7000A。之後再以CVD法在 絕緣層102表面依序沈積一絕緣層與一犧牲複晶矽層，並 利用傳統的光罩製版和蝕刻技術定義絕緣層與犧牲複晶 砂層’因而形成如圖所示的絕緣層104與犧牲複晶矽層 106 °其中，絕緣層104例如爲矽氮化物層，厚度例如約Referring to FIG. 21, a dielectric film layer 46 is formed on the exposed surfaces of the storage electrodes 44 and 38, respectively. The dielectric film layer 46 may be, for example, a silicon dioxide layer, a NO (silicon nitride / silicon dioxide) structure of a silicon nitride layer, a 0N0 (silicon dioxide / silicon nitride / silicon dioxide) structure, or any similar . Then, on the surface of the dielectric film layer 46, a counter electrode 48 made of polycrystalline silicon is formed. The process of the counter electrode can be achieved by the following steps: CVD This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) -------- {-装 ------ booking- ----- ί (t read the precautions on the back before filling this page) Ministry of Economic Affairs Central Standard Falcon Employee Consumption Cooperation Du Printed 03 1 8TWF.DOC / 002 A7 B7 V. Description of the invention (丨?) A polycrystalline silicon layer with a thickness of, for example, 1000A; then doped with, for example, N-type impurities to improve its conductivity; finally, the polycrystalline silicon layer is defined by traditional mask making and etching techniques to complete the storage capacitor of each memory cell of DRAM. Although Figure 21 is not shown, those familiar with this art should understand that the structure of Figure 21 can be made according to traditional manufacturing techniques, such as bit lines, bonding pads, interconnection wires, and isolation protection layers (passivation) , And packaging, etc., to complete the DRAM integrated circuit. Since these processes are not characteristic of the present invention, they will not be repeated here. In the first preferred embodiment, the storage electrode has only one layer like dendritic electrode layer with an L-shaped cross-section. However, the present invention is not limited to this, and the number of layers of the dendritic electrode layer having a storage electrode resembling an L-shaped cross-section may be two, three, or more. The next preferred embodiment will describe a storage electrode having two dendritic-like electrode layers having an L-shaped cross section. Next, referring to FIGS. 3A to 3E, a second preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is a semiconductor memory of the present invention. The second preferred embodiment of the device manufacturing method is manufactured. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) This preferred embodiment is based on the structure of the preferred embodiment shown in Figure 2F, and then uses different processes Fabricate DRAM storage electrodes with different structures. In Figs. 5A to 5D, the parts similar to those in Fig. 2F are marked with the same numbers. Please refer to Figures 2F and 3A, and then deposit an insulating layer and a sacrificial polycrystalline silicon layer on the surface of the insulating layer 40 by CVD in sequence, and define the insulating layer and sacrificial polycrystalline silicon using traditional photolithography and uranium engraving techniques The 'layer' thus forms the paper scale applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) A7 03 18TWF.DOC / 002 s___B7___ V. Invention description (丨 |) Insulation layer 50 and sacrificial polycrystalline silicon as shown Layer 52. The insulating layer 50 is, for example, a silicon nitride layer with a thickness of about 1000A, and the thickness of the sacrificial polycrystalline silicon layer 52 is about 1000A, for example. The insulating layer 50 and the sacrificial polycrystalline silicon layer 52 are structured as a stacked layer 50; 52, which has a notch 54, which is larger than the notch 30 in FIG. 2C and the preferred position roughly corresponds to the drain region 16 Above. Please refer to FIG. 3B, and then form silicon dioxide sidewalls 56 on the side walls of the stacked layers 50; 52 respectively. In the preferred embodiment, the silicon dioxide sidewall spacer 56 can be formed by the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000 A; and then etching back. After that, an insulating layer 58 is deposited by CVD so that the space of the recess 54 is substantially filled. The insulating layer 58 is, for example, a silicon nitride layer 'and the thickness is, for example, about 2000A. Next, the mechanochemical grinding technique is used to grind the insulating layer 58 until at least the portion above the stacked layer 50; 52 is exposed. Please refer to FIG. 3C, and then use the stacked layer 50; 52 and the insulating layer 58 as the touch mask curtain layer, and etch and remove the silicon dioxide side wall 56. After that, the stacked layers 50; 52 and the insulating layer 58 are still used as the etching mask layer, and the insulating layers 40 and 24 'are continuously etched but not etched to the surface of the etching protection layer 22. Then, the sacrificial polycrystalline sand layer 52 is used as an etching mask layer, and the insulating layer 58 is etched to form an opening 60 °. The depth of the opening 60 can be adjusted according to actual needs, as long as it is kept away from the etching protection layer 22. Please refer to FIG. 3D, and then deposit a polycrystalline silicon layer 62 on the surface of the stacked layer 50; 52 and the insulating layer 40, with a thickness of, for example, about ιοοΑ to substantially fill the opening 00. In order to improve the conductivity of the polycrystalline silicon layer 62, for example, arsenic 13 can be applied to the Chinese paper standard CNS) A4 specification (210X297mm) · --------- ί 1 device ---- --Subscribe ----- i paper '(t read the notes on the back before filling out this page) Printed by the Employees Consumption Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ 03 1 8TWF.DOC / 002 A7 B7 Employee Consumption of the Central Bureau of Standards of the Ministry of Economic Affairs Printed by the cooperative. Fifth, the description of invention (P) is implanted into the polycrystalline silicon layer 62. After that, the polycrystalline silicon layer 'is polished using a mechanochemical grinding technique until at least the portion above the insulating layer 50 is exposed to form a polycrystalline silicon layer 62 as shown in the figure. In this step, the sacrificial polycrystalline sand layer 52 is removed. Then, the polycrystalline silicon layer 62 and the insulating layer 40 are used as etching protective layers, and the stacked layer 50 is removed by wet contact etching; 52 ', that is, the remaining insulating layer 50 is removed. Afterwards, an insulating layer 64 is deposited by CVD, which is, for example, a silicon dioxide layer. The thickness is, for example, about 2000A. Please refer to FIG. 3E, and then use the traditional mask making and etching techniques to sequentially insulate the insulating layer 64, polycrystalline sand layer 62, insulating layer 40, polycrystalline silicon layer 38, insulating layer 24, etching protection layer 22, The insulating layer 20 and the gate oxide layer 14 form a storage electrode contact window 66 that extends from the upper surface of the insulating layer 64 to the surface of the drain region 16. After that, a polycrystalline silicon layer 68 is deposited on the surface of the insulating layer 64 by CVD. The polycrystalline silicon layer 68 substantially fills the storage electrode contact window 66 and covers the surface of the insulating layer 64. Then, using traditional photomask patterning and etching techniques, the polycrystalline silicon layer 68 is defined to define the storage electrode of the storage capacitor of the memory cell. After that, the wet etching method is used to remove the exposed silicon dioxide layer using the touch protection layer 22 as the touch end point, that is, the insulating layers 64, 40 and 24 are removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed. As shown in the figure, it is composed of a trunk-like polycrystalline sand layer 68 and two layers of dendritic polycrystalline silicon layer 62 having an L-shaped cross section. , 38 together. The trunk-like polycrystalline silicon layer 68 is connected to the drain region 16 of the DRAM transfer transistor, and has a τ-shaped cross-section. The dendritic polycrystalline silicon layers 62 and 38 both extend from the outer surface of the trunk-like polycrystalline sand layer 68 in a horizontal direction to a distance i i ------ IT ------ {. ^ (Please read the precautions on the back before filling in this page); paper ruler ㈤ "see grid (1 ^^-03 1 8TWF.DOC / 002 A7 B7 Central Standard Falcon Bureau Employee Consumer Cooperative Printed by the Ministry of Economy V. Inventions Description (丨 5) After the separation, it will extend downward in a vertical direction. The subsequent subsequent process is no different from the traditional process, so it will not be repeated here. The above first and second preferred embodiments are similar The trunk electrode layer has a T-shaped cross section when viewed from the cross section. However, the present invention is not limited to this. The next preferred embodiment will describe the storage electrode of the trunk-like electrode layer with a columnar structure. Referring to FIG. 4, the third preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention is described in detail. This preferred embodiment of a semiconductor memory device is a semiconductor memory device manufacturing method of the present invention The third preferred embodiment is manufactured. This preferred embodiment is based on the second Based on the structure of the preferred embodiment shown in Figure G, DRAM storage electrodes with different structures are manufactured by different processes. In Figure 4, parts similar to those in Figure 2G are marked with the same number. Please refer to 2G and FIG. 4, the polycrystalline silicon layer 44 is then polished using mechanochemical polishing technology, at least until the portion above the insulating layer 40 is exposed, forming the polycrystalline silicon layer 44 as shown in the figure. The wet etching method uses the etching protection layer 22 as the etching end point to remove the exposed sand dioxide layer, that is, the insulating layers 40 and 24. This step completes the storage electrode of the storage capacitor of the dynamic random access memory As shown in the figure, it is composed of a trunk-like polycrystalline silicon layer 44 and a dendritic-like polycrystalline sand layer 38 having an L-shaped cross-section. The trunk-like polycrystalline sand layer 44 is connected to the transfer power of the DRAM The dip region 16 of the crystal is a solid tube. The dendrite-like polycrystalline sand layer is from the outer surface of the trunk-like polycrystalline sand layer 44. The paper size is in accordance with China National Standard (CNS) Λ4 specification (210X297mm ) --------- {-installed ------ ----- i line (t read the precautions on the back before filling in this page) 03 1 8TWF.DOC / 002 A7 03 1 8TWF.DOC / 002 A7 Printed by the Employee Consumer Cooperative of the Central Falcon Bureau of the Ministry of Economic Affairs____B7___ 5 2. Description of the invention (#) After extending a certain distance outward in the horizontal direction, it extends downward in the vertical direction. The following subsequent processes are no different from the traditional processes, so they will not be repeated here. In this preferred embodiment In the example, the trunk-like conductive layer is formed by mechanochemical grinding technology. However, those skilled in the art should also use the etch-back technique to define the polycrystalline silicon layer 44 in FIG. 2G to form a solid tubular trunk-like conductive layer. . Or in FIG. 2G, after forming the storage electrode contact window 42, a polycrystalline silicon layer is formed by epitaxy to fill the storage electrode contact window 42 to form a solid cylindrical trunk-like conductive layer . In the above first, second and third preferred embodiments, the trunk-like electrode layer of the storage electrode is an integral member, and from a cross-sectional view, each layer of the dendritic electrode layer of the storage electrode has two branches Like L-shaped branches. However, the present invention is not limited to this. The next preferred embodiment will describe the trunk-like electrode layer is a storage electrode composed of a plurality of parts and the dendritic electrode layer of the storage electrode is viewed from a cross-section. The branch is L-shaped and the other branch only has a horizontal extension. Next, with reference to FIGS. 5A to 5E, a fourth preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of a semiconductor memory device is a semiconductor memory of the present invention. The fourth preferred embodiment of the device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2B, and then DRAM storage electrodes with different structures are manufactured by different processes. In Figs. 5A to 5E, the parts similar to those in Fig. 2B are marked with the same number Tpc. Please refer to Figure 2B and Figure 5A, and then use the traditional photomask to make 16 copies of this paper. The paper is suitable for China National Standard (CNS) Λ4 specification (210X297mm) --------- < ---- order ----- i line (will read the precautions on the back and then fill out this page) 03 18TWF.DOC / 002 A7 B7 Employee's consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs Du Printed Fifth, invention description (/ y) and etching technology 'sequentially etch the etching protection layer 22, the insulating layer 20, and the gate oxide layer I4 to form a storage electrode contact window%, which respectively extend from the upper surface of the etching protection layer 22 to The surface of the polar region 16. Next, a polycrystalline sand layer 72 is deposited on the surface of the etching protection layer 22 by CVD. In order to improve the conductivity of the polycrystalline silicon layer 72, for example, arsenic ions may be implanted into the polycrystalline silicon layer 72. As shown in the figure, the polycrystalline sand layer 72 is filled with the storage electrode contact window 70 and covers the surface of the etching protection layer 22. After that, a thick insulating layer 74 is deposited on the surface of the polycrystalline sand layer 72, which is, for example, a layer of sand dioxide with a thickness of, for example, about 7000A. Then, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer M by the CVD method, and the insulating layer and the sacrificial polycrystalline silicon layer are defined by using traditional photomask patterning and etching techniques, thus forming as shown in the figure Insulating layer 76 and sacrificial polycrystalline silicon layer 78. The thickness of the insulating layer 76 is, for example, a silicon nitride layer ', for example, about 1000A, and the thickness of the sacrificial polycrystalline silicon layer 78 is, for example, about 1000A. The insulating layer 76 and the sacrificial polycrystalline silicon layer 78 are structured as a stack 76; 78, which has a notch 80, and the preferred position corresponding to the center of the notch 80 is generally biased to one side of the drain region 16. In the preferred embodiment, the recess 80 is biased to the left of the drain region 16. Please refer to FIG. 5B, and then form silicon dioxide sidewalls 82 on the side walls of the stacked layers 76; 78 respectively. In this preferred embodiment, the silicon dioxide sidewall spacer 82 can be formed by the following steps: depositing a silicon dioxide layer ' whose thickness is, for example, about 1000A; and then etching back. After that, an insulating layer 84 is deposited by CVD so that the space of the recess 80 is substantially filled. The insulating layer 84 is, for example, a sand nitride layer, and the thickness is, for example, about 2000A. Let's use the mechanochemical grinding technology to grind the insulating layer 84, at least until the stacked layer 76; the part above 78 is exposed as --------- ί-装 ------ booking --- --i line (* 'Read the precautions on the back and then fill out this page) The standard of this paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X: 297mm) 312 Lion F.DOC / 002 A7 B7 Central Standard of the Ministry of Economy Printed by the Bureau ’s Consumer Cooperatives V. Invention Instructions (A) Only. Please refer to FIG. 5C, and then use the stacked layer 76; 78 and the insulating layer 84 as an etching mask layer to etch and remove the silicon dioxide side wall 82. After that, the stacked layer 76; 78 and the insulating layer M are used as the etching mask layer, and the insulating layer 74 is etched by uranium, but it is not etched to the surface of the polycrystalline silicon layer 72. Then, the sacrificial polycrystalline silicon layer 78 is used as an etching mask layer, and the insulating layer material is etched away to form an opening 86. The latitude of the opening 86 can be adjusted according to actual needs, as long as it is kept at a distance from the polycrystalline silicon layer 72. Then, a polycrystalline silicon layer 88 is deposited on the surfaces of the stacked layers 76; 78 and the insulating layer 74, with a thickness of, for example, about 1000 A to substantially fill the opening 86. In order to improve the conductivity of the polycrystalline silicon layer 88, for example, arsenic ions can be implanted into the polycrystalline silicon layer 88. After that, the polycrystalline silicon layer is polished by mechanochemical polishing technology, at least until the portion above the insulating layer 76 is exposed, and a polycrystalline sand layer 88 as shown in the figure is formed. In this step, the sacrificial polycrystalline sand layer 78 is removed. SR refers to FIG. 5D, and then the polycrystalline silicon layer 88 and the insulating layer 74 are used as etching protective layers. The stacked layer 76 is removed by wet etching; 78, that is, the remaining insulating layer 76 is removed. Thereafter, an insulating layer 90 is deposited by CVD, such as a silicon monoxide layer, with a thickness of about 2,000 people, for example. Then use traditional photomask plate making and bribery to "squeeze the insulating layer 90, the polycrystalline silicon layer 88 and the insulating layer 74 in sequence above the drain region 16 until the surface f of the polycrystalline silicon layer 72" is formed _Opening 92. Next, the formation of one-period formation method in the opening day is the prefectural crystal method or the etching method after deposition. Please refer to Figure 5E 'and then use traditional photomask plate making and etching technology paper. Degrees apply to China --------- ί ------, order ------ ^ ^ (t read the precautions on the back before filling this page) A7 03 I 8TWF.DOC / 002 B7 V. Description of the Invention (/ '1) The technique defines polycrystalline silicon layers 88 and 72 to define the storage electrodes of the storage capacitors of the memory cells, forming the polycrystalline silicon layers 88 and 72 as shown. That is, the vertical extension on one side of the polycrystalline silicon layer 88 is removed by this step. Thereafter, the wet etching method is used and the etching protection layer 22 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layers 90 and 74 are removed. With this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed. As shown in the figure, the trunk-like upper polycrystalline silicon layer 94, the trunk-like lower polycrystalline silicon layer 72, and a single The dendritic polycrystalline silicon layer 88 having a l-shaped cross section on one side is formed together. The trunk-like lower polycrystalline silicon layer 72 is connected to the drain region 16 of the transfer transistor of the DRAM, and has a τ-shaped cross section. The trunk-like upper polycrystalline silicon layer 94 extends from the upper surface of the trunk-like lower polycrystalline silicon layer 72 in a substantially vertical direction. The dendrite-like polycrystalline sand layer 88 extends from the outer surface of the trunk-like upper polycrystalline sand layer 94 first by a distance in the horizontal direction, and then, one end of the horizontal extension on one side then goes in the vertical direction Extend out. In the above-mentioned first to fourth preferred embodiments, the dendritic-like electrode layers of the storage electrode all have L-like cross-sections. However, the present invention is not limited thereto, and the dendritic electrode layer of the storage electrode may include other cross-sectional shapes. The next preferred embodiment will be described as having a layer! The storage electrode of the ^ -shaped cross-section and a dendritic electrode layer resembling a "one" -shaped cross-section. In addition, in the previous preferred embodiment, the lower surface of the horizontal portion of the trunk-like lower polycrystalline silicon layer is in contact with the etching protection layer thereunder. However, the present invention is not limited to this. The next preferred embodiment will describe that the lower surface of the horizontal part of the trunk-like lower polycrystalline silicon layer is not in contact with the etch protection layer underneath, and is separated by one ----- --- i i ------ IT ------ (t read the precautions on the back before filling in this page) The paper standard printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is suitable for Caijia County ( CNS) Λ4 specification (2 | Gx297 publication) 03 I 8TWF.D〇C / °° 2 A7 B7 Printed by the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the invention (good) Release and accept ^ to increase The method of storing the surface area of the electrode. X will then be described in detail with reference to FIGS. 6A to 6E 'a fifth preferred embodiment of a semiconductor memory device with a capacitor ^ 1§ # of the present invention, which is a preferred embodiment of a semiconducting 3§ half billion device Is manufactured by the fifth preferred embodiment of a semiconductor manufacturing method of the present invention. ° ^ This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2B, and then DRAM storage electrodes with different structures are fabricated by different processes. In FIGS. 6A to 6E, the parts similar to those in FIG. 2B are marked with the same number. Please refer to FIGS. 2B and 6A. Then, an insulating layer 96 is deposited on the surface of the etching protection layer 22 by CVD. It is, for example, a silicon dioxide layer 'with a thickness of about 1000A. After that, the traditional photomask patterning and etching techniques are used to sequentially etch the insulating layer 96, the etching protection layer 22, the insulating layer 20, and the gate oxide layer 14 to form the storage electrode contact window 98, which is formed by the insulating layer 96 The upper surface extends to the surface of the drain region 16. Next, a polycrystalline silicon layer 100 is deposited on the surface of the insulating layer 96. In order to improve the conductivity of the polycrystalline silicon layer, for example, arsenic ions can be implanted into the polycrystalline silicon layer. As shown, the polycrystalline silicon layer 100 fills the storage electrode contact window 98 and covers the surface of the insulating layer 96. After that, a thick insulating layer 102, such as a silicon dioxide layer, is deposited on the surface of the polycrystalline silicon layer 100, with a thickness of about 7000 A, for example. After that, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer 102 by CVD method, and the insulating layer and the sacrificial polycrystalline sand layer are defined using traditional photomask patterning and etching techniques. The insulating layer 104 and the sacrificial polycrystalline silicon layer 106 ° Wherein, the insulating layer 104 is, for example, a silicon nitride layer, and the thickness is, for example, about
(CNS ) Λ4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁) •裂. 訂 線 經濟部中央橾準局員工消費合作社印製 TT3V8TWF.DOC/002 一__B7 五、發明説明（ή ) 是ΙΟΟΟΑ，而犧牲複晶矽層106之厚度例如約是1000A。 絕緣層104與犧牲複晶矽層106結構成一堆疊層104; 106，其具有一凹口 108，凹口 108的較佳位置大致係對 應於汲極區16的上方。 請參照第6B圖，接著分別在堆疊層1〇4; 106的側壁上 形成二氧化矽邊牆110。在本較佳實施例中，二氧化矽邊 牆110可以以下列步驟形成：沈積一二氧化矽層，其厚度 例如約1000A ;再回蝕刻。之後，以CVD法沈積一絕緣層 112 ’使其大致塡滿凹口 108的空間。絕緣層112例如爲 矽氮化物層，厚度例如約2000A。再來，利用機械化學式 硏磨技術硏磨絕緣層112，至少直到堆疊層1〇4; 106上方 的部份露出爲止。 請參照第6C圖，接著以堆疊層1〇4; 106和絕緣層112 爲蝕刻罩幕層，触刻去除二氧化砂邊牆110。之後，仍以 堆疊層104; 106和絕緣層112爲蝕刻罩幕層，繼續蝕刻絕 緣層102 ’但不蝕刻至複晶矽層ι00表面。然後以犧牲複 晶矽層106爲飩刻罩幕層’蝕刻去除絕緣層n2，形成一 開口 114。開口 114的深度可依實際需求加以調整’只要 與複晶砍層100保持一段距離即可。接著在堆疊層104; 1〇6 和絕緣層102的表面沈積一複晶矽層n6，厚度例如約 1000A，以大致塡滿開口 II4。爲了提高複晶矽層116的 導電性’可將例如砷離子植入到複晶矽層116中。之後， 利用機械化學式硏磨技術硏磨複晶矽層，至少直到絕緣層 104上方的部份露出爲止，形成如圖所示的複晶砂層116。 (請先閲讀背面之注意事項再填寫本頁) -裝_ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X：297公嫠） 經濟部中央標準局員工消費合作社印製 03 1 8TWF.DOC/002 A7 ____B7_____ 五、發明説明（β) 在此步驟中，犧牲複晶矽層106會被去除。 請參照第6D圖，接著以複晶矽層116與絕緣層102爲 蝕刻保護層，利用濕式蝕刻法去除堆疊層104; 106，亦即 去除剩餘的絕緣層104。之後，以CVD法依序沈積一絕緣 層118、一複晶矽層120與一絕緣層122,其中絕緣層118、 122例如均是二氧化矽層，厚度例如分別約2000A與 1000A。爲了提高複晶矽層120的導電性，可將例如砷離 子植入到複晶矽層120中。之後，利用傳統的光罩製版和 蝕刻技術，在大致對應於汲極區16的上方依序蝕刻絕緣層 122、複晶矽層120、絕緣層118、複晶矽層116與絕緣層 102，直到複晶矽層1〇〇的表面爲止，以形成一開口 124。 請參照第6E圖，接著在開口 124中形成一實心筒狀的 複晶矽層126，其形成方式例如是以磊晶方式或以沈積後 再回蝕刻方式形成。之後利用傳統的光罩製版與蝕刻技 術’定義複晶矽層120、100，以界定出記億單元的儲存 電容器之儲存電極。之後利用濕式蝕刻法，並以蝕刻保護 層22爲蝕刻終點，將暴露出的二氧化矽層去除，亦即去除 絕緣層122、118、102與96。藉此步驟即完成動態隨機 存取記憶體的儲存電容器之儲存電極，其如圖所示係由類 樹幹狀的下複晶矽層1〇〇、類樹幹狀的上複晶矽層126、 一具有似“一”型剖面的類樹枝狀複晶矽層120以及一具有 似L形剖面的類樹枝狀複晶矽層U6所一起構成。類樹幹 狀的下複晶矽層1〇〇連接到DRAM的轉移電晶體之汲極區 16 ’且具有一似T形的剖面。類樹幹狀的上複晶矽層126 22 本紙張尺度適用中CNS) M規格（21〇><297公楚）- (請先閲讀背面之注意事項再填寫本頁) 丨装_ 訂 级 03 18TWF.DOC/002 A7 _ B7 五、發明説明（2丨） 係從類樹幹狀的下複晶矽層100的上表面，大致以垂直的 方向往上延伸出。類樹枝狀複晶矽層120係從類樹幹狀的 上複晶矽層126的外表面，大致以水平方向往四週延伸 出。類樹枝狀複晶矽層116則從類樹幹狀的上複晶矽層126 的外表面，先以約水平方向往外延伸一段距離後，再以約 垂直方向往下延伸出。 熟習此藝者應可瞭解，上述本發明各個較佳實施例的 構想特徵，除了可以單獨應用之外，亦可混合應用，而再 達成非常多種不同結構的儲存電極和儲存電容器，這些儲 存電極和儲存電容器的結構都應在本發明的保護範圍之 內。 應注意雖然在圖式中轉移電晶體的汲極均爲矽基底表 面的擴散區結構，然本發明並不限於此，任何適當的汲極 結構均可應用於本發明，例如溝槽式（trench )汲極即爲 一例。 再者，也應注意圖式中各構件部份的形狀、尺寸、和 延伸的角度，僅爲繪示方便所作的示意表示’其與實際情 況或有差異，故不應用以限制本發明。 經濟部中央標準局員工消費合作社印製 --------一—裝-- (請先閱讀背面之注意事項再填寫本頁) 雖然本發明已以若干較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 23 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）(CNS) Λ4 specification (210X 297mm) (Please read the precautions on the back before filling in this page) • Split. Printed TT3V8TWF.DOC / 002 1__B7 by the Central Consumer ’s Bureau of the Ministry of Economic Affairs. The description of the invention (ή) is 100 Α, and the thickness of the sacrificial polycrystalline silicon layer 106 is, for example, about 1000A. The insulating layer 104 and the sacrificial polycrystalline silicon layer 106 are structured as a stacked layer 104; 106, which has a notch 108, and the preferred position of the notch 108 corresponds approximately above the drain region 16. Please refer to FIG. 6B, and then form silicon dioxide sidewalls 110 on the sidewalls of the stacked layers 104; 106, respectively. In the preferred embodiment, the silicon dioxide sidewall spacer 110 can be formed by the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000 A; and then etching back. Thereafter, an insulating layer 112 'is deposited by CVD so that it substantially fills the space of the recess 108. The insulating layer 112 is, for example, a silicon nitride layer, and has a thickness of about 2000A, for example. Next, the insulating layer 112 is polished using a mechanochemical polishing technique until at least the portion above the stacked layer 104 is exposed. Please refer to FIG. 6C, and then use the stacked layer 104 and the insulating layer 112 as the etching mask layer, and remove the sand edge wall 110 by etching. After that, the stacked layer 104; 106 and the insulating layer 112 are still used as the etching mask layer, and the insulating layer 102 'is continuously etched but not etched to the surface of the polycrystalline silicon layer ι00. Then, the sacrificial polycrystalline silicon layer 106 is used as a masking layer to etch away the insulating layer n2 to form an opening 114. The depth of the opening 114 can be adjusted according to actual needs' as long as it is kept at a distance from the polycrystalline cutting layer 100. Next, a polycrystalline silicon layer n6 is deposited on the surface of the stacked layer 104; 106 and the insulating layer 102, with a thickness of, for example, about 1000 A to substantially fill the opening II4. In order to improve the conductivity of the polycrystalline silicon layer 116, for example, arsenic ions can be implanted into the polycrystalline silicon layer 116. After that, the polycrystalline silicon layer is polished by mechanochemical polishing technology until at least the portion above the insulating layer 104 is exposed to form a polycrystalline sand layer 116 as shown in the figure. (Please read the precautions on the back before filling in this page)-Installation _ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X: 297 public daughter) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 03 1 8TWF.DOC / 002 A7 ____B7_____ 5. Description of the invention (β) In this step, the sacrificial polycrystalline silicon layer 106 is removed. Please refer to FIG. 6D, and then using the polycrystalline silicon layer 116 and the insulating layer 102 as an etching protection layer, the stacked layer 104 is removed by a wet etching method; 106, that is, the remaining insulating layer 104 is removed. After that, an insulating layer 118, a polycrystalline silicon layer 120 and an insulating layer 122 are sequentially deposited by the CVD method, wherein the insulating layers 118 and 122 are, for example, silicon dioxide layers, and have a thickness of about 2000A and 1000A, respectively. In order to improve the conductivity of the polycrystalline silicon layer 120, for example, arsenic ions can be implanted into the polycrystalline silicon layer 120. After that, using conventional photomask patterning and etching techniques, the insulating layer 122, the polycrystalline silicon layer 120, the insulating layer 118, the polycrystalline silicon layer 116, and the insulating layer 102 are sequentially etched in sequence above the drain region 16. An opening 124 is formed up to the surface of the polycrystalline silicon layer 100. Please refer to FIG. 6E, and then form a solid cylindrical polycrystalline silicon layer 126 in the opening 124, for example, it is formed by epitaxial method or by etching back after deposition. Afterwards, the polysilicon layers 120, 100 are defined using traditional photomask patterning and etching techniques to define the storage electrodes of the billion-unit storage capacitor. After that, the wet etching method is used, and the etching protection layer 22 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layers 122, 118, 102 and 96 are removed. With this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed. As shown in the figure, the trunk-like lower polycrystalline silicon layer 100, the trunk-like upper polycrystalline silicon layer 126, a The dendrite-like polycrystalline silicon layer 120 having a “one” -like cross-section and a dendrite-like polycrystalline silicon layer U6 having an L-like cross-section are formed together. The trunk-like lower polycrystalline silicon layer 100 is connected to the drain region 16 'of the transfer transistor of the DRAM and has a T-shaped cross section. Trunk-like upper polycrystalline silicon layer 126 22 This paper size is suitable for CNS) M specifications (21〇 < 297 Gongchu)-(Please read the precautions on the back before filling this page) 丨 Installation_ Ordering 03 18TWF.DOC / 002 A7 _ B7 V. Description of the invention (2 丨) It extends from the upper surface of the trunk-like lower polycrystalline silicon layer 100 and extends upward in a substantially vertical direction. The dendritic polycrystalline silicon layer 120 extends from the outer surface of the trunk-like upper polycrystalline silicon layer 126 and extends approximately horizontally. The dendritic polycrystalline silicon layer 116 extends from the outer surface of the trunk-like upper polycrystalline silicon layer 126 outward in a horizontal direction, and then extends downward in a vertical direction. Those skilled in the art should understand that the above-mentioned conceptual features of the preferred embodiments of the present invention can be used in addition to separate applications, and can also be used in combination to achieve a very wide variety of storage electrodes and storage capacitors with different structures. The structure of the storage capacitor should be within the protection scope of the present invention. It should be noted that although the drains of the transfer transistors in the drawings are all diffused region structures on the surface of the silicon substrate, the invention is not limited thereto, and any suitable drain structure can be applied to the invention, such as trench ) Jiji is an example. In addition, the shapes, sizes, and extension angles of each component part in the drawings should also be noted. The illustrations are for convenience of illustration only. They may differ from the actual situation, so they should not be used to limit the present invention. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs -------- One-Pack-- (please read the precautions on the back and then fill out this page) Although the present invention has been disclosed as above with several preferred embodiments, It is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications without departing from the spirit and scope of the present invention, so the scope of protection of the present invention should be defined as the scope of the attached patent application Whichever prevails. 23 This paper scale is applicable to China National Standard (CNS) A4 (210X 297mm)