H8&3Q〇 c/002 A7 B7 五、發明説明（I ) 本發明是有關於一種具有電容器的半導體記憶體元 件（Semiconductor Memory Device )，且特別是有關於一 種動態隨機存取記憶體（DynamicRand〇mAccessMemory; DRAM )的一記憶單元（Memory Cell )結構，其包含一 轉移電晶體（Transfer Transistor )和一樹型（tree-tyPe ) 儲存電容器。 第1圖是一 DRAM元件的一記憶單元之電路示意圖。 如圖所示，一個記憶單元是由一轉移電晶體T和一儲存電 容器C組成。轉移電晶體T的源極係連接到一對應的位元 線BL，汲極連接到儲存電容器C的一儲存電極6 ( storage electrode )，而閘極則連接到一對應的字元線WL。儲存 電容器C的一相對電極8 ( opposed electrode )係連接到 一固定電壓源，而在儲存電極6和相對電極8之間則設置 一介電膜層7。 在傳統DRAM的儲存電容量少於1M ( mega=百萬） 位元時，於積體電路製程中，主要是利用二度空間的電容 器來實現，亦即泛稱的平坦型電容器（planar type capacitor )。一平坦型電容器需佔用半導體基底的一相當 大的面積來儲存電荷，故並不適合應用於高度的積集化。 高度積集化的DRAM，例如大於4M位元的儲存電容量者， 需要利用三度空間的電容器來實現，例如所謂的堆疊型 (stacked type )或溝槽型（trench type )電容器。 與平坦型電容器比較，堆疊型或溝槽型電容器可以在 記憶單元的尺寸已進一步縮小的情況下，仍能獲得相當大 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） F.DOC/002 A7 B7 五、發明説明（工） 的電容量。雖然如此，當記憶體元件再進入更高度的積集 化時，例如具有64M位元容量的DRAM，單純的三度空間 電容器結構已不再華用。H8 & 3Q〇c / 002 A7 B7 V. Description of the invention (I) The present invention relates to a semiconductor memory device (Semiconductor Memory Device) with a capacitor, and in particular to a dynamic random access memory (Dynamic Random). mAccessMemory; DRAM) a memory cell (Memory Cell) structure, which includes a transfer transistor (Transfer Transistor) and a tree-type (tree-tyPe) storage capacitor. Figure 1 is a schematic circuit diagram of a memory cell of a DRAM device. As shown in the figure, a memory cell is composed of a transfer transistor T and a storage capacitor C. The source of the transfer transistor T is connected to a corresponding bit line BL, the drain is connected to a storage electrode 6 (storage electrode) of the storage capacitor C, and the gate is connected to a corresponding word line WL. An opposed electrode 8 of the storage capacitor C is connected to a fixed voltage source, and a dielectric film layer 7 is provided between the storage electrode 6 and the opposite electrode 8. When the storage capacity of the traditional DRAM is less than 1M (mega = million) bits, in the integrated circuit manufacturing process, it is mainly realized by using a capacitor of a two-dimensional space, which is generally known as a planar type capacitor. . A flat capacitor requires a considerable area of the semiconductor substrate to store charge, so it is not suitable for high accumulation. Highly integrated DRAMs, such as those with a storage capacity of more than 4M bits, need to be implemented with three-dimensional capacitors, such as so-called stacked type or trench type capacitors. Compared with flat capacitors, stacked or trench capacitors can still obtain a considerable size when the size of the memory cell has been further reduced. 3 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) F .DOC / 002 A7 B7 Fifth, the electric capacity of invention description (work). Nonetheless, when memory devices enter a higher degree of integration, such as DRAM with 64M bit capacity, the simple three-dimensional capacitor structure is no longer used.
解決之道之一是利用所謂的鰭型（fin type )堆疊電容 器。鰭型堆疊電容器之相關技術可參考Ema等人的論文 “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMsm, International Electron Devices Meeting, pp. 592-595，Dec. 1988。鰭型堆疊電容器主要是其電極和介電膜層 係由複數個堆疊層，延伸成一水平鰭狀結構，以便增加電 極的表面積。DRAM的鰭型堆疊電容器的相關美國專利 可以參考第 5,071,783 號、第 5，126,810 號、第 5，196,365 號、以及第5,206,787號。 另一種解決之道是利用所謂的筒型（cylindrical type ) 堆疊電容器。筒型堆疊電容器之相關技術可參考Wakamiya 等人的論文 “Novel Stacked Capacitor Cell for 64-Mb DRAM”，1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70。筒型堆疊電容器主要是其電 極和介電膜層係延伸成一垂直筒狀結構，以便增加電極的 表面積。DRAM的筒型堆疊電容器的相關美國專利可以 參考第5,077,688號。 隨著積集度的不斷增加，DRAM記憶單元的尺寸仍會 再縮小。如熟習此藝者所知，記憶單元尺寸縮小，儲存電 容器的電容値也會減少。電容値的減少將導致因α射線入 射所引起的軟錯誤（soft error )機會增加。因此，此藝者 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ---------ί '裝— (I先閲讀背面之注意事項再填寫本頁) 訂One of the solutions is to use so-called fin type stacked capacitors. For the related technology of fin-type stacked capacitors, please refer to the paper “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMsm, International Electron Devices Meeting, pp. 592-595, Dec. 1988” by Ema et al. The dielectric film layer is composed of a plurality of stacked layers, extending into a horizontal fin structure in order to increase the surface area of the electrode. For DRAM type fin-type stacked capacitors, related US patents can refer to No. 5,071,783, No. 5,126,810, No. No. 196,365, and No. 5,206,787. Another solution is to use the so-called cylindrical type (stack type capacitor). The related technology of the cylindrical type stack capacitor can refer to the paper "Novel Stacked Capacitor Cell for 64-Mb DRAM" by Wakamiya et al. ", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. Cylindrical stacked capacitors mainly consist of electrodes and dielectric film layers extending into a vertical cylindrical structure in order to increase the surface area of the electrodes. DRAM cylindrical stack Related US patents for capacitors can refer to No. 5,077,688. With the degree of accumulation With the increase of the break, the size of the DRAM memory cell will still shrink again. As is known to those skilled in the art, the reduction in the size of the memory cell will reduce the capacitance value of the storage capacitor. The reduction in the capacitance value will result in soft errors caused by the incidence of alpha rays (Soft error) opportunities increase. Therefore, this artist's 4 paper scales are applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) --------- ί '装 — (I read the back of the first Matters needing attention before filling this page)
A 經濟部中央標隼局貝工消費合作社印裝 經濟部中央標準局員工消費合作杜印製 3128&S .DOC/002 A7 B7 五、發明说明（3 ) 仍不斷在尋找新的儲存電容器結構及其製造方法，希望在 儲存電容器所佔的平面尺寸被縮小的情況，仍能維持所要 的電容値。 緣此，本發明的一主要目的就是在提供一種具有電容 器的半導體記憶體元件，其電容器具有一樹狀結構，以增 加電容器的儲存電極之表面積。 依照本發明之一較佳實施例，提供一種具有電容器的 半導體記憶體元件，該元件包括：一基底；一轉移電晶體， 形成在基底上，並包括汲極和源極區；以及一儲存電容器， 電性耦接到轉移電晶體的汲極和源極區之一上。其中，儲 存電容器又包括： 一類樹幹狀導電層，具有一底部，電性耦接到轉移電 晶體的汲極和源極區之一上，類樹幹狀導電層又具有一向 上延伸部，以一大致向上的方向，從底部延伸出； 至少一第一類樹枝狀導電層，具有一似L形的剖面， 第一類樹枝狀導電層的一末端連接在類樹幹狀導電層的 內表面上’類樹幹狀導電層和第一類樹枝狀導電層構成儲 存電容器的一儲存電極； 一介電層，形成在類樹幹狀導電層和第一類樹枝狀導 電層暴露出的表面上；以及 一上導電層，形成在介電層上，以構成儲存電容器的 一相對電極》 依照本發明之一特點，類樹幹狀導電層包括一下樹幹 部與一上樹幹部。其中，下樹幹部電性耦接到轉移電晶體 5 本紙張尺度適用中國國家榡準（CNS ) A4規格（21〇 X 297公釐） {請先閲讀背面之注意事項再填寫本頁) -裝· 訂 053 ITWF.DOC/002 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（屮） 的汲極和源極區之一上，其剖面可以爲τ型，也可以爲u 型；而上樹幹部則大致以垂直方向自下樹幹部的周邊往上 延伸出。 依照本發明之另一較佳實施例，提供一種具有電容器 的半導體記憶體元件，該元件包括：一基底；一轉移電晶 體，形成在基底上，並包括汲極和源極區；以及一儲存電 容器，電性耦接到轉移電晶體的汲極和源極區之一上。 儲存電容器又包括： 一類樹幹狀導電層，具有一底部，電性耦接到轉移電 晶體的汲極和源極區之一上，類樹幹狀導電層又具有一向 上延伸部，以一大致向上的方向，從底部延伸出； 至少一第一類樹枝狀導電層，包括一第一延伸段和一 第二延伸段’第一延伸段的一末端連接在類樹幹狀導電層 的內表面上，大致以水平方向往內延伸出，第二延伸段大 致以垂直方向，從第一延伸段的另一末端往下延伸出，類 樹幹狀導電層和第一類樹枝狀導電層構成儲存電容器的 一儲存電極； 一介電層，形成在類樹幹狀導電層和第一類樹枝狀導 電層暴露出的表面上；以及 一上導電層’形成在介電層上，以構成儲存電容器的 一相對電極。 依照本發明之又一較佳實施例，本發明之類樹枝狀導 電層更包括一第二類樹枝狀導電層，其具有一似“一”型的 剖面’且大致以水平的方向從類樹幹狀導電層的內表面往 請- 先 閲 讀 背 之 注 意 事 項 再 養 裝 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210χ 297公缝） A7 B7 312830 0 5 3 1 TW F. 五、發明説明（^) 內延伸出。 依照本發明之又一特點，第一類樹枝狀導電層的第一 延伸段大致係以水平方向，自上樹幹部的四週內表面由外 往內延伸出。 依照本發明之又一較佳實施例，本發明之第一類樹枝 狀導電層的第一延伸段大致係以水平方向，從上樹幹部一 側的內表面往另一內側延伸出。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉若干較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖是一 dram元件的一記憶單元之電路示意圖。 第2A至21圖係一系列剖面圖，用以解釋本發明的一 種半導體記憶元件製造方法之第一較佳實施例，以及本發 明的一種半導體記憶元件之第一較佳實施例。 第3A至3F圖係一系列剖面圖，用以解釋本發明的一 種半導體記憶元件製造方法之第二較佳實施例，以及本發 明的一種半導體記憶元件之第二較佳實施例。 第4A至4E圖係一系列剖面圖，用以解釋本發明的一 、 種半導體記憶元件製造方法之第三較佳實施例，以及本發 明的一種半導體記憶元件之第三較佳實施例。 第5A至5F圖係一系列剖面圖，用以解釋本發明的一 種半導體記憶元件製造方法之第四較佳實施例，以及本發 明的一種半導體記憶元件之第四較佳實施例。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 053 ITWF.DOC/002 A7 B7 經濟部中央標準局員工消費合作社印聚 五 '發明説明（ί7 ) 實施例 首先請參照第2A至21圖，以詳述本發明的一種具有 樹型儲存電容器的半導體記憶元件之第一較佳實施例。A Printed by the Central Standard Falcon Bureau of the Ministry of Economic Affairs, Beigong Consumer Cooperative, and printed by the Central Bureau of Economic Affairs of the Ministry of Economic Affairs. Printed 3128 & S .DOC / 002 A7 B7 V. Invention description (3) Still looking for new storage capacitor structures and The manufacturing method is expected to maintain the desired capacitance value when the plane size occupied by the storage capacitor is reduced. Therefore, a main object of the present invention is to provide a semiconductor memory device having a capacitor whose capacitor has a tree structure to increase the surface area of the storage electrode of the capacitor. According to a preferred embodiment of the present invention, a semiconductor memory device having a capacitor is provided. The device includes: a substrate; a transfer transistor formed on the substrate and including a drain and a source region; and a storage capacitor , Electrically coupled to one of the drain and source regions of the transfer transistor. The storage capacitor further includes: a type of trunk-like conductive layer with a bottom, electrically coupled to one of the drain and source regions of the transfer transistor, and a trunk-like conductive layer with an upward extension to In a generally upward direction, extending from the bottom; at least one first-type dendritic conductive layer having an L-shaped cross-section, one end of the first-type dendritic conductive layer is connected to the inner surface of the trunk-like conductive layer ' The trunk-like conductive layer and the first-type dendritic conductive layer constitute a storage electrode of the storage capacitor; a dielectric layer formed on the exposed surface of the trunk-like conductive layer and the first-type dendritic conductive layer; and A conductive layer is formed on the dielectric layer to form a counter electrode of the storage capacitor. According to one feature of the present invention, the trunk-like conductive layer includes a lower trunk portion and an upper trunk portion. Among them, the lower trunk is electrically coupled to the transfer transistor. The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) (please read the precautions on the back before filling this page)- · Order 053 ITWF.DOC / 002 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. One of the drain and source regions of the invention description (屮), the cross-section can be τ-type or u-type ; The upper trunk extends from the periphery of the lower trunk upward in a vertical direction. According to another preferred embodiment of the present invention, a semiconductor memory device having a capacitor is provided. The device includes: a substrate; a transfer transistor formed on the substrate and including drain and source regions; and a storage The capacitor is electrically coupled to one of the drain and source regions of the transfer transistor. The storage capacitor further includes: a type of trunk-like conductive layer with a bottom, electrically coupled to one of the drain and source regions of the transfer transistor, and a trunk-like conductive layer with an upward extension, generally upward Direction, extending from the bottom; at least one first type dendritic conductive layer, including a first extension and a second extension 'one end of the first extension is connected to the inner surface of the trunk-like conductive layer, Extends approximately horizontally inward, and the second extension extends approximately vertically from the other end of the first extension, the trunk-like conductive layer and the first type of dendritic conductive layer constitute a part of the storage capacitor Storage electrode; a dielectric layer formed on the exposed surface of the trunk-like conductive layer and the first type of dendritic conductive layer; and an upper conductive layer 'formed on the dielectric layer to form a counter electrode of the storage capacitor . According to yet another preferred embodiment of the present invention, the dendritic conductive layer of the present invention further includes a second type of dendritic conductive layer, which has a “1” -like cross-section and is approximately horizontal from the trunk The inner surface of the conductive layer-please read the precautions before back binding. The size of the bound paper is applicable to the Chinese National Standard (CNS) A4 specification (210χ 297 male seam) A7 B7 312830 0 5 3 1 TW F. V. Description of the invention (^) Extends inside. According to still another feature of the invention, the first extension of the first type of dendritic conductive layer extends approximately horizontally, extending from the inner surface around the upper trunk portion from the outside to the inside. According to yet another preferred embodiment of the present invention, the first extension of the first type of dendritic conductive layer of the present invention extends substantially horizontally from the inner surface on one side of the upper trunk portion to the other inner side. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are described below in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: Figure 1 It is a circuit diagram of a memory unit of a dram device. 2A to 21 are a series of cross-sectional views for explaining a first preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a first preferred embodiment of a semiconductor memory device of the present invention. Figures 3A to 3F are a series of cross-sectional views for explaining a second preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a second preferred embodiment of a semiconductor memory device of the present invention. FIGS. 4A to 4E are a series of cross-sectional views for explaining a third preferred embodiment of a semiconductor memory device manufacturing method of the present invention, and a third preferred embodiment of a semiconductor memory device of the present invention. Figures 5A to 5F are a series of cross-sectional views for explaining a fourth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a fourth preferred embodiment of a semiconductor memory device of the present invention. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 053 ITWF.DOC / 002 A7 B7 The Ministry of Economy Central Standards Bureau Employee Consumer Cooperative Printed Poly 5 'Invention Description (ί7) For the examples, please refer to 2A to FIG. 21 is a detailed description of a first preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention.
請參照第2A圖，首先將一矽基底10的表面進行熱氧 化製程，例如以矽的局部氧化（LOCOS )技術來達成， 因而形成場區氧化層12 ，其厚度例如約3000A (angstroms )。接著，再將矽基底10進行熱氧化製程， 以形成一閘極氧化層14，其厚度例如約150A。然後，利 用一 CVD (化學氣相沈積）或LPCVD (低壓CVD )法， 在矽基底10的整個表面上沈積一複晶矽層，其厚度例如約 2000A。爲了提高複晶矽層的導電性，可將磷離子植入到 複晶砂層中。較佳是可再沈積一耐火金屬（refractory metal )層，然後施行退火（anneal )步驟，即形成金屬 複晶矽化合物層（polycide )，以更提高其導電性。該耐 火金屬可例如爲鎢（Tungsten )，沈積厚度例如約2000A。 之後’利用傳統的光罩製版（photolithography )和触刻 技術定義（pattern )金屬複晶矽化合物層，因而形成如第 2A圖所示的閘極（或稱字元線）WL1至WL4。接著，例 如以砷離子植入到矽基底10中，以形成汲極區16a和 16b、以及源極區18a和18b。在此步驟中，字元線WL1 至WL4係當作罩幕層，而離子植入的劑量例如約丨X 10i5 atoms/cm2，能量貝[J 約 70KeV。 請參照第2B圖，接著以CVD法沈積一絕緣層20，其 例如爲BPSG (硼磷矽玻璃），厚度約7000A。然後，再 8 (請先閱讀背面之注意事項再填寫本頁) 丨裝·Referring to FIG. 2A, first, a surface of a silicon substrate 10 is subjected to a thermal oxidation process, for example, by local oxidation of silicon (LOCOS) technology, thereby forming a field oxide layer 12 with a thickness of about 3000 A (angstroms), for example. Then, the silicon substrate 10 is subjected to a thermal oxidation process to form a gate oxide layer 14 having a thickness of, for example, about 150A. Then, using a CVD (chemical vapor deposition) or LPCVD (low pressure CVD) method, a polycrystalline silicon layer is deposited on the entire surface of the silicon substrate 10, with a thickness of, for example, about 2000 Å. In order to improve the conductivity of the polycrystalline silicon layer, phosphorus ions can be implanted into the polycrystalline sand layer. Preferably, a refractory metal layer may be deposited, and then an annealing step is performed to form a metal polycide layer to further increase its conductivity. The refractory metal may be, for example, tungsten (Tungsten), and the deposited thickness is, for example, about 2000A. Afterwards, the metal polycrystalline silicon compound layer is patterned using traditional photolithography and lithography techniques, thus forming gates (or word lines) WL1 to WL4 as shown in FIG. 2A. Next, for example, arsenic ions are implanted into the silicon substrate 10 to form drain regions 16a and 16b and source regions 18a and 18b. In this step, the word lines WL1 to WL4 are used as the mask layer, and the dose of ion implantation is, for example, about 10 × 10 5 atoms / cm 2, and the energy is [J about 70KeV. Please refer to FIG. 2B, and then deposit an insulating layer 20 by CVD, such as BPSG (borophosphosilicate glass), with a thickness of about 7000A. Then, 8 again (please read the precautions on the back before filling this page)
,1T 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210Χ297公釐） 053 ITWF.DOC/002 A7 B7 __ 五、發明説明（η ) 以 CVD 法沈積一飩刻保護層（etching protection layer ) 22，其例如爲砂氮化物層（silicon nitride )，厚度約 1000A。之後，利用傳統的光罩製版和蝕刻技術，依序蝕 刻蝕刻保護層22、絕緣層20、和閘極氧化層14，以形成 儲存電極接觸窗（storage electrode contact holes ) 24a 和 24b’其係分別由蝕刻保護層22的上表面延伸到汲極區16a 和i6b的表面。接著，以cvd法在蝕刻保護層22的表面 沈積〜複晶矽層26。爲了提高複晶矽層26的導電性，可 將例如砷離子植入到複晶矽層26中。如圖所示，複晶矽層 26塡滿儲存電極接觸窗24a; 24b，且覆蓋住蝕刻保護層22 的表面。之後，在複晶矽層26表面沈積一厚的絕緣層28， 其例如爲二氧化矽層，厚度例如約7000A。 請參照第2C圖，接著以CVD法在絕緣層28表面依序 沈積〜絕緣層與一犧牲複晶矽層，再利用傳統的光罩製版 和@刻技術定義絕緣層與犧牲複晶矽層，因而形成如圖所 示之絕緣層3〇a; 30b與犧牲複晶矽層3〗a; 32b。其中，絕 緣層3〇a; 30b例如爲矽氮化物層，厚度例如約是1〇〇〇a， 而犧牲複晶矽層32a; 32b之厚度例如約是1000A。絕緣層 3 〇a與犧牲複晶砂層32a結構成一堆疊層30a; 32a，其爲實 心筒狀’水平剖面可爲圓形、矩形或是其他形狀。堆疊層 32a的較佳位置大致係對應於汲極區1以的上方；而 絕緣層30b與犧牲複晶矽層32b結構成另一堆疊層30b; 32b ’其亦爲實心筒狀，水平剖面可爲圓形、矩形或是其 他形狀。堆疊層30b; 32b的較佳位置大致係對應於汲極區 _ 9 本紙張尺度it用中'( eNS } ( 2ι()χ 297以} (請先閲讀背面之注意事項再填寫本頁) 丨裝· .1Τ 經濟部中央標準局員工消費合作社印製 DOC/002 A7 DOC/002 A7 經濟部中央標準局貝工消費合作社印製 B7___ 五、發明説明（S ) 16b的上方。 請參照第2D圖，接著分別在堆疊層30a; 32a和30b; 32b 的側壁（sidewalls )上形成二氧化矽邊牆（spacers ) 34a 和34b。在本較佳實施例中，二氧化矽邊牆34a和34b可 以以下列步驟形成：沈積一二氧化矽層，其厚度例如約 1000A ;再回蝕刻（etchback )。之後，以CVD法沈積一 絕緣層36，其例如爲矽氮化物層，厚度例如約2000A。再 來’利用機械化學式硏磨（chemical mechanical polish; CMP )技術硏磨絕緣層36，至少直到堆疊層30a; 32a和 30b; 32b上方的部份露出爲止。 請參照第2E圖，接著以堆疊層30a; 32a、30b; 32b和 絕緣層36爲蝕刻罩幕，鈾刻去除二氧化矽邊牆34a; 34b 以及其下的部份絕緣層28。然後以犧牲複晶矽層32a; 32b 爲蝕刻罩幕，蝕刻去除絕緣層36，形成開口 38a和38b。 開口 38a和38b的深度可依實際需求加以調整’只要與複 晶矽層26表面保持一段距離即可。 請參照第2F圖，接著在堆疊層3〇a; 、30b; 32b和 絕緣層28的表面沈積一複晶矽層40,厚度例如約ΙΟΟΟΑ， 以塡滿開口 38a和38b。爲了提高複晶矽層4〇的導電性， 可將例如砷離子植入到複晶矽層40中。之後’利用機械化 學式硏磨技術硏磨複晶砂層40，至少直到絕緣層30a; 30b 上方的部份露出爲止，形成如圖所示的複晶矽層40。在此 步驟中，犧牲複晶矽層32a; 32b會被去除。 請參照第2G圖，接著以複晶矽層4〇與絕緣層28爲蝕 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210Χ297公釐） ---------ί 袭------，玎------^ ^ (請·先閲讀背面之注意事項再填寫本頁) 053 1TWF.DOC/002 A7 053 1TWF.DOC/002 A7 經濟部中央標準局員工消費合作社印製 ______B7 五、發明説明（1 ) 刻保護層，利用濕式蝕刻法去除絕緣層30a; 30b。之後以 CVD法沈積一絕緣層42，其例如是二氧化砂層，厚度例 如約2000A。再來利用傳統的光罩製版與餓刻技術，依序 倉虫刻絕緣層42、複晶砂層40、絕緣層28和複晶砂層26， 形成一開口 44 ’以界定出各記億單元的儲存電容器之儲存 電極。亦即藉此步驟將複晶矽層40和％切割成若干區段 40a; 40b 和 26a; 26b。 請參照第2H圖，接著在開口 44的側壁上形成複晶矽 邊牆46a和46b。在本較佳實施例中，複晶砂邊牆46a; 46b 可以以下列步驟形成：沈積一複晶砂層，其厚度例如約 ΙΟΟΟΑ，再回飽刻。爲了提局複晶砂層46a; 46b的導電性， 可將例如砷離子植入到複晶矽層46a; 4615中。之後利用濕 式蝕刻法，並以蝕刻保護層22爲蝕刻終點，將暴露出的二 氧化矽層去除，亦即去除絕緣層42和28。藉此步驟即完 成動態隨機存取記憶體的儲存電容器之儲存電極，其如圖 所示係由類樹幹狀的下複晶矽層26a; 26b、類樹幹狀的上 複晶砂層46a; 46b、以及一具有似L形剖面的類樹枝狀複 晶矽層40a; 40b所一起構成。類樹幹狀的下複晶矽層26a; 26b連接到DRAM的轉移電晶體之汲極區16a; 10b ’且具 有一似T形的剖面。類樹幹狀的上複晶矽層46a; 46b的下 端連接於類樹幹狀的下複晶矽層26a; 26b的週邊’且大致 往上延伸出。類樹枝狀複晶矽層40a; 40b從類樹幹狀的上 複晶矽層46a; 46b的內表面，先以約水平方向往內延伸一 段距離後，再以約垂直方向往下延伸出。由於本發明的儲 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 ·" 312830 053 ITWF.DOC/002 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（w) 存電極之形狀非常特殊，故在本說明書中乃以“樹型儲存電 極”稱之’且因而製成之電容器則稱爲“樹型儲存電容器”。 請參照第21圖，接著分別在儲存電極26a，40a，46a; 26b， 40b; 46b裸露的表面上分別形成一介電膜層48a; 48b。介 電膜層48a; 48b例如可爲二氧化矽層、矽氮化物層的NO (砂氮化物/二氧化砂）結構、ΟΝΟ (二氧化矽/砂氮化物 /二氧化矽）結構、或任何類似者。然後，在介電膜層48a 和48b的表面上’形成由複晶矽製成的相對電極50。相對 電極的製程可由下列步驟達成：以CVD法沈積一複晶矽 層，其厚度例如爲1000A ;再摻入例如N型雜質，以提高 其導電性；最後以傳統光罩製版和蝕刻技術定義複晶矽 層，完成DRAM各記憶單元的儲存電容器。 雖然第21圖未顯示，然熟習此藝者應瞭解，第21圖的 結構可依傳統製程技術製作位元線、焊墊（bonding pad )、互連導線（interconnection )、隔絕保護層 (passivation )、以及包裝等等，以完成DRAM積體電路。 由於這些製程非關本發明之特徵，故於此不多作贅述。 在第一較佳實施例中，儲存電極只具有一層似L形剖 面的類樹枝狀電極層。然而，本發明並不限於此，儲存電 極似L形剖面的類樹枝狀電極層之層數可爲二層、三層、 或更多。下一個較佳實施例即將描述具有二層似L形剖面 的類樹枝狀電極層的儲存電極。 接著將參照第3A至3E圖，詳述本發明的一種具有樹 型儲存電容器的半導體記憶元件之第二較佳實施例，半導 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） ----------裝------訂------^知 (I先閲讀背面之注意事項再填寫本頁) 053 1 TWF.DOC/002 A7 B7 五、發明説明（丨I ) 體記憶元件的此一較佳實施例，係由本發明的一種半導體 記憶元件製造方法之第二較佳實施例所製造的。 本較佳實施例係以第2F圖所示的較佳實施例之結構 爲基礎，再以不同的製程製作不同結構的DRAM儲存電 極。在第3A至；3E圖中’與第2f圖相似的部份係以相同 的編號標示。 請參照第2F和3A圖’接著以複晶矽層40與絕緣層28 爲蝕刻保護層，利用濕式蝕刻法去除絕緣層30a; 30b。之 後以CVD法沈積一絕緣層52，其例如爲二氧化矽層，厚 度約2000A。再來以CVD法在絕緣層52表面依序沈積一 絕緣層與一犧牲複晶矽層，再利用傳統的光罩製版和蝕刻 技術定義絕緣層與犧牲複晶矽層，因而形成如圖所示之絕 緣層54a; 54b與犧牲複晶矽層56a; 56b。其中，絕緣層54a; 54b例如爲矽氮化物層，厚度例如約是1000A，而犧牲複 晶矽層56a; 56b之厚度例如約是1000A。絕緣層54a與犧 牲複晶砂層56a結構成一堆疊層54a;56a’其爲實心筒狀’ 水平剖面可爲圓形、矩形或是其他形狀。堆疊層54a; 56a 較圖2C中的堆疊層30a; 32a小，其較佳位置大致係對應於 汲極區16a的上方；而絕緣層54b與犧牲複晶矽層56b結 構成另一堆疊層54b; 56b，其亦爲實心筒狀’水平剖面可 爲圓形、矩形或是其他形狀。堆疊層54b; 56b較圖2C中 的堆疊層30b; 32b小，其較佳位置大致係對應於汲極區16b 的上方。 請參照第3B圖，接著分別在堆疊層54a; 56a和Mb; 56b ---------{丨裝------訂-----i 線 (^先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 053 1TWF.DOC/002 A7 B7 五、發明説明（丨2·) 的側壁上形成二氧化矽邊牆58a和58b。在本較佳實施例 中，二氧化矽邊牆58a和58b可以以下列步驟形成：沈積 一二氧化矽層，其厚度例如約1000A ;再回蝕刻。之後， 以CVD法沈積一絕緣層60，其例如爲矽氮化物層，厚度 例如約2000A。再來，利用機械化學式硏磨技術硏磨絕緣 層60，至少直到堆疊層54a; 56a和54b; 56b上方的部份露 出爲止。 請參照第3C圖，接著以堆疊層54a; 56a、54b; 56b和 絕緣層60爲蝕刻罩幕，蝕刻去除二氧化矽邊牆58a; 58b 以及其下方的絕緣層52與部份絕緣層28。然後以犧牲複 晶矽層56a; 56b爲蝕刻罩幕，蝕刻去除絕緣層60，形成開 口 62a和62b。開口 62a和62b的深度可依實際需求加以 調整，只要與複晶矽層26表面保持一段距離即可。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 請參照第3D圖，接著在堆疊層54a; 56a、54b; 56b和 絕緣層52的表面沈積一複晶矽層64,厚度例如約1000A， 以塡滿開口 62a和62b。爲了提高複晶矽層64的導電性， 可將例如砷離子植入到複晶矽層64中。之後，利用機械化 學式硏磨技術硏磨複晶矽層64，至少直到絕緣層54a; 54b 上方的部份露出爲止，形成如圖所示的複晶矽層64。在此 步驟中，犧牲複晶矽層56a; 56b會被去除。接著以複晶矽 層64與絕緣層52爲蝕刻保護層，利用濕式蝕刻法去除絕 緣層 54a; 54b。 請參照第3E圖，接著以CVD法沈積一絕緣層66，其 例如是二氧化矽層，厚度例如約2000A。再來利用傳統的 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨OX297公釐） 31288t^ F.DOC/002 A7 _ B7 "X、發明説明（丨》） 光罩製版與蝕刻技術，依序蝕刻絕緣層66、複晶砂層64、 絕緣層52、複晶矽層40、絕緣層28和複晶矽層26，形 成一開口 68，以界定出各記憶單兀的儲存電容器之儲存電 極。亦即藉此步驟將複晶砍層64、40和26切割成若干區 段 64a; 64b、40a; 40b 和 26a; 26b。 經濟部中央標準局員工消費合作社印装 (請f閲讀背面之注意事項再填寫本頁) 請參照第3F圖，接著在開口 68的側壁上形成複晶砂 邊牆7〇a和7〇b。在本較佳實施例中，複晶矽邊牆7〇a; 7〇b 可以以下列步驟形成.沈積一複晶砂層，其厚度例如約 1000A;再回蝕刻。爲了提高複晶矽層7〇a; 7〇b的導電性， 可將例如砷離子植入到複晶矽層70a; 7〇b’中。之後利用濕 式餓刻法，並以餓刻保護層22爲触刻終點，將暴露出的一 氧化矽層去除，亦即去除絕緣層66、S2和28。藉此步驟 即完成動態隨機存取記憶體的儲存電容器之儲存電極，其 如圖所不係由類樹幹狀的下複晶砂層26a; 26b、類樹幹狀 的上複晶矽層70a; 70b、以及兩層具有似L形剖面的類樹 枝狀複晶矽層64a; 64b和40a; 40b所—起構成。類樹幹狀 的下複晶矽層26a; 26b連接到DRAM的轉移電晶體之汲極 區16a; 16b ’且具有一似T形的剖面。類樹幹狀的上複晶 砂層70a; 70b的下端連接於類樹幹狀的下複晶矽層26a; 26b的週邊，且大致以垂直方向往上延伸出。類樹枝狀複 晶矽層64a; 64b和40a; 40b大致平行，且分別從類樹幹狀 的上複晶矽層70a; 70b的內表面，先以約水平方向往內延 伸一段距離後，再以約垂直方向往下延伸出。接下來之後 續製程因無異於傳統製程，故在此不再贅述。如果要得到 _____ 15 本紙張尺度4用中家縣（CNS) A4規格（21()>< 297公董） A7 053 1TWF.DOC/002 _______B7___ 五、發明説明（丨y ) 更多層的類樹枝狀電極層，只要依照本較佳實施例中之描 述（圖3A至3D)，多次重複堆疊層的製作就可滿足所需。 上述第一、第二較佳實施例中之類樹枝狀電極層從剖 面觀之，均具有兩支似L型的樹枝，然而，本發明並不限 於此，類樹枝狀電極層似L形的樹枝可以只有一支’下一 個較佳實施例即將描述具有單支似L形剖面的類樹枝狀電 極層的儲存電極。又，在上述第一、第二較佳實施例中之 類樹幹狀的下複晶矽層均爲實心構件，且具有一似T形的 剖面，然而，本發明亦不限於此，類樹幹狀的下複晶矽層 可具有一中空結構的部份，以增加儲存電極的表面積。下 一個較佳實施例即將描述類樹幹狀的下複晶矽層具有一 似U形的剖面，以更增加儲存電極的表面積的結構及其作 法。 接著將參照第4A至4E圖，詳述本發明的一種具有樹 型儲存電容器的半導體記憶元件之第三較佳實施例，半導 體記憶元件的此一較佳實施例，係由本發明的一種半導體 記憶元件製造方法之第三較佳實施例所製造的。 本較佳實施例係以第2A圖所示的較佳實施例之結構 爲基礎，再以不同的製程製作不同結構的DRAM儲存電 極。在第4A至4E圖中，與第2A圖相似的部份係以相同 的編號標示。 請參照第2A圖與第4A圖，接著以CVD法沈積一平坦 化的絕緣層72，其例如爲BPSG，厚度例如約7000A。然 後，再以CVD法沈積一蝕刻保護層74，其例如爲矽氮化 16 ---------{-裝 J-----訂------ (請'先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 本紙張尺度適用中國國家橾隼（CNS ) Λ4規格（210X297公釐） 經濟部中夬標準局貝工消費合作社印製 05 3 1TWF.DOC/002 A ^ A7 ___ _B7 五、發明説明（丨.（） 〜 物層，厚度例如約1000A。之後，利用傳統的光罩製版和 蝕刻技術’依序蝕刻蝕刻保護層74、平坦化絕緣層72、 和閘極氧化層14 ’以形成儲存電極接觸窗76a和76b，其 係分別由蝕刻保護層74的上表面延伸到汲極區16a和l6b 的表面。接著，沈積一複晶矽層78。如圖所示，複晶矽層 78覆蓋蝕刻保護層74的表面、以及儲存電極接觸窗76a 和76b的內壁表面，但未塡滿儲存電極接觸窗76&和761)， 因而使複晶矽層78具有一似U形剖面的中空結構部份。 爲了提闻複晶矽層78的導電性，可將例如砷離子植入到複 晶砂層78中。之後，在複晶矽層78表面沈積一厚的絕緣 層80 ’其例如爲二氧化矽層，厚度例如約7〇〇〇a。接著以 CVD法在絕緣層80表面依序沈積一絕緣層與一犧牲複晶 砂層’再利用傳統的光罩製版和蝕刻技術定義絕緣層與犧 牲複晶矽層’因而形成如圖所示之絕緣層82a; 82b與犧牲 複晶砂層84a; 84b。其中，絕緣層82a; 82b例如爲矽氮化 物層’厚度例如約是1000A，而犧牲複晶矽層84a; 84b之 厚度例如約是1000A。絕緣層82a與犧牲複晶矽層84a結 構成一堆疊層82a; 84a，而絕緣層82b與犧牲複晶矽層84b 結構成另一堆疊層82b; 84b。堆疊層82a; 84a和82b; 84b 均爲實心筒狀，水平剖面可爲圓形、矩形或是其他形狀。 堆疊層82a; 843和82b; 84b的中心往下對應的較佳位置大 致均係同時偏向汲極區16a; 16b的某一側。在本較佳實施 例中’堆疊層82a; 84a和82b; 84b的中心均係偏向汲極區 16a; 16b的右側。之後分別在堆疊層82a; 84a和82b; 84b 17 度適用中國國) A4規格（210X297公釐_) ---------f I裝------訂-----i缘 (*-先閲讀背面之注意事項再填寫本頁) 053 1 TWF.DOC/002 A 7 五、發明説明（仏） 的側壁上形成二氧化矽邊牆86a和86b。在本較佳實施例 中，二氧化矽邊牆86a和86b可以以下列步驟形成：沈積 一二氧化矽層’其厚度例如約ιοοοΑ ;再回蝕刻。再來以 CVD法沈積一絕緣層88 ’其例如爲矽氮化物層’厚度例 如約2000 A。再來’利用機械化學式硏磨技術硏磨絕緣層 88，至少直到堆疊層82a; 84a和82b; 84b上方的部份露出 爲止。 請參照第4B圖’接著以堆疊層82a; 84&和82b; 84b、 以及絕緣層88爲蝕刻罩幕’蝕刻去除二氧化矽邊牆86a和 86b、以及其下的部份絕緣層80。然後以犧牲複晶矽層84a; 84b爲蝕刻罩幕’蝕刻去除絕緣層88 ’形成開口 90a和 90b。開口 90a和90b的深度可依實際需求加以調整，只 要與複晶矽層78表面保持一段距離即可。 經濟部中央標準局員工消費合作社印製 請參照第4C圖’接著在堆疊層82a; 84a和82b; 84b、 以及絕緣層80的表面沈積一複晶矽層92 ’厚度例如約 1000A，以塡滿開口 90a和9〇b。爲了提高複晶矽層92的 導電性，可將例如砷離子植入到複晶矽層92中。之後，利 用機械化學式硏磨技術硏磨複晶矽層92，至少直到絕緣層 82a; 82b上方的部份露出爲止，形成如圖所不的複晶砂層 92。在此步驟中，犧牲複晶矽層84a; 84b會被去除。 請參照第4D圖，接著以複晶矽層92與絕緣層80爲蝕 刻保護層，利用濕式蝕刻法去除絕緣層82a; 82b。之後以 CVD法沈積一絕緣層94，其例如是二氧化矽層’厚度例 如約2000A。再來利用傳統的光罩製版與蝕刻技術，依序 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 31 • DOC/002 31 • DOC/002 經濟部中央橾準局負工消費合作社印繁 Β7 五、發明説明（⑺） 蝕刻絕緣層94、複晶矽層92、絕緣層80和複晶矽層78 ’ 形成一開口 96，以界定出各記憶單兀的儲存電谷器之儲存 電極。亦即藉此步驟將複晶矽層92和78切割成若干區段 92a; 92b 和 78a; 78b。 請參照第4E圖，接著在開口 96的側壁上形成複晶矽 邊牆98a和98b。在本較佳實施例中’複晶矽邊牆98a; 98b 可以以下列步驟形成：沈積一複晶矽層’其厚度例如約 1000A;再回蝕刻。爲了提高複晶矽層98a; 98b的導電性’ 可將例如砷離子植入到複晶矽層98a; 98b中。之後利用濕 式蝕刻法，並以蝕刻保護層74爲蝕刻終點’將暴露出的二 氧化矽層去除，亦即去除絕緣層94和80。藉此步驟即完 成動態隨機存取記憶體的儲存電容器之儲存電極，其如圖 所示係由類樹幹狀的下複晶矽層78a; 78b、類樹幹狀的上 複晶矽層98a; 98b、以及一僅具有一支似L形剖面的類樹 枝狀複晶矽層92a; 92b所一起構成。類樹幹狀的下複晶矽 層78a; 78b連接到DRAM的轉移電晶體之汲極區16a; 16b，且具有一似U形的剖面。類樹幹狀的上複晶矽層98a; 98b的下端連接於類樹幹狀的下複晶矽層78a; 78b的週 邊，且大致以垂直方向往上延伸出。類樹枝狀複晶矽層92a; 92b自剖面觀之僅具有一支似L形的樹枝’其大致從類樹 幹狀的上複晶矽層98a; 98b之某一側的內表面，先以約水 平方向朝向類樹幹狀的上複晶矽層98a; 98b之另一內側延 伸出一段距離後，再以約垂直方向往下延伸出。接下來之 後續製程因無異於傳統製程，故在此不再贅述。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） ---------ί f裝------訂-----i線 (I先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印製 053 1TWF.DOC/002 A7 B7___ 五、發明説明（β') 在上述第一至第三較佳實施例中，儲存電極的類樹枝 狀電極層均只有似L形的剖面。然而，本發明並不限於此’ 儲存電極的類樹枝狀電極層可以包括有其他剖面形狀。下 一個較佳實施例即將描述具有一層似L形剖面與一似“一” 型剖面的類樹枝狀電極層的儲存電極。又’在上述第一至 第三較佳實施例中，類樹幹狀的下複晶矽層水平部份之下 表面均與其下方的蝕刻保護層接觸。然而，本發明亦不限 於此，下一個較佳實施例即將描述類樹幹狀的下複晶矽層 水平部份之下表面未與其下方的蝕刻保護層接觸，而相距 一段距離，以更增加儲存電極的表面積之作法。 接著將參照第5A至5F圖，詳述本發明的一種具有樹 型儲存電容器的半導體記憶元件之第四較佳實施例，半導 體記憶元件的此一較佳實施例，係由本發明的一種半導體 記億元件製造方法之第四較佳實施例所製造的。 本較佳實施例係以第2A圖所示的較佳實施例之結構 爲基礎，再以不同的製程製作不同結構的DRAM儲存電 極。在第5A至5F圖中，與第2A圖相似的部份係以相同 的編號標示。 請參照第2A圖與第5A圖，接著以CVD法依序沈積一 平坦化的絕緣層100、一蝕刻保護層102與一絕緣層104。 其中’絕緣層100例如爲BPSG，厚度例如約7000A ;蝕 刻保護層1〇2例如爲矽氮化物層，厚度例如約1000A ;絕 緣層104例如爲二氧化矽層，厚度例如約1000A。之後， 利用傳統的光罩製版和蝕刻技術，依序蝕刻絕緣層104、 20 本紙張尺度適用中國國家榡準（CNS ) Λ4規格（210X297公釐） ---------ί 袭------1Τ------ί 4 (請·先閲讀背面之注意事項再填寫本頁) 經濟部中央標率局員工消費合作社印製 053 1 TWF.DOC/002 A7 B7 五、發明説明（η ) 蝕刻保護層102、平坦化絕緣層100和閘極氧化層14，以 形成儲存電極接觸窗106a和106b，其係分別由絕緣層104 的上表面延伸到汲極區16a和16b的表面。接著，沈積一 複晶砂層108。如圖所示，複晶砂層108覆蓋在絕緣層104 的表面以及儲存電極接觸窗l〇6a和106b的內壁表面，但 未塡滿儲存電極接觸窗l〇6a和106b，因而使複晶矽層108 具有一似U形剖面的中空結構部份。爲了提高複晶矽層108 的導電性，可將例如砷離子植入到複晶矽層108中。 請參照第5B圖，接著在複晶矽層108表面沈積一厚的 絕緣層110，其例如爲二氧化矽層，厚度例如約7000A。 接著以CVD法在絕緣層110表面依序沈積一絕緣層與一犧 牲複晶矽層，再利用傳統的光罩製版和蝕刻技術定義絕緣 層與犧牲複晶矽層，因而形成如圖所示之絕緣層112a; 112b與犧牲複晶矽層114a; 114b。其中，絕緣層112a; 112b 例如爲矽氮化物層，厚度例如約是1000A，而犧牲複晶矽 層114a; 114b之厚度例如約是1000A。絕緣層112a與犧牲 複晶矽層114a結構成一堆疊層112a; 114a，而絕緣層112b 與犧牲複晶矽層114b結構成另一堆疊層112b; 114b。堆疊 層112a; 114a和112b; 114b均爲實心筒狀，水平剖面可爲 圓形、矩形或是其他形狀。堆疊層112a; 114a和112b; 114b 的中心往下對應的較佳位置大致均係同時偏向汲極區16a; 16b的某一側。在本較佳實施例中，堆疊層112a; 114a和 112b; 114b的中心均係偏向汲極區16a; 16b的右側。之後 分別在堆疊層112a; 114a和112b; 114b的側壁上形成二氧 (請先閲讀背面之注意事項再填寫本頁) .裝· 訂 」 4 本紙張尺度適用中國國家標準（CNS > A4規格（210X 297公釐） 05 3 1TWF.DOC/002 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（) 化矽邊牆116a和116b。在本較佳實施例中，二氧化矽邊 牆116a和116b可以以下列步驟形成：沈積一二氧化矽層， 其厚度例如約1000A;再回蝕刻。再來以CVD法沈積一絕 緣層118，其例如爲矽氮化物層，厚度例如約2000A。再 來，利用機械化學式硏磨技術硏磨絕緣層118，至少直到 堆疊層112a; U4a和112b; 114b上方的部份露出爲止。 請參照第5C圖，接著以堆疊層112a; 114a和112b; ll4b、以及絕緣層118爲蝕刻罩幕，蝕刻去除二氧化矽邊 牆116a和116b、以及其下方的部份絕緣層u〇。然後以 犧牲複晶矽層ll4a; 1Mb爲蝕刻罩幕，蝕刻去除絕緣層 118，形成開口 120a和120b。開口 120a和120b的深度可 依實際需求加以調整，只要與複晶矽層1〇8表面保持一段 距離即可。 請參照第5D圖，接著在堆疊層n2a; U4a和U2b; ll4b、以及絕緣層110的表面沈積—複晶矽層122，厚度 例如約胸A，以塡滿開口 12〇，腸。爲了提高複晶 砂層_雜，簡__子植人_晶砂層122 中。之後，利用麵化學式硏磨技麵磨複晶砂層122， 至少直到絕緣層1123; U2b上方的部份露出爲止，形成如 圖所示的複晶顏122。在此步驟中，犧牲複晶㈣⑽ 11扑會被去除。 請參照第，接著以複晶_ 12 触刻保護層，利用濕式倉虫刻法去除絕緣層my ^ 後以㈣法沈積一絕緣層124，其例如是 本纸張尺度適用中國國家標準（CNS > A4规格（ ---------f -裝------訂-----i '線 (*-先閲讀背面之注意事項再填寫本頁) 312娜 WF.DOC/002 A7 B7 經濟部中央標準局員工消费合作社印裝 五、發明説明（21 ) 度例如約2000A。然後在絕緣層124表面以CVD法沈積一 複晶矽層126，厚度例如約是1000A。再來利用傳統的光 罩製版與蝕刻技術，依序蝕刻複晶矽層126、絕緣層124、 複晶矽層122、絕緣層110和複晶矽層1〇8，形成一開口 127，以界定出各記憶單元的儲存電容器之儲存電極。亦 即藉此步驟將複晶矽層122和108切割成若干區段122a; 122b 和 108a; 108b 。 請參照第5F圖，接著在開口 127的側壁上形成複晶矽 邊牆128a和128b。在本較佳實施例中，複晶矽邊牆128a; 128b可以以下列步驟形成：沈積一複晶矽層，其厚度例如 約1000A ;再回蝕刻。爲了提高複晶矽層128a; 128b的導 電性，可將例如砷離子植入到複晶矽層128a; 128b中。之 後利用傳統的光罩製版與蝕刻技術，將複晶矽層126切割 成若干區段126a; 126b。最後利用濕式蝕刻法，並以蝕刻 保護層102爲蝕刻終點，將暴露出的二氧化矽層去除，亦 即去除絕緣層124 ' 110和104。藉此步驟即完成動態隨 機存取記憶體的儲存電容器之儲存電極，其如圖所示係由 類樹幹狀的下複晶矽層108a; 108b、類樹幹狀的上複晶矽 層128a; 128b、一具有似“一”型剖面的類樹枝狀複晶矽層 126a; 120b以及一僅具有一支似L形剖面的類樹枝狀複晶 矽層122a; 122b所一起構成。類樹幹狀的下複晶矽層108a; 108b連接到DRAM的轉移電晶體之汲極區16a; 16b，且具 有一似U形的剖面。類樹幹狀的上複晶矽層128a; 128b的 下端連接於類樹幹狀的下複晶矽層l〇8a; 108b的週邊，且 23 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 經濟部中央標準局員工消費合作社印裝 053 1 TWF.DOC/002 八7 __ ____B7__ 五、發明説明（u) 大致以垂直方向往上延伸出。類樹枝狀複晶政層126a; 126b大致係從類樹幹狀的上複晶矽層128a; 128b之上末端 內表面，以約水平方向往內延伸出。類樹枝狀複晶矽層122a; 122b自剖面觀之僅具有一支似L形的樹枝，其大致從類樹 幹狀的上複晶矽層128a; 128b之某一側的內表面，先以約 水平方向朝向類樹幹狀的上複晶矽層128a; 128b之另一內 側延伸出一段距離後，再以約垂直方向往下延伸出。接下 來之後續製程因無異於傳統製程，故在此不再贅述。 熟習此藝者應可瞭解，上述本發明各個較佳實施例的 構想特徵，除了可以單獨應用之外，亦可混合應用，而再 達成非常多種不同結構的儲存電極和儲存電容器，這些儲 存電極和儲存電容器的結構都應在本發明的保護範圍之 內。 應注意雖然在圖式中轉移電晶體的汲極均爲矽基底表 面的擴散區結構，然本發明並不限於此’任何適當的汲極 結構均可應用於本發明，例如溝槽式（trench )汲極即爲 一例。 再者，也應注意圖式中各構件部份的形狀、尺寸、和 延伸的角度，僅爲繪示方便所作的示意表示’其與實際情 況或有差異，故不應用以限制本發明。 雖然本發明已以若干較佳實施例揭露如上’然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 24 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29*?公釐） ---------ί -裝------訂------1紇 (請'先聞讀背面之注意事項再填寫本頁), 1T This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210Χ297mm) 053 ITWF.DOC / 002 A7 B7 __ Fifth, the invention description (η) CVD deposition of an engraving protection layer (etching protection layer) 22 It is, for example, a silicon nitride layer (silicon nitride) with a thickness of about 1000A. After that, using conventional photomask patterning and etching techniques, the etching protection layer 22, the insulating layer 20, and the gate oxide layer 14 are sequentially etched to form storage electrode contact holes 24a and 24b ', which are respectively The upper surface of the etching protection layer 22 extends to the surfaces of the drain regions 16a and i6b. Next, a polysilicon layer 26 is deposited on the surface of the etching protection layer 22 by the cvd method. In order to increase the conductivity of the polycrystalline silicon layer 26, for example, arsenic ions may be implanted into the polycrystalline silicon layer 26. As shown in the figure, the polycrystalline silicon layer 26 is filled with storage electrode contact windows 24a; 24b, and covers the surface of the etching protection layer 22. After that, a thick insulating layer 28 is deposited on the surface of the polycrystalline silicon layer 26, which is, for example, a silicon dioxide layer, with a thickness of, for example, about 7000A. Please refer to FIG. 2C, and then sequentially deposit an insulating layer and a sacrificial polycrystalline silicon layer on the surface of the insulating layer 28 by CVD method, and then define the insulating layer and the sacrificial polycrystalline silicon layer using traditional photomask patterning and @ 刻 技术, Thus, an insulating layer 3a; 30b and a sacrificial polycrystalline silicon layer 3a and 32b are formed as shown in the figure. Among them, the insulating layer 30a; 30b is, for example, a silicon nitride layer with a thickness of, for example, about 1000a, and the sacrificial polycrystalline silicon layer 32a; 32b has a thickness of, for example, about 1000A. The insulating layer 30a and the sacrificial polycrystalline sand layer 32a are formed as a stacked layer 30a; 32a, which is a solid cylindrical shape. The horizontal cross section may be circular, rectangular, or other shapes. The preferred position of the stacked layer 32a roughly corresponds to that above the drain region 1; and the insulating layer 30b and the sacrificial polycrystalline silicon layer 32b are structured as another stacked layer 30b; 32b 'is also a solid cylindrical shape, and the horizontal section can be It is round, rectangular or other shapes. Stacked layer 30b; the preferred position of 32b roughly corresponds to the drain region _ 9 This paper size is used in '(eNS) (2ι () χ 297 to} (please read the precautions on the back before filling this page) 丨Installed .1Τ DOC / 002 A7 DOC / 002 A7 printed by Employee Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs B7___ printed by Beigong Consumer Cooperative Bureau of Central Bureau of Standards of Ministry of Economics V. Above the description of invention (S) 16b. Please refer to the 2D figure Then, silicon dioxide side walls (spacers) 34a and 34b are formed on the side walls of the stacked layers 30a; 32a and 30b; 32b. In the preferred embodiment, the silicon dioxide side walls 34a and 34b may be as follows Column step formation: depositing a silicon dioxide layer with a thickness of about 1000A; then etchback. Then, an insulating layer 36, such as a silicon nitride layer, with a thickness of about 2000A is deposited by CVD method. 'Using mechanical chemical polishing (chemical mechanical polish; CMP) technology to polish the insulating layer 36, at least until the stacked layers 30a; 32a and 30b; 32b above the exposed part. Please refer to Figure 2E, and then stacked layer 30a; 32a, 30b; 32b and insulating layer 36 are Engrave the mask, uranium etching removes the silicon dioxide sidewalls 34a; 34b and the underlying insulating layer 28. Then the sacrificial polycrystalline silicon layer 32a; 32b is used as an etch mask to etch and remove the insulating layer 36 to form the opening 38a and 38b. The depths of the openings 38a and 38b can be adjusted according to the actual needs' as long as it is kept at a distance from the surface of the polycrystalline silicon layer 26. Please refer to Figure 2F, and then on the stacked layers 3〇a ;, 30b; 32b and the insulating layer A polysilicon layer 40 is deposited on the surface of 28, with a thickness of, for example, about 1000 A to fill the openings 38a and 38b. To increase the conductivity of the polysilicon layer 40, arsenic ions can be implanted into the polysilicon layer 40, for example Afterwards, the polycrystalline sand layer 40 is polished using mechanochemical polishing technology, at least until the upper part of the insulating layer 30a; 30b is exposed, forming a polycrystalline silicon layer 40 as shown in the figure. In this step, sacrificial polycrystalline is sacrificed The silicon layer 32a; 32b will be removed. Please refer to Figure 2G, and then use the polycrystalline silicon layer 40 and the insulating layer 28 as the etching standard. The paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) ---- ----- ί Attack ------, 玎 ------ ^ ^ (please read the note on the back first Please fill in this page for more details) 053 1TWF.DOC / 002 A7 053 1TWF.DOC / 002 A7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy ______B7 V. Description of the invention (1) Engrave the protective layer and remove the insulation by wet etching Layer 30a; 30b. Afterwards, an insulating layer 42 is deposited by CVD, which is, for example, a layer of sand dioxide with a thickness of, for example, about 2000A. Next, using traditional photomask patterning and etching technology, the insulating layer 42, the polycrystalline sand layer 40, the insulating layer 28, and the polycrystalline sand layer 26 are sequentially engraved to form an opening 44 'to define the storage of each billion unit The storage electrode of the capacitor. That is, this step cuts the polycrystalline silicon layer 40 and% into sections 40a; 40b and 26a; 26b. Please refer to FIG. 2H, and then form polysilicon sidewalls 46a and 46b on the side walls of the opening 44. In this preferred embodiment, the polycrystalline sand edge walls 46a; 46b can be formed by the following steps: depositing a polycrystalline sand layer with a thickness of, for example, about ΙΟΟΟΑ, and then saturating. In order to improve the conductivity of the polycrystalline sand layer 46a; 46b, for example, arsenic ions can be implanted into the polycrystalline silicon layer 46a; 4615. Then, the wet etching method is used, and the etching protection layer 22 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layers 42 and 28 are removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is shown by the trunk-like lower polycrystalline silicon layer 26a; 26b, the trunk-like upper polycrystalline sand layer 46a; 46b, And a dendrite-like polycrystalline silicon layer 40a; 40b having an L-shaped cross section is formed together. The trunk-like lower polycrystalline silicon layer 26a; 26b is connected to the drain region 16a of the transfer transistor of the DRAM; 10b 'and has a T-like cross-section. The lower end of the trunk-like upper polycrystalline silicon layer 46a; 46b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 26a; 26b 'and extends substantially upward. The dendritic polycrystalline silicon layer 40a; 40b extends from the inner surface of the trunk-like upper polycrystalline silicon layer 46a; 46b first in a horizontal direction inward, and then extends downward in a vertical direction. Because the storage paper size of the present invention is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back and then fill out this page) Order " 312830 053 ITWF.DOC / 002 A7 B7 Economy Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Education 5. The description of the invention (w) The shape of the storage electrode is very special, so in this specification it is referred to as the "tree storage electrode" and the resulting capacitor is referred to as " Tree storage capacitor ". Please refer to FIG. 21, and then form a dielectric film layer 48a; 48b on the exposed surfaces of the storage electrodes 26a, 40a, 46a; 26b, 40b; 46b respectively. The dielectric film layer 48a; 48b may be, for example, a silicon dioxide layer, a NO (sand nitride / sand dioxide) structure of a silicon nitride layer, a ΝΝΟ (silicon dioxide / sand nitride / silicon dioxide) structure, or any Similar. Then, a counter electrode 50 made of polycrystalline silicon is formed on the surfaces of the dielectric film layers 48a and 48b. The process of the counter electrode can be achieved by the following steps: depositing a polycrystalline silicon layer by CVD with a thickness of, for example, 1000A; then doping with, for example, N-type impurities to improve its conductivity; and finally defining the complex by traditional mask making and etching techniques The crystalline silicon layer completes the storage capacitors of the DRAM memory cells. Although not shown in FIG. 21, those familiar with this art should understand that the structure of FIG. 21 can be manufactured according to the traditional process technology for bit lines, bonding pads, interconnection wires, and isolation protection layers (passivation) , And packaging, etc., to complete the DRAM integrated circuit. Since these processes are not characteristic of the present invention, they will not be repeated here. In the first preferred embodiment, the storage electrode has only one layer like dendritic electrode layer with an L-shaped cross-section. However, the present invention is not limited to this, and the number of layers of the dendritic electrode layer having a storage electrode resembling an L-shaped cross-section may be two, three, or more. The next preferred embodiment will describe a storage electrode having two dendritic-like electrode layers having an L-shaped cross section. Next, with reference to FIGS. 3A to 3E, a second preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. The semi-conducting paper standard is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 Mm) ---------- installed ------ ordered -------- know (I read the notes on the back before filling this page) 053 1 TWF.DOC / 002 A7 B7 5. Description of Invention (丨 I) This preferred embodiment of the body memory device is manufactured by the second preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2F, and then DRAM storage electrodes with different structures are manufactured by different processes. In Figs. 3A to 3E, the parts similar to those in Fig. 2f are marked with the same numbers. Please refer to FIGS. 2F and 3A. Then, the polycrystalline silicon layer 40 and the insulating layer 28 are used as etching protective layers, and the insulating layers 30a and 30b are removed by a wet etching method. Afterwards, an insulating layer 52 is deposited by CVD, for example, a silicon dioxide layer, with a thickness of about 2000A. Next, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer 52 by the CVD method, and then the insulating layer and the sacrificial polycrystalline silicon layer are defined by using traditional photomask patterning and etching techniques, thus forming as shown in the figure 56b. The insulating layer 54a; 54b and the sacrificial polycrystalline silicon layer 56a; 56b. Among them, the insulating layers 54a; 54b are, for example, silicon nitride layers with a thickness of, for example, about 1000A, and the sacrificial polycrystalline silicon layer 56a; 56b has a thickness of, for example, about 1000A. The insulating layer 54a and the sacrificial polycrystalline sand layer 56a are structured as a stacked layer 54a; 56a 'is a solid cylinder. The horizontal cross section may be circular, rectangular or other shapes. The stacked layer 54a; 56a is smaller than the stacked layer 30a; 32a in FIG. 2C, and its preferred position roughly corresponds to the top of the drain region 16a; and the insulating layer 54b and the sacrificial polycrystalline silicon layer 56b are structured as another stacked layer 54b 56b, which is also a solid tube 'horizontal cross-section can be round, rectangular or other shapes. The stacked layers 54b; 56b are smaller than the stacked layers 30b; 32b in FIG. 2C, and their preferred positions generally correspond to those above the drain region 16b. Please refer to Figure 3B, and then on the stacking layer 54a; 56a and Mb; 56b --------- {丨 装 ------ 定 ----- i line (^ first read the back Note: Please fill out this page again.) The paper standards printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs are applicable to the Chinese National Standard (CNS) A4 (210X 297mm) 053 1TWF.DOC / 002 A7 B7 V. Description of Invention (丨 2 ·) The silicon dioxide sidewalls 58a and 58b are formed on the side walls. In the preferred embodiment, the silicon dioxide sidewalls 58a and 58b can be formed by the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000A; and then etching back. After that, an insulating layer 60 is deposited by CVD, which is, for example, a silicon nitride layer, and has a thickness of about 2000A, for example. Next, the insulating layer 60 is polished using a mechanochemical polishing technique until at least the portion above the stacked layers 54a; 56a and 54b; 56b is exposed. Please refer to FIG. 3C, and then use the stacked layers 54a; 56a, 54b; 56b and the insulating layer 60 as an etching mask to etch and remove the silicon dioxide sidewalls 58a; 58b and the insulating layer 52 and part of the insulating layer 28 below it. Then, using the sacrificial polysilicon layer 56a; 56b as an etching mask, the insulating layer 60 is etched away to form openings 62a and 62b. The depth of the openings 62a and 62b can be adjusted according to actual needs, as long as it is kept at a distance from the surface of the polycrystalline silicon layer 26. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). Please refer to Figure 3D, and then deposit a polycrystal on the surface of stacked layers 54a; 56a, 54b; 56b and insulating layer 52 The silicon layer 64 has a thickness of about 1000 A, for example, to fill the openings 62a and 62b. In order to improve the conductivity of the polycrystalline silicon layer 64, for example, arsenic ions can be implanted into the polycrystalline silicon layer 64. After that, the polycrystalline silicon layer 64 is polished using a mechanochemical polishing technique until at least the portions above the insulating layers 54a; 54b are exposed, forming a polycrystalline silicon layer 64 as shown in the figure. In this step, the sacrificial polycrystalline silicon layer 56a; 56b is removed. Next, the polycrystalline silicon layer 64 and the insulating layer 52 are used as etching protective layers, and the insulating layer 54a; 54b is removed by a wet etching method. Please refer to FIG. 3E, and then deposit an insulating layer 66 by CVD, which is, for example, a silicon dioxide layer with a thickness of about 2000A, for example. Let's make use of the traditional paper standard to apply the Chinese National Standard (CNS) A4 specification (2 丨 OX297mm) 31288t ^ F.DOC / 002 A7 _ B7 " X, invention description (丨》) Mask making and etching technology , Etching the insulating layer 66, the polycrystalline sand layer 64, the insulating layer 52, the polycrystalline silicon layer 40, the insulating layer 28 and the polycrystalline silicon layer 26 in sequence to form an opening 68 to define the storage of the storage capacitors of each memory cell electrode. That is, by this step, the polycrystalline cutting layers 64, 40 and 26 are cut into several sections 64a; 64b, 40a; 40b and 26a; 26b. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back and fill in this page). Please refer to Figure 3F, and then form polycrystalline sand side walls 7〇a and 7〇b on the side walls of the opening 68. In this preferred embodiment, the polycrystalline silicon sidewall spacers 7〇a; 7〇b can be formed in the following steps. Deposit a polycrystalline sand layer with a thickness of, for example, about 1000A; then etch back. In order to improve the conductivity of the polycrystalline silicon layer 70a; 70b, for example, arsenic ions can be implanted into the polycrystalline silicon layer 70a; 70b '. Afterwards, the wet silicon etching method is used, and the exposed silicon oxide layer is removed using the etching protection layer 22 as the end point of etching, that is, the insulating layers 66, S2 and 28 are removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is not composed of a trunk-like lower polycrystalline sand layer 26a; 26b, a trunk-like upper polycrystalline silicon layer 70a; 70b, And two layers of dendritic polycrystalline silicon layers 64a; 64b and 40a; The trunk-like lower polycrystalline silicon layer 26a; 26b is connected to the drain region 16a; 16b 'of the transfer transistor of the DRAM and has a T-like profile. The trunk-like upper polycrystalline sand layer 70a; 70b has a lower end connected to the periphery of the trunk-like lower polycrystalline silicon layer 26a; 26b, and extends approximately vertically upward. The dendritic polycrystalline silicon layer 64a; 64b and 40a; 40b are approximately parallel, and respectively from the inner surface of the trunk-like upper polycrystalline silicon layer 70a; 70b, extend inward in the horizontal direction at a distance, and then Extend downwards approximately vertically. Since the subsequent process is no different from the traditional process, it will not be repeated here. If you want to get _____ 15 paper size 4 for Zhongjia County (CNS) A4 specification (21 () > < 297 public director) A7 053 1TWF.DOC / 002 _______B7___ V. Invention description (丨 y) More layers As for the dendritic electrode layer, as long as it is described in this preferred embodiment (FIGS. 3A to 3D), the production of repeated stacked layers can meet the requirements. From the cross-sectional view, the dendritic electrode layers in the first and second preferred embodiments above have two L-shaped branches. However, the present invention is not limited thereto. The dendritic electrode layers are L-shaped. The branch may have only one branch. The next preferred embodiment will describe a storage electrode having a single branch-like dendritic electrode layer with an L-shaped cross section. In addition, the trunk-like lower polycrystalline silicon layers in the first and second preferred embodiments described above are solid members and have a T-shaped cross-section. However, the present invention is not limited to this, trunk-like The lower polycrystalline silicon layer may have a hollow structure to increase the surface area of the storage electrode. The next preferred embodiment will describe a structure and a method in which the trunk-like lower polycrystalline silicon layer has a U-shaped cross section to further increase the surface area of the storage electrode. Next, referring to FIGS. 4A to 4E, a third preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is a semiconductor memory of the present invention. The third preferred embodiment of the device manufacturing method is manufactured. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2A, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figs. 4A to 4E, the parts similar to those in Fig. 2A are marked with the same numbers. Please refer to FIGS. 2A and 4A, and then a CVD method is used to deposit a planarized insulating layer 72, which is, for example, BPSG and has a thickness of, for example, about 7000A. Then, an etch protection layer 74 is deposited by CVD, which is, for example, silicon nitride 16 --------- {-装 J ----- 定 ------ (please read first Note on the back and then fill out this page) The paper standard printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is suitable for the Chinese National Falcon (CNS) Λ4 specification (210X297 mm) Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy 05 3 1TWF.DOC / 002 A ^ A7 ___ _B7 V. Description of the invention (丨. () ~ Object layer, thickness is about 1000A. Afterwards, the etching protection layer 74 is etched in sequence using traditional photomask plate making and etching techniques, flat The insulating layer 72 and the gate oxide layer 14 'form storage electrode contact windows 76a and 76b, which extend from the upper surface of the etch protection layer 74 to the surfaces of the drain regions 16a and 16b, respectively. Then, a polycrystal is deposited Silicon layer 78. As shown, the polycrystalline silicon layer 78 covers the surface of the etching protection layer 74 and the inner wall surfaces of the storage electrode contact windows 76a and 76b, but does not fill the storage electrode contact windows 76 & and 761), so The polycrystalline silicon layer 78 has a hollow structure portion with a U-shaped cross section. In order to improve the conductivity of the polycrystalline silicon layer 78, for example, arsenic ions may be implanted into the polycrystalline sand layer 78. After that, a thick insulating layer 80 'is deposited on the surface of the polycrystalline silicon layer 78, which is, for example, a silicon dioxide layer, and has a thickness of, for example, about 7000 a. Then deposit an insulating layer and a sacrificial polycrystalline sand layer on the surface of the insulating layer 80 in sequence by CVD method, and then use the traditional mask making and etching technology to define the insulating layer and the sacrificial polycrystalline silicon layer 'to form the insulation shown The layers 82a; 82b and the sacrificial polycrystalline sand layer 84a; 84b. The thickness of the insulating layer 82a; 82b is, for example, a silicon nitride layer ', for example, about 1000A, and the thickness of the sacrificial polycrystalline silicon layer 84a; 84b is, for example, about 1000A. 84a, the insulating layer 82a and the sacrificial polycrystalline silicon layer 84a form a stacked layer 82a; 84a, and the insulating layer 82b and the sacrificial polycrystalline silicon layer 84b form another stacked layer 82b; 84b. The stacked layers 82a; 84a and 82b; 84b are solid cylindrical, and the horizontal cross-section may be circular, rectangular or other shapes. The preferred positions corresponding to the center of the stacked layers 82a; 843 and 82b; 84b downwards are generally both biased to one side of the drain region 16a; 16b at the same time. In this preferred embodiment, the center of the stacked layers 82a; 84a and 82b; 84b are all biased to the right of the drain region 16a; 16b. After that, at the stacked layers 82a; 84a and 82b; 84b 17 degrees apply to China) A4 specification (210X297mm_) --------- f I installed ------ ordered ----- i margin (* -Read the precautions on the back before filling in this page) 053 1 TWF.DOC / 002 A 7 V. Invention description (s) The silicon dioxide side walls 86a and 86b are formed on the side walls. In this preferred embodiment, the silicon dioxide sidewalls 86a and 86b can be formed by the following steps: depositing a silicon dioxide layer whose thickness is, for example, about ιοοοΑ; and then etching back. Next, an insulating layer 88 'is deposited by CVD, which is, for example, a silicon nitride layer' and has a thickness of about 2000 A, for example. Let's use the mechanochemical grinding technology to grind the insulating layer 88 at least until the portions above the stacked layers 82a; 84a and 82b; 84b are exposed. Please refer to FIG. 4B 'and then use the stacked layers 82a; 84 & and 82b; 84b, and the insulating layer 88 as etching masks' to etch and remove the silicon dioxide sidewalls 86a and 86b, and a part of the insulating layer 80 thereunder. Then, the sacrificial polycrystalline silicon layer 84a; 84b is used as an etching mask, and the insulating layer 88 is etched away to form openings 90a and 90b. The depths of the openings 90a and 90b can be adjusted according to actual needs, as long as they are kept at a distance from the surface of the polycrystalline silicon layer 78. Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, please refer to Figure 4C. Then deposit a polycrystalline silicon layer 92 on the surface of the stacked layers 82a; 84a and 82b; 84b, and the insulating layer 80. The thickness is about 1000A, for example. Openings 90a and 90b. In order to increase the conductivity of the polycrystalline silicon layer 92, for example, arsenic ions can be implanted into the polycrystalline silicon layer 92. After that, the polycrystalline silicon layer 92 is polished by mechanochemical polishing technology, at least until the upper part of the insulating layers 82a; 82b is exposed, and a polycrystalline sand layer 92 as shown in the figure is formed. In this step, the sacrificial polycrystalline silicon layer 84a; 84b is removed. Please refer to FIG. 4D, and then use the polycrystalline silicon layer 92 and the insulating layer 80 as etching protection layers, and remove the insulating layers 82a and 82b by wet etching. Then, an insulating layer 94 is deposited by CVD, for example, a silicon dioxide layer 'with a thickness of, for example, about 2000A. Let's use the traditional photomask plate making and etching technology, and the paper standard is in accordance with the Chinese National Standard (CNS) A4 specification (210X 297 mm) in order. 31 • DOC / 002 31 • DOC / 002 Ministry of Economic Affairs Consumer Cooperative Yinfan B7 V. Description of the invention (⑺) The insulating layer 94, the polycrystalline silicon layer 92, the insulating layer 80 and the polycrystalline silicon layer 78 'are etched to form an opening 96 to define the storage valley of each memory cell The storage electrode. That is, this step cuts the polycrystalline silicon layers 92 and 78 into sections 92a; 92b and 78a; 78b. Please refer to FIG. 4E, and then form polycrystalline silicon sidewalls 98a and 98b on the side walls of the opening 96. In this preferred embodiment, the 'polycrystalline silicon sidewall 98a; 98b can be formed by the following steps: depositing a polycrystalline silicon layer' whose thickness is, for example, about 1000A; and then etched back. In order to improve the conductivity of the polycrystalline silicon layer 98a; 98b ', for example, arsenic ions can be implanted into the polycrystalline silicon layer 98a; 98b. After that, the wet silicon etching method is used, and the exposed silicon dioxide layer is removed using the etching protection layer 74 as the etching end point, that is, the insulating layers 94 and 80 are removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is shown as a trunk-like lower polycrystalline silicon layer 78a; 78b, a trunk-like upper polycrystalline silicon layer 98a; 98b And a dendritic polycrystalline silicon layer 92a; 92b having only one L-shaped cross section. The trunk-like lower polycrystalline silicon layer 78a; 78b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a U-shaped cross section. The lower end of the trunk-like upper polycrystalline silicon layer 98a; 98b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 78a; 78b, and extends upward in a substantially vertical direction. The dendritic polycrystalline silicon layer 92a; 92b only has an L-shaped branch from a cross-sectional view, which is roughly from the trunk-like upper polycrystalline silicon layer 98a; the inner surface of one side of 98b, first Horizontally toward the trunk-like upper polycrystalline silicon layer 98a; 98b, the other inside extends a distance, and then extends downward in about vertical direction. The subsequent process is no different from the traditional process, so it will not be repeated here. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------- ί f installed ------ set ----- i line (I read the back first Please pay attention to this page and then fill out this page) Employee Consumer Cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs Du Printed 053 1TWF.DOC / 002 A7 B7___ 5. Description of Invention (β ') In the first to third preferred embodiments above, the storage electrode The dendrite-like electrode layers have only L-shaped cross sections. However, the present invention is not limited to this. The dendritic electrode layer of the storage electrode may include other cross-sectional shapes. The next preferred embodiment will describe a storage electrode having a dendritic-like electrode layer having an L-like cross-section and a "one" -like cross-section. Also in the first to third preferred embodiments described above, the lower surface of the horizontal portion of the trunk-like lower polycrystalline silicon layer is in contact with the etching protection layer below it. However, the present invention is not limited to this. The next preferred embodiment is to describe the trunk-like lower polycrystalline silicon layer. The lower surface of the horizontal portion is not in contact with the etching protection layer under it, but is separated by a distance to increase storage. The surface area of the electrode. Next, referring to FIGS. 5A to 5F, a fourth preferred embodiment of a semiconductor memory device with a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is a semiconductor memory device of the present invention. Manufactured by the fourth preferred embodiment of the 100 million element manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2A, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figs. 5A to 5F, the parts similar to those in Fig. 2A are marked with the same numbers. Please refer to FIGS. 2A and 5A, and then sequentially deposit a planarized insulating layer 100, an etch protection layer 102 and an insulating layer 104 by CVD. Wherein, the insulating layer 100 is, for example, BPSG with a thickness of about 7000A; the etch protection layer 102 is a silicon nitride layer with a thickness of about 1000A; the insulating layer 104 is a silicon dioxide layer with a thickness of about 1000A, for example. After that, using traditional photomask plate-making and etching techniques, the insulating layers 104 and 20 were etched in this order. The paper standard is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm) ----- 1Τ ------ ί 4 (please read the precautions on the back before filling out this page) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards and Statistics, Ministry of Economic Affairs 053 1 TWF.DOC / 002 A7 B7 V. DESCRIPTION OF THE INVENTION (η) Etching the protective layer 102, planarizing the insulating layer 100 and the gate oxide layer 14 to form storage electrode contact windows 106a and 106b, which extend from the upper surface of the insulating layer 104 to the drain regions 16a and 16b, respectively s surface. Next, a layer of polycrystalline sand 108 is deposited. As shown in the figure, the polycrystalline sand layer 108 covers the surface of the insulating layer 104 and the inner wall surfaces of the storage electrode contact windows 106a and 106b, but does not fill the storage electrode contact windows 106a and 106b, so that the polycrystalline silicon The layer 108 has a hollow structure portion with a U-shaped cross section. In order to improve the conductivity of the polycrystalline silicon layer 108, for example, arsenic ions can be implanted into the polycrystalline silicon layer 108. Please refer to FIG. 5B, and then deposit a thick insulating layer 110 on the surface of the polycrystalline silicon layer 108, which is, for example, a silicon dioxide layer with a thickness of, for example, about 7000A. Then, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer 110 by the CVD method, and then the insulating layer and the sacrificial polycrystalline silicon layer are defined by using traditional mask making and etching techniques, thus forming 114b. The insulating layer 112a; 112b and the sacrificial polycrystalline silicon layer 114a; 114b. Among them, the insulating layers 112a; 112b are, for example, silicon nitride layers with a thickness of, for example, about 1000A, and the sacrificial polycrystalline silicon layer 114a; 114b has a thickness of, for example, about 1000A. The insulating layer 112a and the sacrificial polycrystalline silicon layer 114a form a stacked layer 112a; 114a, and the insulating layer 112b and the sacrificial polycrystalline silicon layer 114b form another stacked layer 112b; 114b. The stacked layers 112a; 114a and 112b; 114b are solid cylindrical, and the horizontal cross-section may be circular, rectangular, or other shapes. The preferred positions corresponding to the center of the stacked layers 112a; 114a and 112b; 114b are roughly all at the same time biased to one side of the drain region 16a; 16b. In the preferred embodiment, the centers of the stacked layers 112a; 114a and 112b; 114b are all biased to the right of the drain region 16a; 16b. After that, dioxins are formed on the sidewalls of the stacked layers 112a; 114a and 112b; 114b (please read the precautions on the back and then fill out this page). Binding and ordering 4 This paper size is applicable to the Chinese national standard (CNS > A4 specifications (210X 297 mm) 05 3 1TWF.DOC / 002 A7 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () Silicon side walls 116a and 116b. In this preferred embodiment, the dioxide The silicon sidewalls 116a and 116b can be formed in the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000 A; and then etching back. Then, an insulating layer 118 is deposited by CVD, for example, a silicon nitride layer, with a thickness of Approximately 2000A. Next, the insulating layer 118 is polished using mechanochemical polishing technology, at least until the upper part of the stacked layers 112a; U4a and 112b; 114b is exposed. Please refer to FIG. 5C, and then the stacked layers 112a; 114a and 112b; ll4b, and the insulating layer 118 is an etch mask, etching to remove the silicon dioxide side walls 116a and 116b, and a portion of the insulating layer u〇 below. Then sacrifice sacrificial polycrystalline silicon layer ll4a; 1Mb as an etch mask, Etching away the insulating layer 118, Openings 120a and 120b are formed. The depth of the openings 120a and 120b can be adjusted according to actual needs, as long as it is kept at a distance from the surface of the polycrystalline silicon layer 108. Please refer to Figure 5D, and then on the stacked layers n2a; U4a and U2b ll4b, and the surface of the insulating layer 110 is deposited-polycrystalline silicon layer 122, a thickness of, for example, chest A, to fill the opening 12〇, intestines. In order to improve the polycrystalline sand layer_Miscellaneous, Jane _ 子 植 人 _Crystal layer 122 Afterwards, the polycrystalline sand layer 122 is surface-grinded using a surface chemical formula grinding technique, at least until the portion above the insulating layer 1123; U2b is exposed, forming a polycrystalline surface 122 as shown in the figure. In this step, the polycrystalline sacrificial crystal is sacrificed ㈣⑽ 11 flutter will be removed. Please refer to the following, and then touch the protective layer with polycrystalline _12, remove the insulating layer my ^ by the wet worm etching method, and then deposit an insulating layer 124 by the ㈣ method, for example, this paper The scale is applicable to the Chinese National Standard (CNS > A4 specification (--------- f -installed ------ ordered ----- i 'line (* -read the precautions on the back and then fill in This page) 312 Na WF.DOC / 002 A7 B7 Printed and printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (21) degrees For example, about 2000 A. Then, a polycrystalline silicon layer 126 is deposited on the surface of the insulating layer 124 by CVD with a thickness of, for example, about 1000 A. Then, using the conventional photomask patterning and etching techniques, the polycrystalline silicon layer 126 and the insulating layer are sequentially etched 124. The polycrystalline silicon layer 122, the insulating layer 110 and the polycrystalline silicon layer 108 form an opening 127 to define the storage electrodes of the storage capacitors of the memory cells. That is, by this step, the polycrystalline silicon layers 122 and 108 are cut into sections 122a; 122b and 108a; 108b. Please refer to FIG. 5F, and then form polycrystalline silicon sidewalls 128a and 128b on the side walls of the opening 127. In this preferred embodiment, the polycrystalline silicon sidewall spacers 128a; 128b can be formed by the following steps: depositing a polycrystalline silicon layer with a thickness of, for example, about 1000A; and then etching back. In order to improve the conductivity of the polycrystalline silicon layer 128a; 128b, for example, arsenic ions can be implanted into the polycrystalline silicon layer 128a; 128b. After that, using traditional photomask patterning and etching techniques, the polycrystalline silicon layer 126 is cut into sections 126a; 126b. Finally, the wet etching method is used, and the etching protection layer 102 is used as an etching end point to remove the exposed silicon dioxide layer, that is, the insulating layers 124 ′ 110 and 104 are removed. With this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is shown as a trunk-like lower polycrystalline silicon layer 108a; 108b, a trunk-like upper polycrystalline silicon layer 128a; 128b 1. A dendritic polycrystalline silicon layer 126a; 120b having a "one" -like cross-section and a dendritic polycrystalline silicon layer 122a; 122b having only one L-shaped cross section are formed together. The trunk-like lower polycrystalline silicon layer 108a; 108b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a U-like profile. The trunk-like upper polycrystalline silicon layer 128a; the lower end of 128b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 108a; 108b, and 23 paper scales are applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X297 Mm) (Please read the precautions on the back before filling in this page)-Binding · Order Printed by the Employees ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 053 1 TWF.DOC / 002 8 7 __ ____B7__ V. Description of Invention (u) Vertically extend upwards. The dendrite-like compound crystal layer 126a; 126b is roughly from the inner surface of the upper end of the trunk-like compound crystal silicon layer 128a; 128b, extending inward in a horizontal direction. The dendritic polycrystalline silicon layer 122a; 122b only has an L-shaped branch from a cross-sectional view, which is roughly from the inner surface of one side of the trunk-like upper polycrystalline silicon layer 128a; 128b. The horizontal direction is toward the trunk-like upper polycrystalline silicon layer 128a; the other inner side of 128b extends a distance, and then extends downward in a vertical direction. The following subsequent processes are no different from traditional processes, so they will not be repeated here. Those skilled in the art should understand that the above-mentioned conceptual features of the preferred embodiments of the present invention can be used in addition to separate applications, and can also be used in combination to achieve a very wide variety of storage electrodes and storage capacitors with different structures. The structure of the storage capacitor should be within the protection scope of the present invention. It should be noted that although the drains of the transfer transistors in the drawings are all diffusion regions on the surface of the silicon substrate, the present invention is not limited to this. Any suitable drain structure can be applied to the present invention, such as trench ) Jiji is an example. In addition, the shapes, sizes, and extension angles of each component part in the drawings should also be noted. The illustrations are for convenience of illustration only. They may differ from the actual situation, so they should not be used to limit the present invention. Although the present invention has been disclosed in several preferred embodiments as above, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and retouching without departing from the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. 24 The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X29 *? Mm) --------- ί -installation ------ order ------ 1 纥 (please ' (Read the precautions on the back before filling this page)