TW306035B - Manufacturing method of semiconductor memory device with capacitor (part 7) - Google Patents

Abstract

A manufacturing method of semiconductor memory device with capacitor, in which the semiconductor memory device includes one substrate, one transfer transistor formed on the substrate, and one storage capacitor electrically coupled to one of drain and source region of the transfer transistor, comprises of the following steps: (1) on the substrate forming one first insulator overlaying the transfer transistor; (2) forming one first conductive layer, passing through at least the first insulator, and electrically coupled with one of the drain and source region of transfer transistor; (3) forming one second insulator; (4) on the second insulator forming one stack layer; (5) on the stack layer sidewall forming one third insulator; (6) on the second, third insulator surface forming one fourth insulator;(7) first removing the third insulator and partial second insulator located under the third insulator, then removing the fourth insulator to form one first opening; (8) on the stack layer and second insulator surface forming one second conductive layer to fill the first opening approximately; (9) removing the second conductive layer located above the stack layer;(10) removing the stack layer; (11) forming one fifth insulator; (12) patterning the first, second conductive layer to form one second opening; (13) on the second opening sidewall forming one third conductive layer, making the third conductive layer approximately connected to the first conductive layer periphery, and one end of the second conductive layer connected to on internal surface of the third conductive layer, the first, third conductive layer constitute one trunk-type like conductive layer, the second conductive layer constitutes one branch-type like conductive layer, and the first, second, third conductive layer constitute one storage electrode of the storage capacitor; (14) removing the second, fifth insulator; (15) on the first, second, third conductive layer exposed surface forming one dielectric; (16) on the dielectric layer forming one fourth conductive layer to constitute one opposed electrode of the storage capacitor.

Description

S06993w F.DOC / 002 A7 B7 Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the Invention (丨) The present invention relates to a semiconductor memory device (Semiconductor Memory Device) with a capacitor, and particularly relates to a A memory cell structure of dynamic random access memory (Dynamic Random Access Memory; DRAM), which includes a transfer transistor (Transfer Transistor) and a tree-type storage capacitor. Figure 1 is a schematic circuit diagram of a memory cell of a DRAM device. As shown in the figure, a memory cell is composed of a transfer transistor T and a storage capacitor c. The source of the transfer transistor T is connected to a corresponding bit line BL ', the drain is connected to a storage electrode 6 (storage electrode) of the storage capacitor C, and the gate is connected to a corresponding word line wL. An opposed electrode 8 of the storage capacitor C is connected to a fixed voltage source, and a dielectric film layer 7 is provided between the storage electrode 6 and the opposite electrode 8. When the storage capacity of the traditional DRAM is less than 1M (mega = million) bits, in the integrated circuit manufacturing process, the capacitor of the second degree is mainly used to achieve the 'also known as the planar type capacitor (planar type capacitor) . A flat capacitor requires a considerable area of the semiconductor substrate to store charge, so it is not suitable for high accumulation. Highly integrated DRAM's, such as those with a storage capacity of more than 4M bits, need to be realized with three-dimensional capacitors, such as so-called stacked type or trench type capacitors. Compared with flat capacitors, stacked or trench capacitors can still get quite large when the size of the memory cell has been further reduced 4 -------..---: --- ^- Install ------ order -------- Γ \ Please read the precautions on the back before filling in this page) This paper size is applicable to China National Standard Vehicle (CNS) Α4 present grid (210X297mm) 0532TWF .DOC / 002 A7 B7 Printed and printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. The electrical capacity of the invention description (work). Nonetheless, when the memory device enters a higher degree of integration, for example, a DRAM with 64M bit capacity, a simple three-dimensional capacitor structure is no longer suitable. One of the solutions is to use so-called fin type stacked capacitors. For the related technology of fin-type stacked capacitors, please refer to the paper "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMsM, International Electron Devices Meeting, pp. 592-595, Dec. 1988" by Ema et al. The fin-type stacked capacitor is mainly its electrodes The dielectric film layer is composed of a plurality of stacked layers, extending into a horizontal fin structure in order to increase the surface area of the electrode. For DRAM type fin-type stacked capacitors, related US patents can refer to No. 5,071,783, No. 5,126,810, No. 5, No. 196,365, and No. 5,206,787. Another solution is to use the so-called cylindrical type (stack type capacitor). The related technology of the cylindrical type stack capacitor can refer to the paper "Novel Stacked Capacitor Cell for 64-Mb DRAM" by Wakamiya et al. ", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. Cylindrical stacked capacitors mainly consist of electrodes and dielectric film layers extending into a vertical cylindrical structure in order to increase the surface area of the electrodes. DRAM cylindrical stack Related US patents for capacitors can refer to No. 5,077,688. With the degree of accumulation With the increase of the break, the size of the DRAM memory cell will still be reduced again. As is known to those skilled in the art, the reduction in the size of the memory cell will reduce the capacitance value of the storage capacitor. The decrease in the capacitance value will cause the softness caused by the incidence of α rays The chance of error (softener) increases. Therefore, this artist's 5 paper scales are applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm> ----! --- r--ί-装- Please read the precautions on the back before filling this page), 1T ir. • TWF.DOC / 002 A7 B7 5. Invention description (3) Still looking for new storage capacitor structure and manufacturing method In the case where the size of the occupied plane is reduced, the desired capacitance value can still be maintained. Therefore, a main object of the present invention is to provide a semiconductor memory device having a capacitor whose capacitor has a tree structure to increase the storage of the capacitor The surface area of the electrode. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor memory element having a capacitor is provided, wherein the semiconductor memory element includes a substrate, A transfer transistor formed on the substrate and a storage capacitor are electrically coupled to one of the drain and source regions of the transfer transistor. The manufacturing method includes the following steps: a. Forming a first insulation on the substrate Layer, covering the transfer transistor; b. Forming a first conductive layer, through at least the first insulating layer, electrically coupled with one of the drain and source regions of the transfer transistor; c. Forming a second insulation Layer: d. Form a stacked layer above the second insulating layer; e. Form a third insulating layer on the side wall of the stacked layer; f. Form a fourth insulating layer on the surface of the second and third insulating layers; g. Remove first The third insulating layer and a part of the second insulating layer below the third insulating layer, and then removing the fourth insulating layer to form a first opening; h. Forming a second conductive layer on the surface of the stacked layer and the second insulating layer , The second conductive layer substantially fills the first opening; i. Remove the second conductive layer above the stacked layer; j. Remove the stacked layer; k. Form a fifth insulating layer; 1. define the first and second conductive Layer, forming a second opening; m. Forming a third conductive layer on the side wall of the second opening The third conductive layer is generally connected to the periphery of the first conductive layer, and one end of the second conductive layer is connected to the inner surface of the third conductive layer. The first and third conductive layers constitute a type of trunk-like guide. Applicable to the Chinese National Standard (CNS > A4 specification (210X 297mm) (please read the notes on the back before filling in this page)-Binding · Order Printed by the Employees Consumer Cooperative of Central Central Bureau of Economics 0532TWF.DOC / 002 Α7 Β7 Printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economy V. Description of Invention (屮) The electrical layer, the second conductive layer constitutes a kind of dendritic conductive layer, and the first, second and third conductive layers constitute a storage of the storage capacitor Electrode; η. Removing the second and fifth insulating layers; 〇. On the exposed surface of the first, second, and third conductive layers, forming a dielectric layer; and P. on the surface of the dielectric layer, forming A fourth conductive layer constitutes an opposite electrode of the storage capacitor. According to one feature of the present invention, the trunk-like conductive layer includes a lower trunk portion and an upper trunk portion. Among them, the lower trunk is electrically coupled to one of the drain and source regions of the transfer transistor, and its cross-section can be T-shaped or U-shaped; while the upper trunk is generally vertical from the lower trunk The perimeter of it extends upward. According to another feature of the present invention, after step a and before step b, the following steps are further included: forming an etch protection layer on the first insulating layer; and wherein step b further includes forming a first conductive layer through the etch protection layer A step of. According to yet another feature of the present invention, the forming method of the stacked layer in step d includes the following steps: forming a first film layer and a second film layer in sequence above the second insulating layer, wherein the second film layer is formed by It is made of conductive material, and the first film layer is made of insulating material; the first and second film layers are defined to form a stacked layer. According to another preferred embodiment of the present invention, after step a and before step b, the following steps are further included: first forming an etch protection layer on the first insulation layer, and then forming a sixth insulation layer on the etch protection layer Above; wherein step b further includes the step of forming a first conductive layer through the sixth insulating layer and the etching protective layer, and wherein step n further includes the step of removing the sixth insulating layer. 7 -i ^ · — HI i ^ Il · n In e, please read the note $ item on the back and then fill in this page) Order " This paper size is applicable to China National Standard (CNS) Λ4 specification (210X297mm) Economy 0532TWF.DOC / 002 ρ ^ η Β7 printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards V. Description of the invention (() According to yet another preferred embodiment of the present invention, the following steps are further included after step k and before step 1: Forming a fifth conductive layer: wherein step 1 further includes the step of defining a fifth conductive layer; wherein step m further includes separating the portion of the fifth conductive layer above the fifth insulating layer after forming the third conductive layer, Making the fifth conductive layer constitute a part of the dendritic-like conductive layer; and wherein step 0 further includes forming a dielectric layer on the exposed surfaces of the first, second, fourth, and fifth conductive layers. According to the present invention In another preferred embodiment, after step j and before step k, the steps from step c to step j are repeated at least once; and wherein in step m, the second conductive layers form at least two layers of dendritic like Conductive layer, these kind of dendritic conductive layer It is parallel and one of the ends is connected to the inner surface of the third conductive layer. In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a few preferred embodiments are described below in conjunction with The attached drawings are described in detail below as a brief description of the drawings: Figure 1 is a schematic circuit diagram of a memory cell of a DRAM device. Figures 2A to 21 are a series of cross-sectional views to explain a semiconductor of the present invention The first preferred embodiment of the manufacturing method of the memory element, and the first preferred embodiment of the semiconductor memory element of the present invention. Figures 3A to 3F are a series of cross-sectional views for explaining the manufacturing of a semiconductor memory element of the present invention The second preferred embodiment of the method and the second preferred embodiment of a semiconductor memory device of the present invention. Figures 4A to 4E are a series of cross-sectional views for explaining an 8 of the present invention ----:- --L-{— 装-X Please read the precautions on the back before filling in this page) The size of this paper is applicable to China National Standard (CNS) Λ4 specification (210X 297mm) Employee consumption of the Central Standards Bureau of the Ministry of Economic Affairs Printed by Zuoshe 0532TWF.DOC / 002 A7 _ B7 _. Five 'Description of the invention (&) A third preferred embodiment of a semiconductor memory device manufacturing method' and a third preferred embodiment of a semiconductor memory device of the present invention example. Figures 5A to 5F are a series of cross-sectional views for explaining a fourth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention and a fourth preferred embodiment of a semiconductor memory device of the present invention. Embodiments First, please refer to FIGS. 2A to 21 to detail the first preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention.

Please refer to FIG. 2A. First, the surface of a silicon substrate 10 is subjected to a thermal oxidation process, for example, by local oxidation of silicon (LOCOS) technology. Thus, a field oxide layer 12 is formed, and its thickness is about 3000 A (angstroms), for example. Then, the silicon substrate 10 is subjected to a thermal oxidation process to form a gate oxide layer 14 having a thickness of about 150A, for example. Then, a polycrystalline silicon layer is deposited on the entire surface of the silicon substrate 10 by a CVD (chemical vapor deposition) or LPCVD (low pressure CVD) method, and its thickness is, for example, about 2000A. In order to improve the conductivity of the polycrystalline silicon layer, phosphorus ions can be implanted into the polycrystalline silicon layer. Preferably, a refractory metal layer may be deposited, and then an annealing step is performed to form a metal polycide layer to further increase its conductivity. The refractory metal may be, for example, tungsten (Tungsten), and the deposited thickness is, for example, about 2000A. After that, the metal polycrystalline sand compound layer is patterned using traditional photolithography and lithography techniques, thereby forming gates (or word lines) WL1 to WL4 as shown in FIG. 2A. Next, for example, arsenic ions are implanted into the silicon substrate 10 to form the drain regions 16a and 9. The paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X29 * 7mm). — ≪ -install ------ order ------ ί line / please read the notes on the back first and then fill in this page)

SCS0SS I F.DOC / 002 A7 B7 Printed and printed by the Employee Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economy V. Description of Invention (Π) 16b, and source regions 18a and 18b. In this step, the word lines WL1 to WL4 are used as the mask layer, and the dose of ion implantation is, for example, about 1 × 10 5 atoms / cm2, energy (J about 70KeV. Please refer to FIG. 2B, and then An insulating layer 20 is deposited by CVD, for example, BPSG (borophosphosilicate glass), with a thickness of about 7000 a. Then, an etching protection layer 22 is deposited by CVD, for example, a silicon nitride layer (Silicon with ⑴ heart), the thickness is about 1000A. After that, using traditional photomask patterning and etching techniques, the protective layer 22, the insulating layer 20, and the gate oxide layer 14 are sequentially etched to form a storage electrode contact window (storage electrode contact holes) 24a and 24b 'respectively extending from the upper surface of the etch protection layer 22 to the surfaces of the drain regions 16a and 16b. Next, a polycrystalline silicon layer 26 is deposited on the surface of the etch protection layer 22 by CVD. In order to improve the conductivity of the polycrystalline silicon layer 26, for example, arsenic ions can be implanted into the polycrystalline silicon layer 26. As shown, the polycrystalline silicon layer 26 is filled with storage electrode contact windows 24a; 24b, and covers the etching The surface of the protective layer 22. After that, in the polycrystalline silicon layer A thick insulating layer 28 is deposited on the surface 26, for example, a silicon dioxide layer, with a thickness of about 7000 A. Please refer to FIG. 2C, and then sequentially deposit an insulating layer and a sacrificial polycrystalline silicon on the surface of the insulating layer 28 by CVD Layer, and then use the traditional mask making and etching technology to define the insulating layer and the sacrificial polycrystalline silicon layer, thus forming the insulating layer 30a; 30b and sacrificial polycrystalline silicon layer 32a; 32b as shown in the figure, wherein the insulating layer 30a; 30b is, for example, a sand nitride layer with a thickness of about 100A, and the sacrificial polycrystalline silicon layer 32a; 32b has a thickness of about 1000A. The insulating layer 3〇a and the sacrificial polycrystalline silicon layer 3a form a stacked layer 30a; 32a 'It is the actual paper. The standard is applicable to the Chinese National Standard (CNS) Λ4 specification (210 X 297 mm) _ (please read the precautions on the back before filling this page).

, 1T ”053 2TWF.DOC / 002 A7 B7 V. Description of the invention (B) Heart-shaped tube’ horizontal section can be circular, rectangular or other shapes. The preferred position of the stacked layer 30a; 32a corresponds roughly to the top of the drain region 16 &; and the insulating layer 30b and the sacrificial polycrystalline sand layer 32b are structured as another stacked layer 30b; 32b 'which is also a solid cylindrical shape, horizontal section It can be round, rectangular or other shapes. The preferred position of the stacked layers 30b; 32b generally corresponds to the top of the drain region 16b. Please refer to FIG. 2D, and then form silicon dioxide side walls (Spacers) 34a and 34b on the side walls of the stacked layers 30a; 32a and 30b; 32b, respectively. In the preferred embodiment, the silicon dioxide sidewalls 34a and 34b can be formed by the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000A; and then etching back (etchback). Thereafter, an insulating layer 36 is deposited by CVD, which is, for example, a silicon nitride layer, and has a thickness of, for example, about 2000A. Next, the insulating layer 36 is polished using a chemical mechanical polish (CMP) technique, at least until the portions above the stacked layers 303; 32 & and 30b; 32b are exposed. Please refer to FIG. 2E, and then use the stacked layers 30a; 32a, 30b; 32b and the insulating layer 36 as an etching mask to etch and remove the silicon dioxide sidewalls 34a; 34b and a part of the insulating layer 28 thereunder. Then, using the sacrificial polycrystalline silicon layer 32a; 32b as an etching mask, the insulating layer 36 is etched away to form openings 3Sa and 38b. The depth of the openings 38a and 38b can be adjusted according to actual needs, as long as it is kept at a distance from the surface of the polycrystalline silicon layer 26. Please refer to FIG. 2F, and then deposit a polycrystalline silicon layer 40 on the surface of the stacked layers 30a; 32a, 30b; 32b and the insulating layer 28, with a thickness of, for example, about 100 Å to fill the openings 38a and 38b. In order to improve the conductivity of the polycrystalline silicon layer 40, this paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) -----..--- 1--ί I 装-\ Please read first (Notes on the back and then fill out this page) Ordered by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative Printed 0532TWF.DOC / 002 A7 B7 Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative Printed 5. Description of invention (9) For example, arsenic Implanted into the polycrystalline silicon layer 40. After that, the polycrystalline silicon layer 40 is polished by mechanochemical polishing technology, at least until the upper part of the insulating layers 30a; 30b is exposed to form the polycrystalline silicon layer 40 as shown in the figure. In this step, the sacrificial polycrystalline silicon layer 32a; 32b is removed. Please refer to FIG. 2G, and then use the polycrystalline silicon layer 40 and the insulating layer 28 as etching protection layers, and remove the insulating layers 30a and 30b by wet etching. Then, an insulating layer 42 is deposited by CVD, for example, a silicon dioxide layer, and the thickness is, for example, about 2000A. Next, using traditional photomask patterning and etching techniques, the insulating layer 42, the polycrystalline silicon layer 40, the insulating layer 28 and the polycrystalline silicon layer 26 are sequentially etched to form an opening 44 to define the storage capacitor of each memory cell Storage electrode. That is, by this step, the polycrystalline silicon layers 40 and 26 are cut into sections 40a; 40b and 26a; 26b °. Please refer to FIG. 2H, and then form polycrystalline silicon sidewalls 46a and 46b on the side walls of the opening 44. In the preferred embodiment, the polycrystalline silicon sidewalls 46a; 46b can be formed by the following steps: depositing a polycrystalline silicon layer with a thickness of, for example, about 1000A; and then etching back. In order to improve the conductivity of the polycrystalline silicon layer 46a; 46b, for example, arsenic ions can be implanted into the polycrystalline silicon layer 46a; 46b. Then, the wet etching method is used, and the etching protection layer 22 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layers 42 and 28 are removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is shown by the trunk-like lower polycrystalline silicon layer 26a; 26b, the trunk-like upper polycrystalline silicon layer 46a; 46b And a dendritic polycrystalline silicon layer 40a; 40b with an L-shaped cross section. The trunk-like lower polycrystalline silicon layer 26a; 26b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and is equipped with ------ ^ ----- (please read the notes on the back first (Fill in this page again)

* 1T.i line paper size is applicable to Chinese National Mou Mou (CNS & A4 specifications (210X 297mm) 053 2TWF.DOC / 002 A7 B7 5. Description of invention (丨 (?) There is a T-shaped section. Class The trunk-shaped upper polycrystalline silicon layer 46a; the lower end of 46b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 26a; 26b, and extends roughly upward. The dendritic polycrystalline silicon layer 40a; 40b from the trunk-like 46b; the inner surface of the upper polycrystalline silicon layer 46a; 46b first extends inward in a horizontal direction and then extends downward in a vertical direction. The shape of the storage electrode of the present invention is very special, so In the specification, it is called "tree-shaped storage electrode" and the resulting capacitor is called "tree-shaped storage capacitor." Please refer to Figure 21 'and then at the storage electrode 26a, 40a, 46a; 26b, 4〇 b; 40b is formed on the exposed surface of a dielectric film layer 48a; 48b. The dielectric film layer 48a; 48b can be, for example, a silicon dioxide layer, a silicon nitride layer NO (silicon nitride / silicon dioxide) structure, ΟΝΟ (silicon dioxide / silicon nitride / silicon dioxide) structure, or any similar. , On the surfaces of the dielectric film layers 48a and 48b, a counter electrode 50 made of polycrystalline silicon is formed. The process of the counter electrode can be achieved by the following steps: depositing a polycrystalline silicon layer by CVD method whose thickness is, for example, 1000A; Then, for example, N-type impurities are added to improve its conductivity; finally, the polysilicon layer is defined by traditional mask making and etching technology to complete the storage capacitor of each memory cell of DRAM. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy -------- ^ · Install-- · (Please read the precautions on the back before filling in this page) Although the picture 21 is not shown, it should be understood by those who are familiar with this artist, the structure of the picture 21 can be based on tradition Process technology is used to produce bit lines, bonding pads, interconnection wires, isolation protection layers, packaging, etc. to complete the DRAM integrated circuit. Since these processes are not characteristic of the present invention, Therefore, it will not be repeated here. In the first preferred embodiment, the storage electrode has only one layer of dendritic electrode layer with an L-shaped cross-section. However, the present invention is not limited to this. Country (CNS) A4 size (210X297 mm)

V. Description of Invention (π) Printed by the Staff Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. The number of layers of dendritic electrode layers resembling L-shaped profiles can be two, three, or more. The next preferred embodiment will describe a storage electrode having two dendritic-like electrode layers having an L-shaped cross section. Next, referring to FIGS. 3A to 3E, a second preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is a semiconductor memory of the present invention. The second preferred embodiment of the device manufacturing method is manufactured. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2F, and then DRAM storage electrodes with different structures are manufactured by different processes. In Figs. 3A to 3E, the parts similar to those in Fig. 2F are marked with the same numbers. Please refer to FIGS. 2F and 3A, and then use the polycrystalline silicon layer 40 and the insulating layer 28 as etching protection layers, and remove the insulating layers 30a and 30b by wet etching. Afterwards, an insulating layer 52 is deposited by CVD, for example, a silicon dioxide layer, with a thickness of about 2000A. Next, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer 52 by the CVD method, and then the insulating layer and the sacrificial polycrystalline silicon layer are defined by using traditional photomask patterning and etching techniques, thus forming as shown in the figure 56b. The insulating layer 54a; 54b and the sacrificial polycrystalline silicon layer 56a; 56b. Among them, the insulating layers 54a; 54b are, for example, silicon nitride layers with a thickness of, for example, about 1000A, and the sacrificial polycrystalline silicon layer 56a; 56b has a thickness of, for example, about 1000A. The insulating layer 54a and the sacrificial polycrystalline silicon layer 56a are formed as a stacked layer Ma; 56a, which is a solid cylindrical shape, and the horizontal cross-section may be circular, rectangular, or other shapes. The stacked layer 54a; 56a is smaller than the stacked layer 3〇a in FIG. 2C; 32a, and its preferred position roughly corresponds to the top of the drain region 16a; and the insulating layer 54b and the sacrificial polycrystalline silicon layer 56b are suitable for the paper size China National Standard (CNS) A4 specification (210X297mm) (Please read the notes on the back before filling in this page) • Pack. Order WF.DOC / 002 A7 WF.DOC / 002 A7 Ministry of Economic Affairs Central Bureau of Industry and Commerce Consumer Cooperative Printed B7 ------------------------ V. Description of Invention (μ) constitutes another stacked layer 54b; 56b, which is also a solid tube, The horizontal section can be circular, rectangular or other shapes. The stacked layers 54b; 56b are smaller than the stacked layers 30b; 32b in FIG. 2C, and their preferred positions generally correspond to those above the drain region 16b. Please refer to FIG. 3B, and then form silicon dioxide sidewalls 58a and 58b on the sidewalls of the stack layers 54a; 56a and 54b; 56b, respectively. In the preferred embodiment, the silicon dioxide sidewalls 58a and 58b can be formed by the following steps: depositing a silicon dioxide layer having a thickness of, for example, about 1000 A; and then etching back. Thereafter, an insulating layer 60 'is deposited by CVD, which is, for example, a silicon nitride layer, and has a thickness of, for example, about 2000A. Let's use the mechanochemical grinding technology to grind the insulating layer 60 at least until the portions above the stacked layers 54a; 56a and 54b; 56b are exposed. Please refer to FIG. 3C 'and then use the stacked layers 54a; 56a, 54b; 56b and the insulating layer 60 as an etching mask to etch and remove the silicon dioxide sidewalls 58a; 58b and the insulating layer 52 and part of the insulating layer 28 below it. Then, using the sacrificial polysilicon layer 56a; 56b as an etching mask, the insulating layer 60 is etched away to form openings 62a and 62b. The depth of the openings 62a and 02b can be adjusted according to actual needs, as long as it is kept at a distance from the surface of the polycrystalline sand layer 26. Please refer to FIG. 3D, and then deposit a polysilicon layer 64 on the surface of the stacked layer 54a; "a, 54b; wb and the insulating layer 52, with a thickness of, for example, about 1000A to fill the openings 62a and 62b. In order to improve the polysilicon The conductivity of the layer 64 can be implanted with, for example, arsenic ions into the polycrystalline silicon layer 04. Afterwards, the polycrystalline silicon layer 64 is polished using a mechanochemical polishing technique, at least until the upper part of the insulating layers 54a; 54b is exposed , Forming a polycrystalline sand layer 64 as shown in the figure. The 15 S sheet scale is applicable to the Chinese National Standard (CNS) A4 specification (" 210X2974 ^ 7 ^ ---- _ (please read the precautions on the back before filling in this Page) 丨 Installation · Order U-line Printed by the Employee Consumer Cooperative of the Central Bureau of Standards 0532TWF.DOC / 002 A7 ___ B7 5. Description of the invention (丨 5) ~~~ 'In the step, sacrifice the polycrystalline silicon layer 56a; 56b meeting It is removed. Next, the polycrystalline sand layer 64 and the insulating layer 52 are used as etching protective layers, and the insulating layers 54a and 54b are removed by wet etching. Please refer to FIG. 3E, and then an insulating layer 66 is deposited by CVD, for example, two Silicon oxide layer, for example, about 2000A in thickness. Then use the traditional mask making and etching techniques , Sequentially etch the insulating layer 66, the polycrystalline silicon layer 64, the insulating layer 52, the polycrystalline silicon layer 40, the insulating layer 28 and the polycrystalline silicon layer 26 to form an opening 68 'to define the storage capacitor storage of each memory cell Electrodes. That is, the polycrystalline silicon layers 64, 40, and 26 are cut into several sections 64a; 64b, 40a; 40b, and 26a; 26b. Please refer to FIG. 3F, and then form polycrystals on the sidewalls of the opening 68 Silicon sidewalls 70a and 70b. In the preferred embodiment, the polycrystalline silicon sidewalls 70a; 70b can be formed in the following steps: deposit a polycrystalline silicon layer with a thickness of, for example, about 1000A; and then etch back. The conductivity of the polycrystalline silicon layer 70a; 70b, for example, arsenic ions can be implanted into the polycrystalline silicon layer 70a; 70b. Then using the wet etching method, and using the etching protection layer 22 as the etching end point, the exposed two The silicon oxide layer is removed, that is, the insulating layers 66 '52 and 28 are removed. This step completes the storage electrode of the storage capacitor of the dynamic random access memory, which is shown as a trunk-like lower polycrystalline silicon layer 26a; 26b, trunk-like polycrystalline silicon layer 70a; 70b, and two layers have an L-shaped cross section The dendrite-like polycrystalline sand layer 64a; 64b and 40a; 40b together. The trunk-like lower polycrystalline silicon layer 26a; 26b is connected to the DRAM transfer transistor drain region 16a; 16b, and has a similar T Shaped profile. The trunk-like upper polycrystalline silicon layer 70a; the lower end of 70b is connected to the trunk-like lower polycrystalline silicon layer 26a; 16 This paper size scale is applicable to the Chinese national rate (CNS) Λ4 specification (2IOX297 Seam) f Jing read the precautions on the back and then fill in this page} — installed. -Order 0532TWF.DOC / 002 A7 0532TWF.DOC / 002 A7 Printed B7 by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention (W) The periphery of 26b extends approximately vertically upward. The dendritic polycrystalline silicon layer 64a; 64b and 40a; 40b are approximately parallel, and respectively from the inner surface of the trunk-like upper polycrystalline sand layer 70a; 70b, extending inward in the horizontal direction for a distance, and then approximately Extend vertically downward. Since the subsequent process is no different from the traditional process, it will not be repeated here. If more layers of dendritic electrode layers are to be obtained, as long as described in this preferred embodiment (FIGS. 3A to 3D), the production of repeated stacked layers may be sufficient. From the cross-sectional view, the dendritic electrode layers in the first and second preferred embodiments above have two L-shaped branches. However, the present invention is not limited thereto. The dendritic electrode layers are L-shaped. There may be only one branch, and the next preferred embodiment will describe a storage electrode having a single branch-like dendritic electrode layer with an L-shaped cross section. In addition, the trunk-like lower polycrystalline silicon layers in the first and second preferred embodiments described above are solid members and have a T-shaped cross-section. However, the present invention is not limited to this, trunk-like The lower polycrystalline silicon layer may have a hollow structure to increase the surface area of the storage electrode. The next preferred embodiment will describe a structure and a method in which the trunk-like lower polycrystalline silicon layer has a U-shaped cross section to further increase the surface area of the storage electrode. Next, referring to FIGS. 4A to 4E, a third preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is a semiconductor memory of the present invention. The third preferred embodiment of the device manufacturing method is manufactured. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2A, and then uses different processes to make different structures of DRAM storage power (please read the precautions on the back before filling this page). The standard paper size is applicable to China National Standard Rate (CNS) A4 specification (210X 297mm) 0532TWF.DOC / 002 A7 B7 Printed by the Employees Consumer Cooperative of the Central Standard Rate Bureau of the Ministry of Economic Affairs Fifth, the invention description (β) pole. In Figs. 4A to 4E, the parts similar to those in Fig. 2A are marked with the same numbers. Please refer to FIG. 2A and FIG. 4A, and then a CVD method is used to deposit a planarized insulating layer 72, which is, for example, BPSG and has a thickness of, for example, about 7000 A. Then, an etch protection layer 74 is deposited by CVD, which is, for example, a silicon nitride layer, and has a thickness of, for example, about ΙοοοΑ. After that, using traditional photomask patterning and etching techniques, the etching protection layer 74, the planarization insulating layer 72, and the gate oxide layer 14 are sequentially etched to form storage electrode contact windows 76a and 76b, which are respectively formed by etching protection layers The upper surface of 74 extends to the surfaces of the drain regions 16a and 16b. Next, a polycrystalline silicon layer 78 is deposited. As shown in the figure, the polycrystalline silicon layer 78 covers the surface of the etching protection layer 74 and the inner wall surfaces of the storage electrode contact windows 76a and 76b, but does not fill the storage electrode contact windows 76a and 76b, so that the polycrystalline silicon layer 78 A hollow structure part with a U-shaped cross section. In order to increase the conductivity of the polycrystalline silicon layer 78, for example, arsenic ions may be implanted into the polycrystalline silicon layer 78. After that, a thick insulating layer 80, such as a silicon dioxide layer, is deposited on the surface of the polycrystalline silicon layer 78, with a thickness of about 7000A, for example. Then, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer 80 by CVD method, and then the traditional photomask patterning and etching techniques are used to define the insulating layer and the sacrificial polycrystalline silicon layer. 84b. The insulating layer 82a; 82b and the sacrificial polycrystalline silicon layer 84a; 84b. Among them, the insulating layer 82a; 82b is, for example, a silicon nitride layer with a thickness of, for example, about 1000A, and the sacrificial polycrystalline silicon layer 84a; 84b has a thickness of, for example, about 1000A. 84a, the insulating layer 82a and the sacrificial polycrystalline silicon layer 84a form a stacked layer 82a; 84a, and the insulating layer 82b and the sacrificial polycrystalline silicon layer 84b form another stacked layer 82b; 84b. Stacked layers 82a; 84a and 82b; 84b This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) -------- J— installed-- (Please read the precautions on the back before filling in This page) Printed 0532TWF.DOC / 002 A7 B7 by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics ---- ~ ....... — V. The description of the invention (W) is a solid cylindrical 'horizontal profile It can be round, rectangular or other shapes. The preferred positions corresponding to the center of the stacked layers 82a; 84a and 82b; 84b downward are generally both biased to one side of the drain region 16a; 16b at the same time. In this preferred embodiment, the centers of the stacked layers 82a; 84a and 82b; 84b are all biased to the right of the drain region 16a; 16b. Thereafter, silicon dioxide sidewalls 86a and 86b are formed on the side walls of the stacked layers 82a; 84a and 82b; 84b, respectively. In the preferred embodiment, the silicon dioxide sidewalls 86a and 86b can be formed by the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000 A; and then etching back. Next, an insulating layer 88 is deposited by CVD, which is, for example, a silicon nitride layer, and has a thickness of, for example, about 2,000 A. Next, the insulating layer 88 is polished using a mechanochemical grinding technique until at least the portion above the stacked layers 82a; 84a and 82b; 84b is exposed. Please refer to FIG. 4B, and then use the stacked layers 82a; 84a and 82b; 84b, and the insulating layer 88 as an etching mask to etch and remove the silicon dioxide sidewalls 86a and 86b, and a part of the insulating layer 80 thereunder. Then, the sacrificial polycrystalline silicon layer 84a; 84b is used as an etching mask, and the insulating layer 88 is etched to form openings 90a and 90b. The depths of the openings 90a and 90b can be adjusted according to actual needs, as long as they are kept at a distance from the surface of the polycrystalline silicon layer 78. Please refer to FIG. 4C, and then deposit a polycrystalline silicon layer 92 on the surface of the stacked layers 82a; 84a and 82b; 84b, and the insulating layer 80, with a thickness of, for example, about 1000A to fill the openings 90a and 90b. In order to increase the conductivity of the polycrystalline silicon layer 92, for example, arsenic ions can be implanted into the polycrystalline silicon layer 92. After that, the polycrystalline silicon layer 92 is polished by mechanochemical polishing technology, at least until the upper part of the insulating layer 82a; 82b is exposed, and the polycrystalline silicon layer is formed at 19 degrees as shown in the figure. It is suitable for China ^ Falcon (CNS) A4 specification (210X 297mmj (please read the precautions on the back before filling in this page)-Pack. Thread. 0S32TWF.DOC / 002 0S32TWF.DOC / 002 Printed A / B7 by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (η)-92. In this step, the sacrificial polycrystalline silicon layer 84a; 8 will be removed. Please refer to Figure 4D, and then use the polycrystalline silicon layer% and the insulating layer 8〇 as etching protection Layer, the green wall 82 &. 82b is removed by wet etching. Then, the insulating layer 94 is deposited by the ⑽ method, for example, the thick surface is about A. Then, using the traditional mask making and lithography techniques, The insulating layer 94, the polycrystalline sand layer 92, the insulating layer 80, and ㈣㈣ ^ are sequentially etched to form an opening 96 to define the storage electrodes of the storage capacitors of each memory cell. That is, the polycrystalline silicon layer is formed by this step 92 and 78 are cut into Ruoqian sections 92a; 92b and 78a; 78b. Please refer to Figure 4E On □ 96 _ forming a polycrystalline sand edge wall 98a and a sill on the wall. In the preferred embodiment, the polycrystalline sand edge wall _ _ can be made in the following steps, for example, about 1000A; then return to customs. In order to improve the complex晶 _98a; 98b conductivity, for example, arsenic ions can be implanted into polycrystalline complex 98a; 98b φ. ⑽ type etching method, and the etching protection layer 74 is used as the etching end point, the removal of the sand dioxide layer, that is, the removal of the insulating layer 94 and 80. By this step, the storage capacity of the storage capacitor of the dynamic random access memory is completed, which is shown by the trunk-like lower polycrystalline silicon layer 78a; Polycrystalline silicon layer 98a; 98b, and a branch-like dendritic polycrystalline sand layer 92a; 92b having only ~ branch-like l-shaped cross-section. The trunk-like lower polycrystalline silicon layer 78a; 78b is connected to the DRAM transfer circuit The crystal's drain region 16a; 16b, and has a u-shaped cross-section. The trunk-like upper polycrystalline silicon layer 98a; 98b lower end is connected to the trunk-like lower polycrystalline silicon layer 78a; 78b's periphery and It extends roughly vertically. Dendrite-like polycrystalline silicon layer 92a; 20 (Please read the precautions on the back before filling in this Page) Binding _ The size of the bound paper is applicable to China National Standard (CNS) 84 specifications (210X 297mm) 3Gq, QS5 F.DOC / 002 A7 B7_ V. Description of invention (β) 92b only has one from the cross-sectional view The branch resembling an L-shape 'from the trunk-like upper polycrystalline silicon layer 98a; the inner surface on one side of 98b' first toward the trunk-like upper polycrystalline sand layer 98a; the other After extending a distance from the inside, it then extends downward in about vertical direction. The subsequent process is no different from the traditional process, so it will not be repeated here. In the above-described first to third preferred embodiments, the dendritic electrode layers of the storage electrode all have an L-shaped cross section. However, the present invention is not limited thereto, and the dendritic electrode layer of the storage electrode may include other cross-sectional shapes. The next preferred embodiment will describe a storage electrode having a dendritic-like electrode layer having an L-like cross-section and a "one" -like cross-section. Furthermore, in the above-mentioned first to third preferred embodiments, the lower surface of the horizontal portion of the trunk-like lower polycrystalline silicon layer is in contact with the etching protection layer below it. However, the present invention is not limited to this. The next preferred embodiment is to describe the trunk-like lower polycrystalline silicon layer. The lower surface of the horizontal portion is not in contact with the etching protection layer under it, but is separated by a distance to increase storage. The surface area of the electrode. Next, with reference to FIGS. 5A to 5F, a fourth preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of a semiconductor memory device is a semiconductor memory of the present invention. The fourth preferred embodiment of the device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2A, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figs. 5A to 5F, the parts similar to those in Fig. 2A are marked with the same numbers. Please refer to Figure 2A and Figure 5A, and then deposit one by CVD method (please read the notes on the back before filling out this page). _ Printed and printed this paper The scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 0532TWF.DOC / 002 A7 B7 5. Description of the invention (11) The planarized insulating layer 100, an etch protection layer 102 and an insulating layer 104. The insulating layer 100 is, for example, BPSG with a thickness of about 7000A; the etch protection layer 102 is, for example, a silicon nitride layer with a thickness of about 1000A; the insulating layer 104 is, for example, a silicon dioxide layer with a thickness of about 1000A. After that, using traditional photomask patterning and etching techniques, the insulating layer 104, the etching protective layer 102, the planarizing insulating layer 100, and the gate oxide layer 14 are sequentially etched to form storage electrode contact windows 106a and 106b, which are formed by The upper surface of the insulating layer 104 extends to the surfaces of the drain regions 16a and 16b. Next, a polycrystalline silicon layer 108 is deposited. As shown in the figure, the polycrystalline silicon layer 108 covers the surface of the insulating layer 104 and the inner wall surfaces of the storage electrode contact windows 106a and 106b, but does not fill the storage electrode contact windows 106a and 106b, so that the polycrystalline sand layer 108 has a Hollow structural part like a U-shaped section. In order to improve the conductivity of the polycrystalline silicon layer 108, for example, arsenic ions can be implanted into the polycrystalline silicon layer 108. Please refer to FIG. 5B, and then deposit a thick insulating layer 110 on the surface of the polycrystalline silicon layer 108, which is, for example, a silicon dioxide layer with a thickness of, for example, about 7000A. Then, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer 110 by the CVD method, and then the insulating layer and the sacrificial polycrystalline silicon layer are defined by using traditional mask making and etching techniques, thus forming 114b. The insulating layer 112a; 112b and the sacrificial polycrystalline silicon layer 114a; 114b. Among them, the insulating layer 112a; 112b is, for example, a silicon nitride layer, and the thickness is, for example, about 1000A, and the thickness of the sacrificial polycrystalline silicon layer 114a; 114b is, for example, about 1000A. The insulating layer 112a and the sacrificial polycrystalline silicon layer 114a form a stacked layer 112a; 114a, and the insulating layer 112b and the sacrificial polycrystalline silicon layer 114b form another stacked layer 112b; 114b. Stacked layers 112a; 114a and 112b; 114b are solid cylindrical, horizontal section can be 22 --------- 1 __ Pack-(please read the precautions on the back before filling this page) Order: line The size of the paper printed by the Central Standard Falcon Bureau Employee Consumer Cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 0532TWF.DOC / 002 A7 B7 5. Description of the invention () mouth) round, rectangular or It is other shapes. The preferred positions corresponding to the center of the stacked layers 112a; 114a and 112b; 114b are roughly all at the same time biased to one side of the drain region 16a; 16b. In the preferred embodiment, the centers of the stacked layers 112a; 114a and 112b; 114b are all biased to the right of the drain region 16a; 16b. Thereafter, silicon dioxide sidewalls 116a and 116b are formed on the sidewalls of the stacked layers 112a; 114a and 112b; 114b, respectively. In the preferred embodiment, the silicon dioxide sidewalls 116a and 116b can be formed by the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000A; and then etching back. Next, an insulating layer Π8 is deposited by CVD, which is, for example, a silicon nitride layer and has a thickness of about 2000A, for example. Furthermore, the insulating layer Π8 is lapped using a mechanochemical grinding technique until at least the portion above the stacked layers 112a; 114a and 112b; 114b is exposed. Please refer to FIG. 5C, and then use the stacked layers 112a; 114a and 11.2b; U4b, and the insulating layer 118 as an etching mask to etch and remove the silicon dioxide sidewalls 116a and 116b, and a portion of the insulating layer 110 below it. Then, using the sacrificial polycrystalline silicon layer 114a; 114b as an etching mask, the insulating layer 118 is etched away to form openings 120a and 120b. The depth of the openings 120a and 120b can be adjusted according to actual needs, as long as it is kept at a distance from the surface of the polycrystalline silicon layer 108. Please refer to FIG. 5D, and then deposit a polycrystalline silicon layer 122 on the surfaces of the stacked layers 112a; 114a and 112b; 114b, and the insulating layer 110, with a thickness of, for example, about 1000A to fill the openings 120a and 120b. In order to improve the conductivity of the polycrystalline silicon layer 122, for example, arsenic ions can be implanted into the polycrystalline silicon layer 122. Afterwards, the polycrystalline silicon layer 122 'is polished by mechanochemical polishing technology at least until the upper part of the insulating layer 112a; 112b is exposed, forming as 23---I-—— I ”I ^ 1 (please read the back (Notes to fill out this page)

、 1T The standard paper printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs applies to the Chinese National Standard Falcon (CNS) A4 specification (2 丨 OX 297mm) 0532TWF.DOC / 002 A7 The Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 2. Description of Invention (N) The polycrystalline silicon layer 122 shown in the figure. In this step, the sacrificial polycrystalline silicon layer 114a; 114b is removed. Please refer to FIG. 5E '. Then, the polycrystalline silicon layer 122 and the insulating layer uo are used as worm-etching protective layers, and the insulating layers 112a and 112b are removed by a wet touch etching method. Thereafter, an insulating layer 124 is deposited by CVD, which is, for example, a silicon dioxide layer, and has a thickness of, for example, about 2,000 A. Then, a polycrystalline silicon layer I26 is deposited on the surface of the insulating layer 124 by CVD with a thickness of about 1000A, for example. Then, the conventional photomask patterning and etching techniques are used to sequentially etch the polycrystalline silicon layer 126, the insulating layer i24, the polycrystalline silicon layer 122, the insulating layer 110 and the polycrystalline silicon layer 108 to form an opening 127, The storage electrodes of the storage capacitors of each memory cell are defined. That is, by this step, the polycrystalline silicon layers 122 and 108 are cut into sections 122a; 122b and 108a; 108b. Please refer to FIG. 5F, and then form polycrystalline silicon sidewalls 128a and IMb on the side walls of the opening 127. In this preferred embodiment, the polycrystalline silicon sidewall spacer 128 &; 128b can be formed by the following steps: depositing a polycrystalline silicon layer with a thickness of, for example, about ιοοοΑ; and then etching back. In order to improve the conductivity of the polycrystalline silicon layer 128a; 12 Pu, for example, arsenic ions can be implanted into the polycrystalline silicon layer 128a; 128b. Afterwards, the polycrystalline silicon layer 116 is cut into sections 126a; 126b using conventional photomask patterning and etching techniques. Finally, the wet etch method is used, and the etch end point of the etched protective layer 102 is used to remove the exposed silicon dioxide layer, that is, the insulating layers m, 110 and 104 are removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is shown as a trunk-like lower polycrystalline sand layer 108a; 108b, a trunk-like upper polycrystalline sand layer 128a; 128b,- The dendritic polycrystalline sand layer with a similar profile ____ 24 scales are applicable to the Chinese national standard 2 丨 〇x297: ^ ------- (please read the precautions on the back before filling out this page). Install.-, ιτ line A7 0532TWF.DOC / 002 _____ _B7 V. Description of the invention (a) ~ 126a; 126b and a dendrite-like polycrystalline sand layer with only one L-shaped profile l〗 2a; 122b. The trunk-like lower polycrystalline sand layer 10a; 10b is connected to the drain region 10a; 16b of the transfer transistor of the DRAM, and has a U-like profile. The lower end of the trunk-like upper polycrystalline silicon layer i28a; 128b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 108a; 108b, and extends approximately vertically upward. The dendritic polycrystalline silicon layer 126a; 126b extends roughly from the trunk-like upper polycrystalline silicon layer 128a; the inner surface of the upper end of the upper end 128b inward in a horizontal direction. The dendritic polycrystalline silicon layer 122a; 122b only has an L-shaped branch from a cross-sectional view, which is roughly from the inner surface of one side of the trunk-like upper polycrystalline silicon layer 128a; 128b. The horizontal direction is toward the trunk-like upper polycrystalline silicon layer 128a; the other inner side of 128b extends a distance, and then extends downward in a vertical direction. The following subsequent processes are no different from traditional processes, so they will not be repeated here. Those skilled in the art should understand that the above-mentioned conceptual features of the preferred embodiments of the present invention can be used in addition to separate applications, and can also be used in combination, and then achieve a very wide variety of storage electrodes and storage capacitors of different structures. These storage electrodes and The structure of the storage capacitor should be within the protection scope of the present invention. It should be noted that although the drains of the transfer transistors in the drawings are all diffused region structures on the surface of the silicon substrate, the invention is not limited thereto, and any suitable drain structure can be applied to the invention, such as trench ) Jiji is an example. In addition, you should also pay attention to the shape, size, and extension angle of each component part in the diagram. It is only a schematic representation for convenience of drawing. It is in accordance with the actual situation. This paper scale is applicable to China National Standard Rate (CNS) Λ4 Specifications (210X 297mm) (Please read the precautions on the back before filling out this page)-Binding-Order DOC / 002 A7 B7 Printed by the Central Consumer Falcon Bureau of the Ministry of Economic Affairs DOC / 002 A7 B7 Difference, so it should not be used to limit the invention. Although the present invention has been disclosed above in a number of preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. (Please read the precautions on the back before filling this page)

'1T Printed by Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 26 This paper standard applies to China National Standard (CNS) Α4 specification (210Χ297mm)

Claims (1)

A8 053 2TWF.DOC / 002 B8 C8 D8 is printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 6. Patent application 1. A method for manufacturing a semiconductor memory device with a capacitor, wherein the semiconductor memory device includes a substrate A transfer transistor on the substrate and a storage capacitor are electrically coupled to one of the drain and source regions of the transfer transistor, the manufacturing method includes the following steps: a. Forming a first on the substrate An insulating layer covering the transfer transistor, b. Forming a first conductive layer, through at least the first insulating layer, and the transfer transistor is electrically coupled to one of the drain and source regions; c. forming a second insulating layer; d. forming a stacked layer above the second insulating layer; e. forming a third insulating layer on the side wall of the stacked layer; f. formed on the surface of the second and third insulating layers A fourth insulating layer; g. First remove the third insulating layer and the portion of the second insulating layer below the third insulating layer, and then remove the fourth insulating layer to form a first opening □; h. In the stacked layer and the first A second conductive layer is formed on the surface of the two insulating layers, the second conductive layer substantially filling the first opening; i. Removing the second conductive layer above the stacked layer; j. Removing the stacked layer; k. Forming a fifth insulating layer; l. Defining the first and second conductive layers to form a second opening; m. Forming a third conductive layer on the side wall of the second opening so that the third conductive layer is substantially connected to the The periphery of the first conductive layer, and one end of the second conductive layer is connected to the inner surface of the third conductive layer, the first and third 27 (please read the precautions on the back before filling in this page)- -The size of the printed paper is in accordance with the Chinese National Standard (CNS) A4 format (210X297mm) 0532TWF.DOC / 002 Α8 Β8 C8 D8 VI. Patent application The conductive layer constitutes a type of trunk-like conductive layer, and the second conductive layer constitutes a type A dendritic conductive layer, and the first and second conductive layers form a storage electrode of the storage capacitor; η. Remove the second and fifth insulating layers; 〇. In the first, second, and On the exposed surface of the three conductive layers, the shape A dielectric layer; Ρ and the surface of the dielectric layer, forming a fourth conductive layer to form an opposing electrode of the storage capacitor. 2. The manufacturing method as described in item 1 of the patent application scope, wherein the trunk-like conductive layer includes a trunk portion electrically coupled to one of the drain and source regions of the transfer transistor; and a The upper trunk portion extends approximately vertically from the periphery of the lower trunk portion. 3. The manufacturing method as described in item 2 of the patent application scope, wherein the lower trunk portion has a T-shaped cross section. 4. The manufacturing method as described in item 2 of the patent application scope, wherein the lower trunk portion has a U-shaped section. 5. The manufacturing method as described in item 4 of the patent application scope, wherein the step b includes forming the first conductive layer to have a υ-shaped cross-sectional portion. 6. The manufacturing method as described in item 1 of the patent application scope, wherein the forming method of the stacked layer in step d includes the following steps: sequentially forming a first film layer and a second layer on the second insulating layer The film layer wherein the second film layer is made of a conductive material, and the first film layer is made of an insulating material; the first film layer is defined to form the stacked layer. 28 This paper is very standard and universal τ National Standard (CNS) M specifications (210 > < 297mm (please read the precautions on the back before filling in this page) Binding · Order-Printed by the Employees Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A8 0532TWF.DOC / 002 β8 C8 D8 printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. Scope of patent application 7. The manufacturing method as described in item 1 of the scope of patent application, including after step k and before step 1 The following steps: first forming a fifth conductive layer; wherein step 1 further includes the step of defining the fifth conductive layer; wherein step m further includes separating the fifth conductive layer after forming the third conductive layer The portion above the fifth insulating layer makes the fifth conductive layer a part of the dendritic conductive layer; and wherein the step 〇 further includes the first, second, fourth, and fifth conductive layers A dielectric layer is formed on the exposed surface. 8. The manufacturing method as described in item 7 of the patent application range, wherein the fifth conductive layer has a "1" -like cross-section, and one end is connected to this type Trunk guide On the inner surface of the layer 9. The manufacturing method as described in item 1 of the patent application scope, wherein after step a and before step b, a step of forming an etching protection layer on the first insulating layer is further included; and wherein The step b further includes the step of forming the first conductive layer through the etching protection layer. 10. The manufacturing method as described in item 9 of the patent application scope, wherein the forming method of the stacked layer in the step d includes the following steps : Forming a first film layer and a second film layer in sequence on the second insulating layer, wherein the second film layer is made of conductive material, and the first film layer is made of insulating material; Definition The first and second film layers form the stacked layer. 11. The manufacturing method as described in item 9 of the patent application scope, wherein after step k and before step 1 the following steps are further included: first forming a fifth conductive layer ; The step 1 further includes the step of defining the fifth conductive layer; its 29 paper scales are applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X 297mm) -------- ^ —— 装------ 1T ------ # (Please read the notes on the back first (Fill in this page again) ABCD 053 2TWF.DOC / 002 6. In the scope of patent application, step m further includes separating the portion of the fifth conductive layer above the fifth insulating layer after forming the third conductive layer , Making the fifth conductive layer a part of the dendritic conductive layer; and wherein the step 〇 further includes forming a dielectric on the exposed surfaces of the first, second, fourth, and fifth conductive layers 12. The manufacturing method as described in item 11 of the patent application scope, wherein the fifth conductive layer has a "1" -like cross-section, and one end thereof is connected to the inner surface of the trunk-like conductive layer. 13. The manufacturing method as described in item 1 of the patent application scope, wherein after step j and before step k, the steps of step c to step j are repeated at least once; and wherein in step m, the second conductive The layers form at least two layers of dendritic conductive layers, the dendritic conductive layers are substantially parallel and one of the ends is respectively connected to the inner surface of the third conductive layer. 14. The manufacturing method as described in item 13 of the patent application scope, wherein the trunk-like conductive layer includes a trunk portion electrically coupled to one of the drain and source regions of the transfer transistor; and a The upper trunk portion extends approximately vertically from the periphery of the lower trunk portion. 15. The manufacturing method as described in item 14 of the patent application scope, wherein the lower trunk portion has a T-shaped section. 16. The manufacturing method as described in item 14 of the patent application scope, wherein the lower trunk portion has a U-shaped section. 17. The manufacturing method as described in item 16 of the patent application scope, wherein the step b includes forming the first conductive layer to have a U-shaped cross-sectional portion. 18. The manufacturing method as described in item 13 of the patent application scope, in which the 30 --------- installed ------ 1T ----- (please read the precautions on the back before filling in This page) The paper standard printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 丨 丨, y ^ vriViiii yrrr fin nii · · "-*** i -^ 1,1 0532TWF.DOC / 002 A8 B8 C8 D8 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. The scope of patent application step d. The formation of the stacked layer includes the following steps. A first film i and a second film layer are sequentially formed on the top, wherein the second film layer is made of conductive material, and the first film layer is made of insulating material; define the first and second films Layer to form the stacked layer. 19. The manufacturing method as described in item 13 of the patent application scope, wherein after step k and before step 1 the following steps are further included: first forming a fifth conductive layer; wherein step 1 further includes defining the fifth conductive layer Step; wherein the step m further includes separating the portion of the fifth conductive layer above the fifth insulating layer after forming the third conductive layer, so that the fifth conductive layer constitutes the type of dendritic conductive layer Part; and wherein the step 0 further includes forming a dielectric layer on the exposed surfaces of the first, second, fourth, and fifth conductive layers. 20. The manufacturing method as described in item 19 of the scope of the patent application, wherein the fifth conductive layer has a "one" -like cross-section, and one end thereof is connected to the inner surface of the trunk-like conductive layer of this type. 21. The manufacturing method as described in item 13 of the patent application scope, wherein after step a and before step b, a step of forming an etching protection layer on the first insulating layer is further included; and wherein step b further includes forming The first conductive layer passes through the step of etching the protective layer. 22. The manufacturing method as described in item 1 of the patent application scope, wherein after step a and before step b, the following steps are further included: first forming an etching protection layer on the first insulating layer, and then forming a sixth The insulating layer is on the etching protection layer; wherein the step b further includes forming the first conductive layer through 3 1 --------- ^ ------ 1τ ------ # (Please Please read the precautions on the back before filling in this page) The standard of this paper is applicable to the Chinese National Standard (CNS & Α4 specification (210Χ297mm) 0532TWF.DOC / 002 Α8 Β8 C8 D8 VI. The scope of patent application exceeds the sixth insulation layer and The step of etching the protective layer; and wherein the step n further includes the step of removing the sixth insulating layer. 23. The manufacturing method as described in item 22 of the patent application scope, wherein the forming method of the stacked layer in the step d The method includes the following steps: forming a first film layer and a second film layer in sequence on the second insulating layer, wherein the second film layer is made of conductive material, and the first film layer is made of insulating material Success; define the first and second film layers to form the stacked layer. The manufacturing method as described in item 22 of the patent application scope, wherein after step k and before step 1 the following steps are further included: first forming a fifth conductive layer; wherein step 1 further includes the step of defining the fifth conductive layer; Wherein the step m further includes separating the portion of the fifth conductive layer above the fifth insulating layer after forming the third conductive layer, so that the fifth conductive layer constitutes a part of the dendritic conductive layer Part; and wherein the step 〇 further includes forming a dielectric layer on the exposed surface of the first, second, fourth, and fifth conductive layers. 25. The manufacturing method as described in item 24 of the patent scope, Wherein, the fifth conductive layer has a “one” -like cross-section, and one end is connected to the inner surface of the trunk-like conductive layer. 26. The manufacturing method as described in item 22 of the patent application scope, in which After step j and before step k, the steps from step c to step j are repeated at least once; and wherein in step m, the second conductive layers form at least two layers of dendritic conductive layers, the dendritic like The conductive layer is roughly Parallel and one of the ends are respectively connected to the inner surface 32 of the third conductive layer --------- ^ ------, order -------- ^ (please read the note on the back first Please fill in this page again.) The paper standard printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) A4 (21〇 < 297mm) A8 B8 C8 D8 6. The scope of patent application. (Please read the precautions on the back before filling in this page) Binding. Thread 1 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This paper standard applies to the Chinese National Standard (CNS) A4 (210 to 297 gong)