TW306065B - Semiconductor memory device with capacitor (part 5) - Google Patents

Abstract

A semiconductor memory device with capacitor comprises of: (1) one substrate; (2) one transfer transistor formed on the substrate, and including drain and source region; (3) one storage capacitor electrically coupled to one of drain and source region of the transfer transistor; The storage capacitor comprises of: (1) one trunk-type like conductive layer with one bottom, electrically coupled to one of drain and source region of the transfer transistor, and with one upward extending part after extending one distance from the bottom with one approximately upward direction, then extending circumferentially with approximately horizontal direction; (2) one branch-type like up conductive layer electrically coupled to above of the trunk-type like conductive layer; (3) at least one branch-type like down conductive layer with one cross section like L-shape and connected to on down surface of the branch-type like up conductive layer, in which the trunk-type like conductive layer, the branch-type like up conductive layer, and type branch-type like down conductive layer constitute one storage electrode of the storage capacitor; (4) at least one trunk-type like conductive layer, with one cross section similar to L shape, whose one end connected to upper surface of the trunk-type like conductive layer, the trunk-type like conductive layer and branch-type like conductive layer constituting one storage electrode of the storage capacitor; (5) one dielectric layer formed on the truck-type like conductive layer and exposed surface of branch-type like conductive layer; (6) one upper conductive layer formed on the dielectric, constituting one opposed electrode of the storage capacitor.

Description

3Q (j〇bTD〇c / 〇 ° 2 A7 B7 Fifth, the description of the invention (I) --------. Install-(please read the precautions on the back before filling this page) This invention is about A semiconductor memory device (Semiconductor Memory Device) with a capacitor, and particularly relates to a memory cell structure of a dynamic random access memory (Dynamic Random Access Memory; DRAM), which includes a transfer transistor (Transfer Transistor) and a tree-type (tree-type) storage capacitor. Figure 1 is a circuit diagram of a memory cell of a DRAM device. As shown in the figure, a memory cell is composed of a transfer transistor T and a storage capacitor C The source of the transfer transistor T is connected to a corresponding bit line BL, the drain is connected to a storage electrode 6 (storage electrode) of the storage capacitor C, and the gate is connected to a corresponding word line WL A opposed electrode 8 of the storage capacitor C is connected to a fixed voltage source, and a dielectric film layer 7 is provided between the storage electrode 6 and the opposite electrode 8. The Central Standard Falcon Bureau employee consumption When the storage capacity of traditional DRAM is less than 1M (mega = million) bits, in the integrated circuit manufacturing process, it is mainly realized by capacitors of two-dimensional space, which is generally known as flat capacitors ( planar type capacitor). A flat type capacitor requires a considerable area of the semiconductor substrate to store charge, so it is not suitable for high accumulation. Highly integrated DRAM, such as storage capacity greater than 4M bits In addition, it is necessary to use three-dimensional capacitors, such as so-called stacked type or trench type capacitors. Compared with flat type capacitors, stacked or trench type capacitors can be in the size of the memory cell In the case of further shrinking, a considerable size of 3 papers can still be obtained. It is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210 X 297 g). Printed by the Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs. 3C60BoFDOC / 002 A7 B7 Five 2. Description of the invention. The capacitance of the invention. Nevertheless, when the memory element enters a higher degree of integration, such as DR with a capacity of 64M bits AM, the simple three-dimensional space capacitor structure is no longer applicable. One solution is to use the so-called fin-type (fin type) stacked capacitors. For the related technology of fin-type stacked capacitors, please refer to the paper "3-Dimensional" by Ema et al. Stacked Capacitor Cell for 16M and 64M DRAMs? ,, International Electron Devices Meeting, pp. 592-595, Dec. 1988. Fin-type stacked capacitors are mainly composed of a plurality of stacked layers of electrodes and dielectric film layers, which extend into a horizontal fin-like structure in order to increase the surface area of the electrodes. Related U.S. patents for DRAM type fin-type stacked capacitors may refer to Nos. 5,071,783, 5,126,810, 5,196,365, and 5,206,787. Another solution is to use so-called cylindrical type (cylindrical type) stacked capacitors. For the related technology of cylindrical stacked capacitors, please refer to the paper "Novel Stacked Capacitor Cell for 64-Mb DRAM" by Wakamiya et al., 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. The cylindrical stacked capacitor mainly has its electrode and dielectric film layer extended into a vertical cylindrical structure in order to increase the surface area of the electrode. Related U.S. patents for DRAM barrel stacked capacitors can be found in No. 5,077,688. As the degree of accumulation continues to increase, the size of the dram memory unit will still shrink. As known to those skilled in the art, as the size of the memory cell decreases, the capacitance value of the storage capacitor also decreases. The reduction of the capacitance value will lead to an increase in the chance of soft errors caused by the incidence of 0C rays. Therefore, this artist 4 please read the precautions before filling in this page). The size of the bound paper is applicable to the Chinese National Standard Falcon (CNS) Λ4% grid (2 丨 0 乂 297 公 #) 03 16TWF.DOC / 002 03 16TWF.DOC / 002 Printed by the Ministry of Economic Affairs, Central Standard Falcon Bureau S Industry and Consumer Cooperative B7 5. Description of invention (3) Still looking for new storage capacitor structures and manufacturing methods, hoping to occupy the plane occupied by storage capacitors When the size is reduced, the desired capacitance value can still be maintained. Therefore, a main object of the present invention is to provide a semiconductor memory device having a capacitor whose capacitor has a tree structure to increase the surface area of the storage electrode of the capacitor. According to a preferred embodiment of the present invention, a semiconductor memory device having a capacitor is provided. The device includes: a substrate; a transfer transistor formed on the substrate and including a drain and a source region; and a storage capacitor , Electrically coupled to one of the drain and source regions of the transfer transistor. The storage capacitor further includes: a type of trunk-like conductive layer with a bottom, electrically coupled to one of the drain and source regions of the transfer transistor, and a trunk-like conductive layer with an upward extension to After extending a distance from the bottom in a generally upward direction, it then extends around in a generally horizontal direction; at least one type of dendritic conductive layer, with an L-shaped cross section, one end of the dendritic conductive layer is connected to the On the upper surface of the trunk-like conductive layer, the trunk-like conductive layer and the dendritic-like conductive layer constitute a storage electrode of the storage capacitor; a dielectric layer is formed on the exposed surface of the trunk-like conductive layer and the dendritic-like conductive layer Upper; and an upper conductive layer formed on the dielectric layer to form a counter electrode of the storage capacitor. According to another preferred embodiment of the present invention, the trunk-like guide of the present invention I _ _ _ _ I _ taxi team ______ D, va (please read the precautions on the back before filling this page) This paper size is applicable China National Standard Falcon (CNS) Λ4 specification (210X W7 public use) 3 () (3 ° 8 · F f> gt.〇C / 002 A7 3 () (3 ° 8 · F f > 〇C / 002 A7 Printed by the Falcon Bureau Employee Consumer Cooperative _____ B7____ V. Description of the invention (^) The electrical layer is electrically coupled to one of the drain and source regions of the transfer transistor. The cross-section may be τ or u The type of dendritic conductive layer is generally a hollow cylindrical shape. According to another preferred embodiment of the present invention, a semiconductor memory device having a valley device is provided. The device includes: a substrate; a transfer transistor. On the substrate, and includes the drain and source regions; and a storage capacitor 'is electrically coupled to one of the drain and source regions of the transfer transistor. The storage capacitor further includes: a type of trunk-like conductive layer having a Bottom, electrically coupled to one of the drain and source regions of the transfer transistor, trunk-like conductive It also has an upwardly extending portion that extends a distance from the bottom in a generally upward direction and then extends around in a generally horizontal direction; at least a first type of dendritic conductive layer, including a first extension and A second extension section, one end of the first extension section is connected to the upper surface of the trunk-like conductive layer and extends upward in a vertical direction, and the second extension section extends from the first extension section in a horizontal direction Extending from the other end, the trunk-like conductive layer and the first-type dendritic conductive layer constitute a storage electrode of the storage capacitor; a dielectric layer formed on the trunk-like conductive layer and the first-type dendritic conductive layer is exposed And a conductive layer formed on the dielectric layer to form a counter electrode of the storage capacitor. According to yet another preferred embodiment of the present invention, the dendritic conductive layer of the present invention further includes a second Dendrimer-like conductive layer, which is columnar or has 6 paper scales, suitable for China National Standard (CNS) Λ4 specification (2 丨 Οχ 297mm) (Please read the notes on the back first (Fill in this page) .Install.-* 03 16TWF.DOC / 002 Λ7 B7 V. Description of invention (ί) A τ-like profile. -------- / Install-(Please read the notes on the back first Please fill in this page) According to another preferred embodiment of the present invention, the second extension of the first type of dendritic conductive layer of the present invention extends from the other end of the first extension from the inside to the outside in a substantially horizontal direction According to yet another preferred embodiment of the present invention, the second extension of the first type of dendritic conductive layer of the present invention extends substantially horizontally from the other end of the first extension from the outside to the inside. In another preferred embodiment of the present invention, the second extension of the first type of dendritic conductive layer of the present invention extends substantially horizontally from the other end of the first extension to the other side where the first extension is located Out. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are described below in conjunction with the accompanying drawings, which are described in detail as follows: = A brief description of the drawings: Figure 1 It is a circuit schematic diagram of a memory unit of a DRAM device. Figures 2A to 2H are a series of cross-sectional views for explaining a first preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a first preferred embodiment of a semiconductor memory device of the present invention. Figures 3A to 3E of the Purple Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs are a series of cross-sectional views for explaining the second preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention and a semiconductor memory device of the present invention The second preferred embodiment. Fig. 4 is a cross-sectional view for explaining a third preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a third preferred embodiment of a semiconductor memory device of the present invention. 7 This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 0X2.97 male yak) 03 I 6TWF.DOC / 002 A7 B7 5. Description of the invention (&) 5A to 5D are a series of cross-sectional views, It is used to explain the fourth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and the fourth preferred embodiment of a semiconductor memory device of the present invention. Figures 6A to 6B are a series of cross-sectional views for explaining the fifth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention and the fifth preferred embodiment of a semiconductor memory device of the present invention. Fig. 7 is a cross-sectional view for explaining a sixth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a sixth preferred embodiment of a semiconductor memory device of the present invention. 8A to 8E are a series of cross-sectional views for explaining a seventh preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a seventh preferred embodiment of a semiconductor memory device of the present invention. Embodiments First, please refer to FIGS. 2A to 2H to detail the first preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention.

Referring to FIG. 2A, first, a surface of a silicon substrate 10 is subjected to a thermal oxidation process, for example, by local oxidation of silicon (LOCOS) technology, thereby forming a field oxide layer 12 with a thickness of about 3000 A (angstroms), for example. Then, the silicon substrate 10 is subjected to a thermal oxidation process to form a gate oxide layer 14 having a thickness of about 150 A, for example. Then, using a CVD (chemical vapor deposition) or LPCVD (low pressure CVD) method, a polycrystalline silicon layer is deposited on the entire surface of the silicon substrate 10, with a thickness of, for example, about 2000 Å. In order to improve the conductivity of the polycrystalline silicon layer, phosphorus ions can be implanted into the polycrystalline sand layer. It is better to deposit another refractory metal (refractory 8 papers &degrees; suitable for China National Standard Falcon (C, NS) Λ4 specifications (210 X 297 male yak) (please read the precautions before filling this page) Outfit

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Economy Zou Central Standard Falcon Bureau Employee Consumer Cooperation Du Yin V 3〇6〇 ^ βτδ F.DOC / 002

The Ministry of Economic Affairs, Central Bureau of Standards and Staff Employee Cooperative Printed 5. The description of invention (q) metal layer, and then performed the annealing (anneal) step to form a metal polycrystalline silicon compound layer (p〇1ycide) to improve its quality. Conductivity. The refractory metal may be, for example, tungsten (Tungsten) 'deposited thickness, for example, about 2000A. After that, the traditional photomask pattern (PhotoUth〇graPhy) and etching technique are used to define the metal polycrystalline silicon compound layer ', thereby forming gates (or word lines) WL 1 to WL 4 as shown in FIG. 2A . Next, for example, arsenic ions are implanted into the silicon substrate 10 'to form drain regions 16b and source regions 18a and 18b. In this step, the word lines WL1 to WL4 are used as the mask layer, and the dose of ion implantation is, for example, about 1 × 1015 atoms / cm2, which is a huge amount of about 70 KeV. Please refer to FIG. 2B, and then deposit an insulating layer 20 by CVD, such as BPSG (borophosphosilicate glass), with a thickness of about 7000 A. Then, an etching protection layer (etching protection layer) 22 'is deposited by CVD, which is, for example, a silicon nitride layer (silicon nitride) with a thickness of about 1000A. After that, using traditional photomask patterning and etching techniques, the etching protection layer 22, the insulating layer 20, and the gate oxide layer 14 are sequentially etched to form a storage electrode contact hole 24a and its respective etching process The upper surface of the protective layer 22 extends to the surfaces of the drain regions i6a and 16b. Next, a polycrystalline sand layer 26 is deposited on the surface of the etching protection layer 22 by the cvd method. In order to increase the conductivity of the polycrystalline silicon layer 26, for example, arsenic ions may be implanted into the polycrystalline silicon layer 26. As shown in the figure, the polycrystalline silicon layer 26 is filled with storage electrode contact windows 24a and 24b, and covers the surface of the etching protection layer 22. Afterwards, a thick insulating layer 28 is deposited on the surface of the polycrystalline silicon layer 26, which is, for example, a sand dioxide layer with a thickness of about 7000 A. After the paper is too much, the midline ID (n \] c \ 4 .iL. Is applied: Γ ~ now n ^ i nn ^ 1 ^ 11 nn — ^ ϋ km —HI— a Jr (please read the precautions on the back first (Fill in this page) 03 I 6TWF.DOC / 002 A7 B7 V. Description of the invention (?) Please refer to Figure 2C, then deposit an insulating layer and a sacrificial polycrystalline silicon layer on the surface of the insulating layer 28 in order by CVD method, and then The traditional photomask plate-making and Cangworm engraving techniques are used to define the insulating layer and the sacrificial polycrystalline sand layer, thus forming a solid cylindrical insulating layer 30a; 30b and the sacrificial polycrystalline silicon layer 32a; 32b. The insulating layer 30a; 30b The horizontal cross-section of the sacrificial polycrystalline silicon layer 32a; 32b can be circular, rectangular, or other shapes. Among them, the insulating layer 30a; 30b is, for example, a silicon nitride layer, and the thickness is, for example, about 100 Α, while the sacrificial polycrystalline silicon layer 32a The thickness of 32b is, for example, about 1000 A. The insulating layer 30a and the sacrificial polycrystalline silicon layer 32a form a stacked layer 30a; 32a, the preferred position of which corresponds roughly to the top of the drain region 16a; and the insulating layer 30b and sacrificial polycrystalline The silicon layer 32b is structured as another stacked layer 30b; 32b, and its preferred position roughly corresponds to the top of the drain region 16b. Referring to FIG. 2D, then, on the side walls of the stacked layers 30a; 32a and 30b; 32b, spacers 34a and 34b are formed. In the preferred embodiment, the silicon dioxide sidewalls 34a And 34b can be formed in the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000 A; and then etching back (etchback). After that, an insulating layer 36 is deposited by CVD, which is, for example, a silicon nitride layer, with a thickness of, for example 2000A. Next, the insulating layer 36 is polished using chemical mechanical polish (CMP) technology, at least until the upper part of the stacked layers 30a; 32a and 30b; 32b is exposed. Please refer to FIG. 2E, followed by The stacked layers 30a; 32a, 30b; 32b and the insulating layer 36 are etching masks, and the silicon dioxide sidewalls 34a and 34b are etched away. After that, the stacked layers 30a; 32a, 30b; 32b and the insulating layer 36 are also suitable for wood paper size China National Standards (CNS) Λ4 specifications (210X 2 mm) (please read the notes on the back before filling out this page). -3 Printed by the Central Consortium Bureau of the Ministry of Economic Affairs, Staff and Consumers Cooperative Printed by the Central Standards Bureau of the Ministry of Economy χ · Consumer cooperative printing ^ SG6 don't r °° e / °° 2 A7 \ n Fifth, the invention description (彳) is to etch the mask, continue to etch the insulating layer 28 until the surface of the polycrystalline silicon layer 26. Then sacrifice the polycrystalline silicon layer 32a; 32b To etch the mask, the insulating layer 36 is etched away to form openings 38a and 38b. Please refer to FIG. 2F, and then deposit a polycrystalline silicon layer 40 on the surface of the stacked layers 30a; 32a, 30b; 32b and the insulating layer 28, with a thickness of, for example, about 1000A to fill the openings 38a and 38b. In order to improve the conductivity of the polycrystalline silicon layer 40, for example, arsenic ions can be implanted into the polycrystalline silicon layer 40. After that, the polycrystalline silicon layer 40 is polished using a mechanical chemical polishing technique until at least the portion above the insulating layer 30a; 30b is exposed. Please refer to FIG. 2G, and then use the polycrystalline silicon layer 40 as a mask to sequentially remove the insulating layers 30a; 30b and the underlying insulating layer 28 by wet etching. Afterwards, the polycrystalline silicon layer 40, the insulating layer 28 and the polycrystalline silicon layer 26 are sequentially etched using conventional photomask patterning and etching techniques to define the storage electrodes of the storage capacitors of each memory cell. That is, by this step, the polycrystalline silicon layers 40 and 26 are cut into sections 40a; 40b and 26a; 26b. Next, the wet etching method is used, and the etching protection layer 22 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layer 28 is removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is composed of a trunk-like polycrystalline silicon layer 26a; 26b and a dendritic polycrystalline silicon having an L-shaped cross-section Layers 40a; 40b are constructed together. The trunk-like polycrystalline silicon layer 26a; 26b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a T-shaped cross section. The dendritic polycrystalline silicon layer 40a; 40b is generally in the shape of a hollow cylinder, and its horizontal cross-section may be circular, rectangular or other shapes. The end depends on the shape of the stacked layers 30a; 32a and 30b; 32b. Dendritic complex m ^^^^ 1 i mfl ma In im -5 (read the precautions before filling in this page) This paper size is applicable to China's Threshold Standard Falcon (CNS) Λ4 specification (210 X 297 Duo) 〇3 | 6TWF DOC / 002 〇3 | 6TWF DOC / 002 Five B7 Description of the invention (丨 mouth) crystalline silicon layer 4〇a; 40b from the trunk-like polycrystalline silicon layer 26a; 26b upper surface, first After extending some distance upward in the vertical direction, it extends from the inside to the outside in the horizontal direction. Since the shape of the storage electrode of the present invention is very special, it is called "tree storage electrode" in this specification, and thus The fabricated capacitors are called "tree-type storage capacitors." Please refer to Figure 2H 'and then form a dielectric film layer 42a; 42b on the exposed surfaces of the storage electrodes 26a, 40a; 26b, and 40b respectively. The electric film layer 42a; 42b may be, for example, a silicon dioxide layer, a N0 (sand nitride oxide sand) structure of a silicon nitride layer, an ONO (sand oxide / sand nitride / silicon dioxide) structure, or any similar Then, on the surfaces of the dielectric film layers 42a and 42b, a counter electrode 44 made of polycrystalline silicon is formed The process of the counter electrode can be achieved by the following steps: CVD deposition ~ polycrystalline sand layer, the thickness of which is, for example, 1000A; and then doped with, for example, N-type impurities to improve its conductivity; Finally, the traditional photomask and etching technology to define polycrystalline Sand layer is used to complete the storage capacitors of each memory cell of DRAM. Although figure 2H is not shown, those familiar with this art should understand that the structure of figure 2] ^ can be used to make bit lines and solder pads according to traditional manufacturing techniques. ), Interconnection (interconnection) 'isolation protection layer (passivation), and packaging, etc.' to complete the DRam integrated circuit. Since these processes are not related to the characteristics of the present invention, so there are not many batches in the first preferred implementation In the example, the trunk-like polycrystalline & silicon layer is a solid member with a T-like cross-section._ In the next preferred embodiment, different structures of storage electrode stems will be formed by different processes The shape of the polycrystalline silicon layer has a hollow structure, i 2 I— I —I— I— I 1 ^ 1 -I- 士-m In [——1 ^ 1 0¾, va (please read the back (Please fill in this page again) The Employee Consumption Cooperative is printed and the tree is used to increase the storage of paper. The standard of China's National Standard (CNS) Λ4 specification (210X 297mm) is printed by the Central Bureau of Economics of the Ministry of Economy. Employee Consumer Cooperative Printing 3 ㈧ 胤 &.; DQ_ A7 __ __ B7 _ V. Description of the invention (I)) Surface area of the electrode. Next, referring to FIGS. 3A to 3E, a second preferred embodiment of a semiconductor memory device with a tree-shaped storage capacitor of the present invention will be described in detail, This preferred embodiment of the semiconductor memory device is manufactured by the second preferred embodiment of a semiconductor memory device manufacturing method of the present invention. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2A, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figs. 3A to 3E, the parts similar to those in Fig. 2A are marked with the same numbers. Please refer to FIGS. 2A and 3A, and then deposit an insulating layer 46 'by CVD, which is, for example, BPSG' with a thickness of about 7000A. Then, an etch protection layer 48 is deposited by CVD, which is, for example, a silicon nitride layer, with a thickness of about 1000A. After that, using traditional photomask patterning and etching techniques, the etching protective layer 48, the insulating layer 46 'and the gate oxide layer 14 are sequentially etched to form storage electrode contact windows 50a and 50b, which are respectively formed by etching the protective layer 48 The upper surface extends to the surfaces of the drain regions 16a and 16b. Next, a polysilicon layer 52 is deposited on the surface of the etching protection layer 48 by CVD. In order to improve the conductivity of the polycrystalline silicon layer 52, for example, arsenic ions may be implanted into the polycrystalline silicon layer 52. As shown in the figure, the polycrystalline sand layer 52 is filled with the storage electrode contact windows 50a and 50b, and covers the surface of the touch protection layer 48. After that, a thick insulating layer 54 is deposited on the surface of the polycrystalline silicon layer 52, for example, a silicon dioxide layer, with a thickness of about 7000A. Next, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer 54 by CVD method, and then the insulating layer and the sacrificial polycrystalline silicon layer are defined using traditional photomask patterning and etching techniques, thus forming as shown in the figure The insulating layer ___ I 3 This paper scale is applicable to the Chinese National Standard Falcon (eNS) Λ4 present case 2 丨 〇 乂 ^ ~~ --- m in i —1 11 ^ 1 ^^^^ 1 ^^^^ 1 ^ ^^^ 1 ^ — ^ 1 «First, J 0¾, va (please read the precautions on the back and then fill out this page) 03 16TWF.DOC / 002 A7 B7 5. Description of the invention (丨 X) 5 6 and sacrifice polymorph Sand layer 5 8. The 'insulating layer 56 is, for example, a sand nitride layer with a thickness of about 1000A, and the sacrificial polycrystalline silicon layer 58 has a thickness of about 1000A, for example. The insulating layer 56 and the sacrificial polycrystalline silicon layer 58 are structured as a stacked layer 56; the preferred position of 58 'generally corresponds to the upper portion between two adjacent storage capacitors. Please refer to FIG. 3B, and then form silicon dioxide sidewalls 6〇a and 60b on the sidewalls of the stacked layers 56; 58 respectively. In the preferred embodiment, the silicon dioxide sidewall spacers 60a and 60b can be formed by the following steps: depositing a silicon dioxide layer ' with a thickness of, for example, about 1000A; and then etching back. Thereafter, an insulating layer 62 is deposited by CVD, which is, for example, a silicon nitride layer, and has a thickness of, for example, about 2000A. Next, the insulating layer 62 is polished using a mechanochemical polishing technique until at least the portion above the stacked layers 56; 58 is exposed. Please refer to FIG. 3C, and then use the stacked layers 56; 58 and the insulating layer 62 as etching masks to etch and remove the silicon dioxide side walls 60a and 60b. After that, the stacked layer 56; 58 and the insulating layer 62 are used as the etching mask, and the insulating layer 54 is etched until the surface of the polycrystalline silicon layer 52 is continued. Then, the sacrificial polycrystalline silicon layer 58 is used as an etching mask, and the insulating layer 62 is etched away to form openings 64a and 6b. Du Yinfan, Employee Consumption Cooperation of the Central Standard Falcon Bureau of the Ministry of Economic Affairs --------! (Please read the precautions on the back before filling this page) Please refer to the 3D picture, and then deposit a polycrystalline silicon layer on the surface of the stacked layers 56; 58 and the insulating layer 54 with a thickness of about 1000A, for example, to fill the opening 64a and 64b. After that, the polycrystalline silicon layer is polished by mechanochemical polishing technology at least until the portion above the insulating layer 56 is exposed to form polycrystalline silicon layers 66a and 66b. In order to improve the conductivity of the polycrystalline silicon layer, for example, arsenic ions can be implanted into the polycrystalline sand layer. Please refer to Figure 3 E, and then use the polycrystalline silicon layer 66a; 66b as the cover screen, and the size of the paper is applicable to the Chinese national standard falcon (C'NS) Λ4 specification (210X 297 Gongqiu> 03 1 6TWF.DOC / 002 A7 Du7 printed by the consumer cooperation of the Central Standard Falcon Bureau of the Ministry of Economic Affairs B. V. Description of the invention (B) The insulating layer 56 and the underlying insulating layer 54 are sequentially removed by the wet etching method. After that, the traditional photomask is used to make and etch Technique, simultaneously etching the polycrystalline silicon layer 66a; 66b and the polycrystalline silicon layer 52 to define the storage electrode of the storage capacitor of each memory cell. That is, the polycrystalline silicon layer 66a; 66b and 52 are cut as shown in the figure Several sections 66a; 66b and 52a; 52b are shown. Then, the wet etching method is used, and the etching protection layer 48 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layer 54 is removed. This step is to complete the storage electrode of the storage capacitor of the dynamic random access memory, which is shown as a trunk-like polycrystalline silicon layer 52a; 52b and a dendritic polycrystalline silicon layer with an L-shaped cross section 66a; 66b together. The trunk-like polycrystalline silicon layer 52a; 52b is connected to The drain region 16a; 16b of the transfer transistor of DRAM has a U-shaped cross-section. The dendrite-like polycrystalline silicon layer 66a; 66b is roughly a hollow cylinder, and its horizontal cross-section can be round, rectangular or other Shape. The dendrite-like polycrystalline silicon layer 66a; 66b is roughly from the trunk-like polycrystalline silicon layer 52a; 52b's peripheral upper surface, first extending a distance upward in a vertical direction, and then outward in a horizontal direction The following subsequent processes are no different from traditional processes, so they are not repeated here. The dendritic electrode layers in the first and second preferred embodiments described above have two similar L-shaped branches, however, the present invention is not limited to this, the L-like branches of the dendritic electrode layer may have only one branch, and the next preferred embodiment will describe a single L-shaped branch-like electrode layer The storage electrode. Next, referring to FIG. 4, the third preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention, a semiconductor memory (please read the precautions before filling in this f) -Install_

、 1T K degrees of this paper is suitable for the printing of the Central Valve Standard (('NS) Λ4 specification (; Μ0Χ 297 public) 0316TWF.DOC / 002 Λ7 0316TWF.DOC / 002 Λ7 Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs B7 5. Description of the Invention (Made) This preferred embodiment of the device is manufactured by the third preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention. This preferred embodiment is shown in FIG. 3D Based on the structure of the preferred embodiment, 'the DRAM storage electrodes of different structures are made by different processes. In Fig. 4, the parts similar to those in Fig. 3D are marked with the same numbers. Please refer to Fig. 30 As shown in Figure 4, the polycrystalline silicon layer 66a; 66b is used as the mask. The insulating layer 56 and the underlying insulating layer 54 are sequentially removed by a wet etching method. Then, using traditional photomask patterning and etching techniques, at least The polycrystalline silicon layer 66a; 66b and the polycrystalline silicon layer 52 (of course, the etched insulating layer 54 can also be included) to define the storage electrode of the storage capacitor of each memory cell. That is, the polycrystalline silicon layer 52 cut into several sections 52a and 52b, and go to In addition to one of the vertical sections of the polycrystalline sand layers 66a and 66b, the poly @ silicon layers 60a and 66b have only one end connected to the polycrystalline silicon layer 52a; 52b .; ^ To use the wet etching method, and the etching protection layer 48 is At the end of the etch, the exposed silicon dioxide layer is removed, that is, the insulating layer 54 is removed. In this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed%, which is shown as a tree trunk-like The polycrystalline silicon layer 52a; 52b and—a dendritic polycrystalline silicon layer 66a; 66b having a {with a ^ -shaped cross-section. The polycrystalline silicon layer 52a; 52b connected to the DRAM transfer transistor Polar region 10a; 10b, and has a T-shaped cross-section. Dendrite-like polycrystalline sand ^ 66a; 66b from a cross-sectional view, only has an L-shaped branch, its large $ from trunk-like polymorph The upper surface of the peripheral of the silicon layer 52a; 52b, first extend a distance in the vertical direction, and then face the other in the horizontal direction __ (please read the precautions before filling this page j-Pei

、 1T This paper is applicable to the Chinese national sorrow (CNS) Λ4 said pile, 210 < 297 guru according to the scale 03 16TWF.DOC / 002 A7 B7 V. The invention description (iC) is extended. The subsequent processes are no different from traditional processes, so they will not be repeated here. In the above-mentioned first, second and third preferred embodiments, the storage electrode has only one layer of dendritic-like electrode layer having an L-shaped cross section. However, the present invention is not limited to this, and the number of layers of the dendritic electrode layer with an L-shaped cross section of the storage electrode may be two, three or more. The next preferred embodiment will describe a storage electrode having two dendritic-like electrode layers with an L-shaped cross section. Next, referring to FIGS. 5A to 5D, a fourth preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is a semiconductor memory of the present invention. The fourth preferred embodiment of the device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2F, and then DRAM storage electrodes with different structures are manufactured by different processes. In Figs. 5A to 5D, the parts similar to those in Fig. 2F are marked with the same numbers. Please refer to FIG. 2F and FIG. 5A, and then use the polycrystalline silicon layer 40 as a mask to remove the insulating layer 30a; 3Ob by wet saturation. Thereafter, an insulating layer 68, such as a silicon dioxide layer, is deposited on the surfaces of the polycrystalline silicon layer 40 and the insulating layer 28. Then, an insulating layer and a sacrificial polycrystalline silicon layer are sequentially deposited on the surface of the insulating layer 68, and then the insulating layer and the sacrificial polycrystalline silicon layer are defined by using traditional mask making and etching techniques, thereby forming an insulating layer 70a as shown in the figure ; 70b and sacrificial polycrystalline silicon layer 72a; 72b. Among them, the insulating layer 70a; 70b is, for example, a silicon nitride layer with a thickness of, for example, about 1000A, and the sacrificial polycrystalline silicon layer 72a; 72b has a thickness of, for example, about 1000A. The insulation layer 70a and the sacrificial polycrystalline silicon layer 72a are connected to each paper size. The Chinese National Standard (CNS) Λ4 specification (? 10χγ) 7 gong is applicable -------- 1 -installed ----- 1T- ------ ^ (Please read the precautions on the back before filling in this page) Ministry of Economic Affairs Central Standard_Bureau Employee Consumption Cooperation Du Yinshi 30 Maji WF.DOC / 002 A7 B7 Central Ministry of Economic Affairs Employee Consumption Cooperative printing 5. The description of the invention (吣) constitutes a stacked layer 70a; 72a, the preferred position of which corresponds roughly to the top of the drain region 16a; and the insulating layer 70b and the sacrificial polycrystalline silicon layer 72b are structured into another stacked layer 70b; 72b, the preferred position of which corresponds roughly to the top of the drain region 16b. Next, silicon dioxide sidewalls 74a and 74b are formed on the side walls of the stacked layers 70a; 72a and 70b; 72b, respectively. In the preferred embodiment, the silicon dioxide sidewalls 74a and 74b can be formed by the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000 A; and then etching back. Please refer to FIG. 5B, and then sequentially deposit an insulating layer 76 by a CVD method, which is, for example, a silicon nitride layer, and has a thickness of about 2000A, for example. Next, the insulating layer 76 is polished using a mechanochemical polishing technique until at least the portion above the stacked layers 70a; 72a and 70b; 72b is exposed. Thereafter, the stacked layers 70a; 72a, 70b; 72b and the insulating layer 76 are used as etching masks to etch and remove the silicon dioxide sidewalls 74a and 74b. After that, the stacked layers 70a; 72a, 70b; 72b and the insulating layer 76 are used as etching masks, and the insulating layers 68 and 28 are continuously etched until the surface of the polycrystalline silicon layer 26, forming openings 78a and 78b. Please refer to FIG. 5C, and then use the sacrificial polycrystalline silicon layer 72a; 72b as an etching mask to etch away the insulating layer 76. Then, a polycrystalline silicon layer 80 is deposited on the surface of the stacked layers 70a; 72a, 70b; 7 and the insulating layer 68, with a thickness of, for example, about 1000 Å to fill the openings 78a and 78b. In order to improve the conductivity of the polycrystalline silicon layer 80 ', for example, arsenic ions can be implanted into the polycrystalline silicon layer 80. After that, the polycrystalline silicon layer 80 is polished using a mechanochemical polishing technique until at least the portion above the insulating layer 70a; 70b is exposed. Next, the polycrystalline silicon layer 80 is used as a mask 'to sequentially remove the insulating layers 70a; 70b and the insulating layers 68, 28 under the wet etching method. This paper uses the Chinese national standard rate (C'NS) Λ4 specifications (210 乂 2 ^ 7 citizenship) (please read the precautions on the back before filling this page) -install 03 16TWF DQC / 002 Λ7 Η-Economy Ministry of Central Standards Bureau employee consumption cooperation printing poly five, invention description (N) Please refer to Figure 5D, and then use the traditional mask making and etching technology, in order to touch the polycrystalline sand layer 80, insulating layer 68, polycrystalline sand layer 40 , The insulating layer 28 and the polycrystalline silicon layer 26 to define the storage electrodes of the storage capacitors of each billion-unit. That is, by this step, the polycrystalline silicon layers 80, 40 and 26 are cut into several sections 80a; 80b, 40a; 40b and 26a; 2 6 b as shown. Next, the wet contact etching method is used, and the etching protection layer 22 is used as the end point of feeding, and the exposed silicon dioxide layer is removed, that is, the insulating layers 68 and 28 are removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is composed of a trunk-like polycrystalline silicon layer 26a; 26b and two layers of dendritic-like polycrystals with an L-shaped cross section as shown The silicon layer 80a; 80b and 40a; 40b are formed together. The trunk-like polycrystalline sand layer 26a; 26b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a T-shaped cross section. The two layers of dendritic polycrystalline sand layers 80a; 80b and 40a; 40b are generally parallel and are generally hollow cylindrical, and their horizontal cross-sections may be circular, rectangular or other shapes. Dendrite-like polycrystalline silicon layer 80a; 80b and 40a; 40b respectively from the upper surface of the trunk-like polycrystalline silicon layer 26a; 26b, first extending a distance upward in a vertical direction, and then inward in a horizontal direction Extend out. The following subsequent processes are no different from traditional processes, so they will not be repeated here. If more layers of dendritic electrode layers are to be obtained, as long as described in this preferred embodiment, the repeated production of stacked layers can meet the needs. In the above-mentioned first to fourth preferred embodiments, the dendritic-like electrode layers of the storage electrode all have L-like cross-sections. However, the present invention is not limited thereto, and the dendritic electrode layer of the storage electrode may include other cross-sectional shapes. Next (please read the notes on the back before filling out this page) -install

* 1T k The size of this paper has been overused by China Herald Standard U'NS) Λ4 specification (2 丨 0 X 297 g) 03 16TWF.DOC / 002 A7 B7 V. Description of the invention (&) A preferred embodiment will be described soon The storage electrode has a dendritic-like electrode layer with an L-like cross-section and a τ-like cross-section. Next, referring to FIGS. 6A to 6B, a fifth preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is a semiconductor memory of the present invention. Manufactured in the fifth preferred embodiment of the device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2F, and then DRAM storage electrodes with different structures are manufactured by different processes. In Figures 6A to 6B, parts similar to those in Figure 2F are marked with the same numbers. Please refer to FIG. 2F and FIG. 6A, and then use the polycrystalline silicon layer 40 as a mask to remove the insulating layer 30a; 30b by wet etching. Then, an insulating layer 82, such as a silicon dioxide layer, is deposited on the surfaces of the insulating layer 28 and the polycrystalline silicon layer 40 by CVD. Afterwards, using conventional photomask patterning and etching techniques, the insulating layer 82, the polycrystalline silicon layer 40 and the insulating layer 28 are etched sequentially until the surface of the polycrystalline silicon layer 26 to form openings 84a and 84b. The preferred positions of the openings 84a and 84b generally correspond to the areas above the drain regions 16a and 16b, respectively. Next, a polycrystalline silicon layer 86 is deposited on the surface of the insulating layer 82 by CVD, with a thickness of, for example, about 1000 Å to fill the openings 84a and 84b. To increase the conductivity of the polycrystalline silicon layer 86, for example, arsenic ions can be implanted into the polycrystalline silicon layer 86. Please refer to FIG. 6B, and then use the traditional mask making and etching techniques to sequentially touch the polycrystalline sand 86, the insulating layer 82, the polycrystalline sand layer 40, the insulating layer 28 and the polycrystalline silicon layer 26 to define each memory Unit storage capacitor 20 This paper standard is applicable to China National Standard Falcon (CNS) Λ4 present grid (210Χ297mm) (please read the precautions on the back before filling this page) Manufacturing 3 1 6TWF.DOC / 002 A7, ------------ Η? ____ Description of the invention (丨 9 ~-The storage electrode. That is to say, this step will be the polycrystalline silicon layer%, 40% and Into a number of sections 86a; 86b, 40a; 40b cutouts as shown in the figure "• pt- tu 26h ° and then use the wet etching method, and the etching protection layer π 舄 etching will eventually expose the exposed silicon dioxide layer Remove, that is, remove the insulating layer 82 " ^, 28. This step is to complete the storage electrode of the storage capacitor of the dynamic random access memory, which is shown in the figure by the trunk-like polycrystalline silicon layer 26a; ° , ~ Dendrite-like polycrystalline silicon layer with a L-like cross-section 4〇a; 4〇b with a T-like cross-section The dendritic polycrystalline silicon layer 80a; 80b is composed of. The trunk-like polycrystalline silicon layer 20a; 26b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a D-shaped cross section. Dendrite-like polycrystalline sand layer 4〇a with a ^ -shaped mouth 丨 J plane; 40b is generally hollow cylindrical, and the horizontal cross-section may be circular, rectangular or other shapes. Dendrite-like polycrystalline silicon layer 40a; 40b from The upper surface of the trunk-like polycrystalline silicon layer π ”261) first extends a distance approximately upward in the vertical direction, and then extends from the interior to the exterior in a horizontal direction. A dendritic polycrystalline crystal with a T-shaped profile Silicon layer 80a; the vertical section of 80b is also roughly hollow cylindrical, and its horizontal section can also be round, rectangular or other shapes. Dendritic-like polycrystalline silicon layer 80a; 80b from trunk-like polycrystalline silicon layer 26a; The upper surface of 26b first extends upward in a vertical direction, and then extends around in a horizontal direction. In the next preferred embodiment, storage electrodes with different structures will be formed by different processes. The storage electrode structure of the embodiment is very similar to the fifth The structure of the preferred embodiment 'the difference is only in the part of the dendritic polycrystalline silicon layer, that is, the fifth preferred embodiment has a τ-like profile' and the next preferred embodiment has a columnar structure (Please read the precautions on the back and then fill in this page) 丨 Installed '* vs Printed by the Central Consumer Standard Falcon Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative. The paper size is applicable to China National Standard (CNS) Λ4 present grid (210x 297 ) The Ministry of Economic Affairs Central Standardization Bureau employee consumption cooperation Du Yin 1i 306G65wfd V. Description of invention () (? ) This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 6A, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figure 7, parts similar to those in Figure 6A are marked with the same numbers. Please refer to FIG. 6A and FIG. 7, and then use the mechanochemical grinding technology to grind the polycrystalline silicon layer 86 until at least the portion above the insulating layer 82 is exposed to form a columnar polycrystalline silicon layer as shown 88a and 88b. After that, using the wet etching method and using the polycrystalline silicon layer 40 as a mask, the exposed silicon dioxide layer is removed, that is, the entire insulating layer 82 and part of the insulating layer 28 are removed. Then, using conventional photomask patterning and etching techniques, the polycrystalline silicon layer 40, the insulating layer 28 and the polycrystalline silicon layer 26 are etched in sequence until the surface of the protective layer 22 is etched to define the storage capacitors of the memory cells Storage electrode. That is, by this step, the polycrystalline silicon layers 40 and 26 are cut into several sections 4〇a; 4b and Ma; Mb as shown in the figure. Then, the wet etching method is used, and the protective layer 22 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layer 28 is removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is composed of a trunk-like polycrystalline stone evening layer 26a; 26b '— dendritic-like polycrystal with an L-shaped cross section as shown in the figure The silicon layer 40a; 40b is composed of a columnar dendritic polycrystalline silicon layer 88a; 88b. The trunk-like polycrystalline silicon layer 26a; 26b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a T-shaped cross section. The dendrite-like polycrystalline silicon layer 40a; 40b having an L-shaped cross-section is substantially a hollow cylinder, and its horizontal cross-section may be circular, rectangular, or other shapes. Dendrite-like polycrystalline silicon layer 4〇a; 4〇b from the trunk-like polycrystalline silicon layer 26a; 2 cents on the upper surface, first hang about 22 -------- ί _ 装 --- --- book ------ f'iK (please read the precautions on the back before filling in this page) This paper size is applicable to China National Geographic (CNS) Λ4 specifications (ΉΟ < 297 public flood) 03 1 6TWF .DOC / 002 Λ7 03 1 6TWF.DOC / 002 Λ7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ___ B7 Five'Instructions for Invention () 丨) After extending a distance in the vertical direction, then from the inside to the outside in a horizontal direction Stretch out. The column-like dendritic polycrystalline silicon layer 88a; 88b can have a horizontal cross-section of a circular, rectangular, or other shape and extend from the upper surface of the trunk-like polycrystalline silicon layer 26a; 26b, extending upward in a vertical direction Out. In the above-mentioned first to sixth preferred embodiments, the lower surface of the horizontal portion of the trunk-like polycrystalline silicon layer is in contact with the etch protection layer underneath, and all of the complexes above the stacked layer are made by CMP technology The crystalline silicon layer is removed and cut off. However, the present invention is not limited to this. The next preferred embodiment is to describe that the lower surface of the horizontal portion of the trunk-like polycrystalline silicon layer is not in contact with the etch protection layer under it, but is separated by a distance to increase the storage electrode. The practice of the surface area. At the same time, the process of cutting the polycrystalline silicon layer above the stacked layer using conventional photomask patterning and etching techniques will also be described. Next, referring to FIGS. 8A to 8E, a seventh preferred embodiment of a semiconductor memory element having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory element is a semiconductor memory of the present invention. The seventh preferred embodiment of the device manufacturing method is manufactured. The present preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2A ', and then DRAM storage electrodes of different structures are manufactured by different processes. In Figs. 8A to 8E, the portions similar to those in Fig. 2A are marked with the same numbers. Please refer to Figs. 2A and 8A 'and then sequentially deposit an insulating layer 90, an etching protection layer 92 and an insulating layer 94 by CVD. The insulating layer 90 is, for example, BPSG 'with a thickness of about 7000A. The etching protection layer 92 is, for example, silicon nitride 23 r · -------- 11 * ^ ______ 丁 ____— 1 ^ ^ (please read the precautions on the back before filling out this page) China National Standard Falcon (CNS) Λ4 specification (2 丨 OX 297 public) A7 B7 0316TWF.DOC / 002 V. Invention description (/)) layer, thickness about 1000A. The insulating layer 94 is, for example, a silicon dioxide layer and has a thickness of about wooA. After that, using traditional photomask patterning and etching techniques, the insulating layer 94, the etching protective layer 92, the insulating layer 90 and the gate oxide layer I4 are sequentially etched to form the storage electrode contact windows 96a and 96b. The upper surface of 94 extends to the surfaces of the drain regions 16a and 16b. Next, a polycrystalline silicon layer is deposited on the surface of the insulating layer 94 and the storage electrode contact windows 96a; 96b. Then use traditional photomask patterning and etching techniques to define the polycrystalline sand layer to form the polycrystalline sand layer as shown in the figure. 98 ° In order to improve the electrical conductivity of the polycrystalline sand layer, for example, arsenic ions can be implanted into the polycrystalline silicon layer. As shown in the figure, the polycrystalline silicon layer 98 is filled with the storage electrode contact windows 96a; 96b 'and covers the surface of the insulating layer 94. After that, an insulating layer 100 is deposited on the surface of the polycrystalline cutting layer 98, which is, for example, a layer of sand dioxide, and the thickness is, for example, about 7000A. Please refer to FIG. 8B, and then sequentially deposit an insulating layer and a sacrificial polycrystalline silicon layer on the surface of the insulating layer 100, and then define the insulating layer and the sacrificial polycrystalline sand layer using traditional photomask patterning and etching techniques, thus forming The solid cylindrical insulating layer 10 2a; 10 2b and the sacrificial polycrystalline silicon layer 104a; 104b shown in the figure. The insulating layer 102a; 102b and the sacrificial polycrystalline silicon layer 104a; HMb may have a circular cross section, a rectangular shape, or other shapes. Where the 'insulating layer 102a; 102 d is for example a silicon nitride layer with a thickness of, for example, about 1000A' and the sacrificial polycrystalline silicon layer 104a; the thickness of 104b is for example about 1000A. The insulating layer 102a and the sacrificial polycrystalline silicon layer 104a are structured as a stacked layer 102a; the preferred position of l04a 'roughly corresponds to the top of the drain region 16a; and the insulating layer 102b and sacrificial polycrystalline silicon The layer 104b is structured as another stacked layer 102b; 104b 'its preferred position roughly corresponds to the top of the drain region 16b. Then at the stacking layers 102a; 104a 24 (please read the precautions on the back before filling out this page), tr buck. The Ministry of Economic Affairs Central Standards Bureau staff consumption cooperation du printed this paper standard is applicable to the national valve country falcon (CNS > ΛΑcurrent grid (210x297 gongs) 03 1 6TWF.DOC / 002 Λ7 B7 V. Description of the invention (θ) and 102b; silicon dioxide side walls l〇6a and l〇6b are formed on the side walls of l〇4b. In a preferred embodiment, the silicon dioxide sidewalls 106a and 106b can be formed by the following steps: depositing a silicon dioxide layer with a thickness of, for example, about 1000A; and then etching back. After that, an insulating layer 108 is deposited by CVD. For example, the thickness of the silicon nitride layer is about 2000 A. Next, the insulating layer 108 is polished using a mechanochemical grinding technique until at least the portion above the stacked layers 102a; 1043 and 102b; 104b is exposed. Please refer to section 8C, and then using the stacked layers 102a; 104a, l02b; 104b and the insulating layer 108 as an etch mask, etched and removed the silicon dioxide side walls 1 〇6a and 106b. After the 'still with stacked layers 102a; l〇4a, 102b; l〇4b and insulating layer l〇8 are etching mask, continue to etch insulation 100 up to the surface of the polycrystalline sand layer 98. Then the sacrificial polycrystalline sand layer 104a; 104b is used as an etching mask, and the insulating layer 108 is removed by the worm worm etching to form the openings 11a and 110b. Please refer to the 8D figure, and then 104a, 104b and 104b and the surface of the insulating layer 100 are deposited a polycrystalline silicon layer 112, with a thickness of, for example, about 10000A, to fill the openings 38a and 38b. In order to improve the polycrystalline cut layer The conductivity of 112 'can be implanted with arsenic ions, for example, into the polycrystalline silicon layer 112. Afterwards, the polycrystalline silicon layer n2 and the sacrificial polycrystalline silicon layer l04a are defined using conventional photomask patterning and etching techniques; 104b' separate The portion located above the insulating layer 10 2a; 丨 〇 2b, forming the structure shown in the figure. Said referring to the table 8E, and then with the polycrystalline sand layer Π2 and sacrificial polycrystalline sand layer 104a; The mask is etched in sequence using wet etching to expose the exposed silicon nitride layer and silicon dioxide layer, that is, to remove the insulating layers l02a; i〇2b and the underlying insulating layer 100. After that, using conventional light Mask-making and etching technology __ 2 5 copies of paper &degree; Zhongguanjia County (CNS) Λ4 specification (21GX 297 gong |) " ' " (Please read the precautions on the back before filling the nest page) 丨 Installed.-= 0 Printed by the Central Bureau of Economics and Staff Employee Consumer Cooperative 03 1 6TWF.DQC / 002 Λ7 03 1 6TWF.DQC / 002 Λ7 Economy The Ministry of Central Standards Bureau employee consumer cooperative printed the B7 5 'invention description ($) technique, in order to etch the polycrystalline silicon layer II2, the insulating layer 100 and the polycrystalline silicon layer 98 to define the storage electrode of the storage capacitor of each memory cell . That is, by this step, the polycrystalline silicon layers 112 and 98 are cut into sections 112a; 112b and 98a; 98b. Next, the wet etching method is used, and the etching protection layer 92 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layers 100 and 94 are removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is shown as a trunk-like polycrystalline silicon layer 98a; 98b and a dendritic polycrystalline silicon with a T-like cross-section The layers 112a; 112b are formed together. The trunk-like polycrystalline silicon layer 98a; 98b is connected to the drain region 16a of the transfer transistor of the DRAM; 16b, which has a T-shaped cross-section, and the horizontal lower surface and the upper surface of the etch protection layer 92 remain A distance to increase the surface area of the storage electrode. The dendrite-like polycrystalline silicon layer 112a; 112b is generally hollow and cylindrical, and its horizontal cross-section may be circular, rectangular, or other shapes, and from the trunk-like polycrystalline silicon layer 98a; the upper surface of 98b 'is first approximately vertical After extending a certain distance upwards, it then extends around in a horizontal direction. Those skilled in the art should understand that the above-mentioned conceptual features of the preferred embodiments of the present invention can be used in addition to separate applications, and can also be used in combination to achieve a very wide variety of storage electrodes and storage capacitors with different structures. The structure of the storage capacitor should be within the protection scope of the present invention. · It should be noted that although the drains of the transfer transistors in the drawings are all diffused region structures on the surface of the silicon substrate, the present invention is not limited to this, any suitable drain structure can be applied to the present invention, such as trench ( trench) Jiji is 26 i --III-ILII If II n IT n II -I ___ ^ Private J3. 、-° 矣 (Please read the precautions on the back before filling in this page) Ping (CNS) Λ4 nigger (2 丨 Οχ 297 male yak) 03 16TWF.DOC / 002 A7 B7 V. Description of the invention (#)-Example. Furthermore, it should also be noted that the shapes, sizes, and angles of extension of each component part in the drawings are schematic representations for convenience of illustration only, and may differ from the actual situation, so they should not be used to limit the present invention. Although the present invention has been disclosed above in a number of preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. (Please read the precautions on the back and then fill out this page) —Installation_Order》 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 27 copies of the paper (eNS) Λ4 specification (2UVx] 97 Gongchu)

Claims (1)

DOC / 002 ABCD Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. Patent application 1. A semiconductor memory device with capacitors includes: a substrate; a transfer transistor formed on the substrate and including the drain and A source region; and a storage capacitor electrically coupled to one of the drain and source regions of the transfer transistor, the storage capacitor includes a type of trunk-like conductive layer having a bottom, electrically coupled to the transfer On one of the drain and source regions of the transistor, the trunk-like conductive layer has an upward extension in a generally upward direction, extending a distance from the bottom, and then going in a horizontal direction Extending around, at least one kind of dendritic conductive layer has an L-shaped cross section, one end of the kind of dendritic conductive layer is connected to the upper surface of the kind of trunk-like conductive layer, the kind of trunk-like conductive layer and the kind of branch The conductive layer constitutes a storage electrode of the storage capacitor, a dielectric layer is formed on the exposed surface of the trunk-like conductive layer and the dendritic conductive layer, and Upper conductive layer formed on the dielectric layer constituting the storage capacitor to a counter electrode. 2. The semiconductor memory device as described in item 1 of the patent application, wherein the trunk-like conductive layer of this type has a T-like cross-section. 3. The semiconductor memory device as described in item 1 of the patent application, wherein the trunk-like conductive layer of this type has a U-like cross-section. 4. For the semiconductor memory device mentioned in item 2 of the patent application scope, 28 paper standards are applicable to the Chinese National Standard (CNS). M specifications (; M〇X 297 public f) ^ ~ ^ ------- JI installation --- order ----- first line (please read the precautions on the back and then fill out this page) 0316TWF DOC / 002 Α8 Β8 C8 D8 Central China Bureau of Economic Affairs Employee consumption cooperation du printing 6. Application The scope of the patent is that the end of the dendritic conductive layer is connected to the upper surface of the trunk conductive layer. 5. The semiconductor memory device as described in item 3 of the patent application, wherein the end of the dendritic conductive layer is connected to the upper surface of the trunk conductive layer. 6. The semiconductor memory device as described in item 1 of the patent application, wherein the dendritic conductive layer is generally in the shape of a hollow cylinder. 7. The semiconductor memory device as described in item 1 of the patent application scope, wherein the storage capacitor includes two substantially parallel dendritic conductive layers, each of which has an L-shaped cross-section, and one end is connected On the upper surface of such a trunk-like conductive layer. 8. A semiconductor memory device having a capacitor includes: a substrate; a transfer transistor formed on the substrate and including drain and source regions: and a storage capacitor electrically coupled to the transfer transistor On one of the drain and source regions, the storage capacitor includes a trunk-like conductive layer with a bottom, electrically coupled to one of the drain and source regions of the transfer transistor, the trunk-like The conductive layer further has an upwardly extending portion 'in a generally upward direction, extending a distance from the bottom' and then extending around in a horizontal direction, at least a first type of dendritic conductive layer, including a first Extension section and a second extension section 'One end of the first extension section is connected to the trunk guide 29 of this type (please read the precautions on the back before filling in this page) -install_ * 1Τ line 21 Ox Chuan 7 male mackerel ) Printed by the Ministry of Economic Affairs of the Central Standardization Bureau Staff Consumer Cooperative 3 06 tear F.DOC / 002 B8 C8 D8 VI. Patent application The upper surface of the electrical layer extends approximately vertically upwards, the second extension is roughly With water In the horizontal direction, extending from the other end of the first extension, the trunk-like conductive layer and the first dendritic conductive layer constitute a storage electrode of the storage capacitor, and a dielectric layer is formed in the trunk-like shape A conductive layer and the exposed surface of the first type of dendritic conductive layer, and an upper conductive layer are formed on the dielectric layer to form an opposite electrode of the storage capacitor. 9. The semiconductor memory device as described in item 8 of the patent application scope, wherein the trunk-like conductive layer of this type has a T-like cross-section. 10. The semiconductor memory element as described in item 8 of the patent application scope, wherein the trunk-like conductive layer of this type has a U-like cross-section. 11. The semiconductor memory element as described in item 8 of the patent application scope, wherein the first type of dendritic conductive layer is generally in the shape of a hollow cylinder. 12. The semiconductor memory device as recited in item 11 of the patent application range, wherein the second extension of the first type of dendritic conductive layer is substantially horizontal from the other end of the first extension from inside to outside Stretch out. 13. The semiconductor memory device as described in item 11 of the patent application scope, wherein the second extension of the first type of dendritic conductive layer is substantially horizontal from the other end of the first extension Extend inward. 14. The semiconductor memory device as described in item 11 of the patent application scope, wherein the second extension of the first type of dendritic conductive layer is substantially horizontal from the other end of the first extension to the first The other side where an extension is located extends out. 30 -------- ί I 装-(Please read the precautions on the back before filling in this page) Threading " ^ Paper size used China National Standards_ (CNS) Λ4 坭 格 （2Ι0χ Μ7 公堂) " 03 I6TWF DOC / 002 Λ8 B8 C8 D8, patent application scope 15. The semiconductor memory device as described in item 8 of the patent application scope, wherein the storage capacitor further includes a second type of dendritic conduction One end of the layer is connected to the upper surface of the trunk-like conductive layer; and the dielectric layer is formed on the exposed surface of the trunk-like conductive layer and the first and second dendritic conductive layers. 16. The semiconductor memory device as described in item 15 of the patent application scope, wherein the second type of dendritic conductive layer has a T-like cross-section. 17_ The semiconductor memory device as described in item 15 of the patent application range, wherein the second type of dendritic conductive layer is in the form of a column, extending approximately vertically from the upper surface of the trunk-like conductive layer of this type . 18. The semiconductor memory device according to item 11 of the patent application scope, wherein the storage capacitor includes two substantially parallel first-type dendritic conductive layers, and one end of each first-type dendritic conductive layer is connected to This type of trunk-like conductive layer is on the upper surface.丨 Binding Information (Please read the precautions on the back before filling in this page) Printed by the Ministry of Economic Affairs, Central Standard Staff and Workers ’Consumer Cooperatives This paper standard is universal Chinese national standard (CNS) Λ4 present grid (210X297 Gongluan)