GB2231718A - A dynamic random access memory cell and method of making the same - Google Patents
A dynamic random access memory cell and method of making the same Download PDFInfo
- Publication number
- GB2231718A GB2231718A GB8926627A GB8926627A GB2231718A GB 2231718 A GB2231718 A GB 2231718A GB 8926627 A GB8926627 A GB 8926627A GB 8926627 A GB8926627 A GB 8926627A GB 2231718 A GB2231718 A GB 2231718A
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- GB
- United Kingdom
- Prior art keywords
- trench
- conductivity type
- source region
- dram cell
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
- H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Abstract
A DRAM and a method of making a DRAM cell capable of increased storage capacity and of utility for large-scale integration is disclosed. The method provides forming on a semiconductor substrate 40 of a first conductivity type, a DRAM cell having stacked and trench capacitors and a transistor of a second conductivity type opposite to the first conductivity type. A polycrystalline silicon layer 56 forms a cell node of the stack capacitor and is coupled to a source region 53 of the transistor. A cell node of the trench capacitor is coupled to the source region 53 of the transistor through an N-type diffusion region 60 around the trench that is formed between the source region 53 and a field oxide layer 46. The trench capacitor is disposed over the stack capacitor, and the capacitors are coupled in parallel. A second polycrystalline silicon layer 64 filling the inside of the trench, forms the second common plate of the two capacitors. <IMAGE>
Description
A DYNAMIC RANDOM ACCESS MEMORY CELL AND
METHOD OF MAKING THE SAME
The present invention relates to a dynamic RAM (DRAM) cell, and a method of making the same.
Typically, a DRAM cell comprises one transistor in which the drain-source channel is coupled between a bit line and a cell node, and one storage capacitor which is connected between the cell node and cell plate.
Reference will now be made to Figure 1 of the accompanying drawings, which is a cross-sectional view showing a preferred embodiment of a known trench capacitor cell.
As shown in Figure 1, a known trench capacitor cell comprises a N-channel MOS transistor, a diffusion layer 8, a dielectric film 9 and a polycrystalline silicon layer 11. The N-channel MOS transistor comprises a source region 3 which is adjacent to a field oxide 10 formed on the surface of a p-type substrate 1, a drain region 2 separated through channel, and a word line 5 formed by a polycrystalline silicon of a conductivity type being grown on a gate oxide 4 on the substrate between the drain 2 and source region 3. The diffusion layer 8 is formed on the outside substrate of a trench 7, and utilized as a cell node by contact with the source region 3. The dielectric film 9 is formed on the inside of the trench 7. The polycrystalline silicon layer 11, on the dielectric film 9, is used as a cell plate by filling up the trench.Also, adjacent word line 6, being a gate electrode of an adjacent memory cell, is formed on a portion of field oxide 10 by being separated from the polycrystalline silicon layer 11 by an insulating film 12.
In the trench capacitor described above, a trench must be deeply dug in order to have a large storage capacity, so a transistor is formed after forming the capacitor, and a diffusion layer formed under the trench is extended by continuous process steps. If large scale integration of DRAM memory cells causes the distance between trenches to be decreased, the distance between diffusion regions of adjacent cells become very narrow, so that there is a problem that information stored in the capacitor is lost due to leakage current flowing through a substrate.
Reference will now be made to Figure 2 of the accompanying drawings which is a cross-sectional view showing a preferred embodiment of a known stack capacitor.
As shown in Figure 2, a known stack capacitor comprises an N-channel MOS transistor, a dielectric film 29 and a polycrystalline silicon layer 31. The N-channel
MOS transistor consists of a source region 22 which is adjacent to a field oxide 30, formed over a p-type semiconductor substrate 20, a drain region 21 separated through channel, and a word line 24 formed by a polycrystalline silicon of a conductivity type being grown over a gate oxide 23 on the substrate between the drain region 21 and source region 22. The dielectric film 29, made of dielectric material, is formed on the inside surface of a trench 26 which is formed in the substrate under the source region 22. The polycrystalline silicon layer 31, formed over the dielectric film 29, is used as a cell plate layer.Also, word lines 24, 25 and a polycrystalline silicon 27, used as a cell node layer, are separated by an insulating film 28, and a bit line 35, separated by an insulating film 34 over the polycrystalline silicon 31 utilized as cell plate layer, is connected with drain region 21 through an opening hole. The insulation film 34 consists of oxide film 32 and BPSG film (Boro-phospho Silicate Glass) 33.
However a stack capacitor described above has a small rate of increase in storage capacity according to extension of area by trench process due to a fixed thickness of a polycrystalline silicon layer used as the cell node layer. In addition, if a trench hole is small, it may be difficult to deposit polycrystalline silicon for forming a cell plate over the inside trench.
Preferred embodiments of the present invention aim to provide a method of making a DRAM cell which may be capable of increasing storage capacity and for use in large-scale integration.
According to a first aspect of the present invention, there is provided a DRAM cell which comprises a field oxide formed on the surface of a semiconductor substrate of a first conductivity type in order to isolate between adjacent cells, a drain and source region of a second conductivity type opposite to the first conductivity type, separated from themselves by a given distance on the substrate, a gate oxide on the substrate between said source and drain region, and word lines of a conductivity type being grown on said field oxide, said
DRAM cell further comprising::
a trench formed under a given portion between said source region and field oxide, a diffusion layer connected with said source region by ion-implanting impurity of a second conductivity type into the substrate of said outside trench;
a first polycrystalline silicon connected with said source region and isolated from said word lines by a first insulating film;
a dielectric film formed on the inside surface of said trench and a first polycrystalline silicon;
a second polycrystalline silicon formed on the dielectric film so as to fill the inside of said trench; and
a bit line connected with said drain region through an opening hole and isolated by a second insulating film.
Preferably, said first insulating film is oxide film. Preferably, said first polycrystalline silicon and diffusion layer of impurity are connected to the source region in parallel.
According to a second aspect of the present invention, there is provided a method of making a DRAM cell having a stacked and a trench capacitor and a transistor of a second conductivity type opposite to a first conductivity type on a semiconductor substrate of the first conductivity type, comprising the steps of::
forming a thick field oxide on a portion of the surface of said semiconductor substrate, a source region of a second conductivity type which is adjacent to said field oxide, and a drain region of the second conductivity type separated through channel region on the surface of said semiconductor substrate, a gate oxide on the surface of said source region, channel and drain region, and then word lines of the conductivity type over said channel region and a given region of said field oxide, respectively;
forming a first insulating film on said word lines, exposed gate oxide and field oxide, and an opening hole at the first insulating film and gate oxide overlaying said source region;
forming a first polycrystalline silicon on said source region to fold with portions of said word lines; ;
forming a trench over the source, substrate and first polycrystalline silicon formed into said opening hole, and a diffusion layer of a second conductivity type on the outside substrate of said trench in order to be connected with said source region, and then a dielectric film on said first insulating film, first polycrystalline silicon and the surface of trench;
forming a second polycrystalline silicon on the dielectric film to fill the inside of said trench and to fold with a portion of said word line on said channel region; and
depositing Low Temperature Oxide and Boro
Phosphorous Silicon Glass film over said second polycrystalline silicon and dielectric film, and forming an opening hole on said drain region and making a metalsilicide film.
Said metal-silicide may be a silicide of tungsten or titanium.
According to a third aspect of the present invention, there is provided a DRAM cell including, on a semiconductor substrate, a transistor, a stack capacitor and a trench capacitor, said stack capacitor and said trench capacitor being connected in parallel, and said transistor being connected to said stack capacitor and said trench capacitor.
Preferably, said semiconductor substrate is of a first conductivity type and said transistor is of a second conductivity type. Preferably, a cell node of the stack capacitor is coupled to a source region of the transistor; a cell node of the trench capacitor is coupled to the source region of the transistor; and respective cell nodes of said stack capacitor and said trench capacitor are coupled to one another.
According to a fourth aspect of the present invention, there is provided a DRAM cell according to the third aspect in combination with a DRAM cell according to the first aspect.
According to a fifth aspect of the present invention, there is provided a method of making a DRAM cell according to the first and third aspects, including the steps of firstly forming said transistor on said semiconductor substrate, followed by forming said stack capacitor and said trench capacitor.
According to a sixth aspect of the present invention, there is provided a method of making a DRAM cell according to the fifth aspect in combination with the second aspect.
For a better understanding of the invention, and to show how same may be put into effect, reference will now be made, by way of example, to Figures 3 and 4 of the accompanying diagrammatic drawings, in which:
Figure 3 is a cross-sectional view of a DRAM cell;
Figures 4A to 4G are cross-sectional views showing each stage of manufacturing a DRAM cell according to the present invention.
In Figures 3 and 4 like reference numerals indicate the same portions or compositions.
A DRAM cell having a capacitor of trench and stack structure has been developed in an attempt to increase DRAM memory density and thereby maximise storage capacity on a fixed area occupied by a DRAM cell.
The structure of the DRAM cell comprises an Nchannel transistor and at least one storage capacitor including a stack capacitor and a trench capacitor. The
N-channel MOS transistor consists of source region 53 which is adjacent to a field oxide 46 formed over the surface of a p-type semiconductor substrate 40, a drain region 52 separated through channel and a word line 50 or a gate electrode of a conductivity type being grown over a gate oxide 48 on the substrate between the drain 52 and source region 53. A first polycrystalline silicon layer 56, separated from the word lines 50, 51 by a first insulating film 71, is connected with the source region 53 to provide a cell node layer of the stack capacitor.
The N-type diffusion region 60 is formed around a trench 58, formed between the source region 53 and field oxide 46, to provide a cell node layer of the trench capacitor.
A second polycrystalline silicon layer 64, filling the trench 58, is formed on a thin dielectric film 62 and utilized as a cell plate layer of the stack and trench capacitor.
Therefore, the stack capacitor comprises the first polycrystalline silicon 56, the thin dielectric film 62 and the second polycrystalline silicon layer 64.
The trench capacitor comprises the diffusion region 60, the thin dielectric film 62 and the second polycrystalline silicon layer 64. The stack and trench capacitors are parallel connected to the source region 53. A bit line 72 separated from the second polycrystalline silicon layer 64 by a second insulating film 70, is connected to the drain region 52 through an opening hole. The second insulating film 70 consists of oxide 66 and a Boro-Phosphorous Silicon Glass (hereinafter BPSG ) film 68. In addition, the word line 51 is formed on the field oxide 46 to provide a gate electrode of adjacent memory cell.
The DRAM cell shown in Figure 3 may be manufactured as follows.
Referring to Figure 4A, the starting material is a p-type substrate with a concentration of 1016 ions/cm3.
It is noted that the substrate 40 may be a p-type well formed in a p-type wafer with a sheet resistance of lo(-1-cm. A field oxide 46 is formed on the substrate 40 for isolating between memory cells. That is to say, after depositing an oxide 42 having a thickness of about 200 a and a nitride 44 having a thickness of about 1000 R on the substrate 40, a portion of nitride 44, except for a transistor region, is removed by a conventional photolithographic method, and a field oxide 46 is formed for isolating between memory cells by means of a LOCOS (Local Oxidation of Silicon) method.
Referring now to Figure 4B, after removing the nitride 44 and the oxide 42, a gate oxide 48 having a thickness of about 160 i is grown on the substrate 40.
Thereafter, a polycrystalline silicon having a thickness of about 2500 a and a Low Temperature Oxide (LTO) of 1500 are sequentially deposited on the gate oxide 48 and the field oxide 46, after forming a gate electrode or word lines 50, 51 by a conventional photolithographic technique. A source 53 and drain region 52 are then formed by means of ion-implantation with Arsenic (As) having a dose of 5 x 1015 ions/cm3 and an energy of 40KeV. Above, the word line 51 on the field oxide 46 becomes a gate electrode of adjacent cell.
Referring to Figure 4C, a first insulating film 71, such as LTO film, having a thickness of 2000 i is deposited on the word lines 50, 51, field oxide 46 and exposed gate oxide 48 by means of known CVD (Chemical vapor Deposition). In addition, an opening hole 54 is formed on a given portion of the source region 53 in order to expose the source region 53.
Referring now to Figure 4D, after depositing a first polycrystalline silicon 56 having a thickness of about 1000 i on the first insulating film 71 and exposed source region 53, a photolithographic technique is operated. The first polycrystalline silicon 56 is utilized as a cell node layer of stack capacitor, and is doped with POC13 or ion implantation. The surface area of the first polycrystalline silicon becomes large due to extending over the word lines 50, 51.
Referring to Figure 4E, after forming a trench 58 in the first polycrystalline silicon 56, contacted by the source region 53 and its lower substrate 56, by means of anisotropic etching like a conventional Reactive ion etching, an N-diffusion region 60 is formed by ion implantation of As having a dose of 5x1015 ions/cm3 at 130 KeV. Then a dielectric film 62 having a thickness of about 100 a is formed on the first polycrystalline silicon 56 and the inside surface of the trench 58. The
N-diffusion region 60, contacted with the source region 53, is utilized as a cell node of trench capacitor.
Also, the dielectric film 62 may function as dielectric material of stack and trench capacitor, and may contain an oxide or ONO (Si02/Si3N4/Si02) film.
Referring now to Figure 4F, a second polycrystalline silicon 64 is deposited on the dielectric film 62 to fill the inside of the trench 58 and a cell plate is formed by a photolithographic technique. The second polycrystalline silicon 64 is utilized as a cell plate of the stack and trench capacitor, and is doped with POC13.
Referring to Figure 4G, an oxide film 66, having a thickness of about 500 R, is deposited on the dielectric film 62 and the second polycrystalline silicon 64, and BPSG film 68 having a thickness of about 3000 R is formed on the oxide film 66 for flattening the surface. The oxide film 66 and BPSG film 68 are utilized as a second insulating film 70. After this processing, a metal-silicide 72 having a thickness of about 3000 a is formed to contact a portion of drain region 52 exposed through an opening hole formed by a photolithographic technique. The metal-silicide 72 can be a silicide of W or Ti and provides a bit line.
The embodiment of the invention described above may increase storage capacity by connecting a trench capacitor with a stack capacitor in parallel. It may be advantageous in that large-scale integration can be achieved, as follows: the distance between trenches is decreased by limit of diffusion region, since a thermal treatment time is short for forming trench capacitor after transistor is formed; and a hole of trench is small because a polycrystalline silicon is not deposited on the surface of trench for forming a cell node.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
Claims (13)
1. A DRAM cell which comprises a field oxide formed on the surface of a semiconductor substrate of a first conductivity type in order to isolate between adjacent cells, a drain and source region of a second conductivity type opposite to the first conductivity type, separated from themselves by a given distance on the substrate, a gate oxide on the substrate between said source and drain region, and word lines of a conductivity type being grown on said field oxide, said DRAM cell further comprising::
a trench formed under a given portion between said source region and field oxide, a diffusion layer connected with said source region by ion-implanting impurity of a second conductivity type into the substrate of said outside trench;
a first polycrystalline silicon connected with said source region and isolated from said word lines by a first insulating film;
a dielectric film formed on the inside surface of said trench and a first polycrystalline silicon;
a second polycrystalline silicon formed on the dielectric film so as to fill the inside of said trench; and
a bit line connected with said drain region through an opening hole and isolated by a second insulating film.
2. A DRAM cell according to claim 1, wherein said first insulating film is oxide film.
3. A DRAM cell according to Claim 1 or Claim 2, wherein said first polycrystalline silicon and diffusion layer of impurity are connected to the source region in parallel.
4. A method of making a DRAM cell having a stacked and a trench capacitor and a transistor of a second conductivity type opposite to a first conductivity type on a semiconductor substrate of the first conductivity type, comprising the steps of:
forming a thick field oxide on a portion of the surface of said semiconductor substrate, a source region of a second conductivity type which is adjacent to said field oxide, and a drain region of the second conductivity type separated through channel region on the surface of said semiconductor substrate, a gate oxide on the surface of said source region, channel and drain region, and then word lines of the conductivity type over said channel region and a given region of said field oxide, respectively;;
forming a first insulating film on said word lines, exposed gate oxide and field oxide, and an opening hole at the first insulating film and gate oxide overlaying said source region;
forming a first polycrystalline silicon on said source region to fold with portions of said word lines;
forming a trench over the source, substrate and first polycrystalline silicon formed into said opening hole, and a diffusion layer of a second conductivity type on the outside substrate of said trench in order to be connected with said source region, and then a dielectric film on said first insulating film, first polycrystalline silicon and the surface of trench;
forming a second polycrystalline silicon on the dielectric film to fill the inside of said trench and to fold with a portion of said word line on said channel region; and
depositing Low Temperature Oxide and Boro
Phosphorous Silicon Glass film over said second polycrystalline silicon and dielectric film, and forming an opening hole on said drain region and making a metalsilicide film.
5. A method of making a DRAM cell according to Claim 4, wherein said metal-silicide is a silicide of tungsten or titanium.
6. A DRAM cell including, on a semiconductor substrate, a transistor, a stack capacitor and a trench capacitor, said stack capacitor and said trench capacitor being connected in parallel, and said transistor being connected to said stack capacitor and said trench capacitor.
7. A DRAM cell according to Claim 6, wherein said semiconductor substrate is of a first conductivity type and said transistor is of a second conductivity type.
8. A DRAM cell according to Claim 6 or Claim 7, wherein a cell node of the stack capacitor is coupled to a source region of the transistor; a cell node of the trench capacitor is coupled to the source region of the transistor; and respective cell nodes of said stack capacitor and said trench capacitor are coupled to one another.
9. A DRAM cell according to any of Claims 6 to 8 in combination with a DRAM cell according to any of Claims 1 to 3.
10. A method of making a DRAM cell according to any of Claims 1 to 3 and 6 to 9, including the steps of firstly forming said transistor on said semiconductor substrate, followed by forming said stack capacitor and said trench capacitor.
11. A method of making a DRAM cell according to Claim 10, in combination with Claim 4 or Claim 5.
12. A DRAM cell substantially as hereinbefore described with reference to Figure 3 and/or Figures 4 of the accompanying drawings.
13. A method of making a DRAM cell, the method being substantially as hereinbefore described with reference to
Figure 3 and/or Figures 4 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890006720A KR920010695B1 (en) | 1989-05-19 | 1989-05-19 | D-ram cell and its manufacturing method |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8926627D0 GB8926627D0 (en) | 1990-01-17 |
| GB2231718A true GB2231718A (en) | 1990-11-21 |
| GB2231718B GB2231718B (en) | 1993-05-26 |
Family
ID=19286319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8926627A Expired - Fee Related GB2231718B (en) | 1989-05-19 | 1989-11-24 | A dynamic random access memory cell and method of making the same |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH0715949B2 (en) |
| KR (1) | KR920010695B1 (en) |
| DE (1) | DE3927176A1 (en) |
| FR (1) | FR2647267B1 (en) |
| GB (1) | GB2231718B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2247105A (en) * | 1990-08-14 | 1992-02-19 | Samsung Electronics Co Ltd | Capacitors for dram cells |
| DE4203565A1 (en) * | 1991-02-08 | 1992-08-13 | Mitsubishi Electric Corp | DRAM AND METHOD FOR THE PRODUCTION THEREOF |
| US5185284A (en) * | 1989-05-22 | 1993-02-09 | Mitsubishi Denki Kabushiki Kaisha | Method of making a semiconductor memory device |
| US5208177A (en) * | 1992-02-07 | 1993-05-04 | Micron Technology, Inc. | Local field enhancement for better programmability of antifuse PROM |
| US5272103A (en) * | 1991-02-08 | 1993-12-21 | Mitsubishi Denki Kabushiki Kaisha | DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof |
| US6278149B1 (en) * | 1997-09-04 | 2001-08-21 | Kabushiki Kaisha Toshiba | Plurality of trench capacitors used for the peripheral circuit |
| EP4030488A4 (en) * | 2019-10-31 | 2022-11-23 | Guangdong Midea White Home Appliance Technology Innovation Center Co., Ltd. | Semiconductor device, preparation method therefor and electrical equipment thereof |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR910013554A (en) * | 1989-12-08 | 1991-08-08 | 김광호 | Semiconductor device and manufacturing method thereof |
| JPH03200366A (en) * | 1989-12-27 | 1991-09-02 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH03278573A (en) * | 1990-03-28 | 1991-12-10 | Mitsubishi Electric Corp | Semiconductor memory device |
| KR100689514B1 (en) | 2006-01-23 | 2007-03-02 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0085988A2 (en) * | 1982-02-10 | 1983-08-17 | Hitachi, Ltd. | Semiconductor memory and method for fabricating the same |
| EP0169938A1 (en) * | 1983-12-15 | 1986-02-05 | Kabushiki Kaisha Toshiba | Semiconductor memory device having trenched capacitor |
| GB2197534A (en) * | 1986-11-12 | 1988-05-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit capacitor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60189964A (en) * | 1984-03-12 | 1985-09-27 | Hitachi Ltd | Semiconductor memory |
| JPS62120070A (en) * | 1985-11-20 | 1987-06-01 | Toshiba Corp | Semiconductor memory |
| JPH01119053A (en) * | 1987-10-31 | 1989-05-11 | Sony Corp | Semiconductor memory device |
| JP2548957B2 (en) * | 1987-11-05 | 1996-10-30 | 富士通株式会社 | Method for manufacturing semiconductor memory device |
-
1989
- 1989-05-19 KR KR1019890006720A patent/KR920010695B1/en not_active IP Right Cessation
- 1989-08-17 DE DE3927176A patent/DE3927176A1/en active Granted
- 1989-08-30 JP JP1221888A patent/JPH0715949B2/en not_active Expired - Fee Related
- 1989-09-07 FR FR8911703A patent/FR2647267B1/en not_active Expired - Lifetime
- 1989-11-24 GB GB8926627A patent/GB2231718B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0085988A2 (en) * | 1982-02-10 | 1983-08-17 | Hitachi, Ltd. | Semiconductor memory and method for fabricating the same |
| EP0169938A1 (en) * | 1983-12-15 | 1986-02-05 | Kabushiki Kaisha Toshiba | Semiconductor memory device having trenched capacitor |
| GB2197534A (en) * | 1986-11-12 | 1988-05-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit capacitor |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5185284A (en) * | 1989-05-22 | 1993-02-09 | Mitsubishi Denki Kabushiki Kaisha | Method of making a semiconductor memory device |
| GB2247105A (en) * | 1990-08-14 | 1992-02-19 | Samsung Electronics Co Ltd | Capacitors for dram cells |
| GB2247105B (en) * | 1990-08-14 | 1995-04-05 | Samsung Electronics Co Ltd | Highly integrated semiconductor memory device and method of manufacture therefor |
| DE4203565A1 (en) * | 1991-02-08 | 1992-08-13 | Mitsubishi Electric Corp | DRAM AND METHOD FOR THE PRODUCTION THEREOF |
| US5272103A (en) * | 1991-02-08 | 1993-12-21 | Mitsubishi Denki Kabushiki Kaisha | DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof |
| US5208177A (en) * | 1992-02-07 | 1993-05-04 | Micron Technology, Inc. | Local field enhancement for better programmability of antifuse PROM |
| US6278149B1 (en) * | 1997-09-04 | 2001-08-21 | Kabushiki Kaisha Toshiba | Plurality of trench capacitors used for the peripheral circuit |
| EP4030488A4 (en) * | 2019-10-31 | 2022-11-23 | Guangdong Midea White Home Appliance Technology Innovation Center Co., Ltd. | Semiconductor device, preparation method therefor and electrical equipment thereof |
| US11935845B2 (en) | 2019-10-31 | 2024-03-19 | Guangdong Midea White Home Appliance Technology Innovation Center Co., Ltd. | Semiconductor device, preparation method therefor and electrical equipment thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3927176A1 (en) | 1990-11-22 |
| GB8926627D0 (en) | 1990-01-17 |
| JPH0715949B2 (en) | 1995-02-22 |
| DE3927176C2 (en) | 1992-03-26 |
| GB2231718B (en) | 1993-05-26 |
| FR2647267B1 (en) | 1995-03-10 |
| KR920010695B1 (en) | 1992-12-12 |
| FR2647267A1 (en) | 1990-11-23 |
| KR900019141A (en) | 1990-12-24 |
| JPH02312270A (en) | 1990-12-27 |
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| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20081124 |