TW309644B - Semiconductor memory device with capacitor (3) - Google Patents

Abstract

A semiconductor memory device with capacitor, in which the semiconductor memory device includes one substrate, one transfer transistor formed on the substrate, and one storage capacitor electrically coupled to one of drain and source region of the transfer transistor, comprises of the following steps: (1) on the substrate forming one first insulator, overlaying the transfer transistor; (2) forming one first conductive layer, passing at least the first insulator, electrically coupled with one of the drain and source region of the transfer transistor; (3) above the first conductive layer periphery forming one pillar layer;(4) on the pillar layer surface and the first conductive layer forming one second conductive layer; (5) patterning the second conductive layer, separating the portion located above the pillar layer; (6) patterning the second conductive layer and the first conductive layer, forming one opening; (7) forming one hollow third conductive layer on the opening sidewall, connected to the first conductive layer periphery, the third and first conductive layer constitute one trunk-type like conductive layer, and one terminal of the second conductive layer connected to internal surface of the third conductive layer, constituting one branch-type like conductive layer, and the first, second, third conductive layer constitute one storage node of the storage capacitor; (8) removing the pillar layer; (9) on exposed surface of the first, second, third conductive layer, forming one dielectric; (10) on one surface of the dielectric, forming one fourth conductive layer to constitute one opposed electrode of the storage capacitor.

Description

03 I3twf.doc / 002 A7 B7 V. Description of the invention (I) The present invention relates to a semiconductor memory device with capacitor (Semiconductor Memory Device), and in particular to a dynamic random access memory (Dynamic Random Access Memory) Memory; DRAM), a memory cell (Memory Cell) structure, which includes a transfer transistor (Transfer Transistor) and a tree-type (tree-type) storage capacitor. Figure 1 is a schematic circuit diagram of a memory cell of a DRAM device. As shown in the figure, a memory cell is composed of a transfer transistor T and a storage capacitor C. The source of the transfer transistor T is connected to a corresponding bit line BL, the drain is connected to a storage electrode 6 (storage electrode) of the storage capacitor C, and the gate is connected to a corresponding word line WL. A opposed electrode 8 of the storage capacitor C is connected to a fixed voltage source, and a dielectric film layer 7 is provided between the storage electrode 6 and the opposite electrode 8. When the storage capacity of the traditional DRAM is less than 1M (mega = million) bits, in the integrated circuit manufacturing process, it is mainly realized by using a capacitor of a two-dimensional space, which is generally known as a planar type capacitor. ^ —Flat-type capacitors require a considerable area of the semiconductor substrate to store charge, so they are not suitable for high accumulation. Highly integrated DRAMs, such as those with a storage capacity of more than 4M bits, need to be implemented with three-dimensional capacitors, such as so-called stacked type or trench type capacitors. Compared with flat capacitors, stacked or trench capacitors can still obtain considerable capacitance even when the size of the memory cell has been further reduced. Nonetheless, when the memory element enters a higher level of accumulation, the 4 paper scales are suitable for China ’s poor family (CNS > A4 specifications (2 丨 OX297 公 1> HM · ί I · * · (please read the back Please pay attention to this matter and then fill out this page) Order the printing of the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs • ίΊ

309 cases * 4 I f.doc / 002 A7 B7 Printed by the WC Industrial Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs V. Description of invention (meaning) For example, a DRAM with a 64M bit capacity and a simple three-dimensional space capacitor structure Is no longer applicable. One solution is to use so-called fin type stacked capacitors. For the related technology of fin-type stacked capacitors, please refer to the paper “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMsM, International Electron Devices Meeting, pp. 592-595, Dec. 1988” of Ema et al. And the dielectric film layer is composed of a plurality of stacked layers, extending into a horizontal fin structure, in order to increase the surface area of the electrode. DRAM fin-type stacked capacitors related U.S. patents can refer to 5,071,783, 5,126,810, No. No. 5,196,365, and No. 5,206,787. Another solution is to use the so-called cylindrical type (stack type capacitor). The related technology of the cylindrical type stack capacitor can refer to the paper "Novel Stacked Capacitor Ceil for 64-" by Wakamiya et al. Mb DRAM ", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. The barrel-type stacked capacitor mainly has its electrodes and dielectric film layers extended into a vertical barrel structure in order to increase the surface area of the electrodes. The barrel of DRAM Related US patents for stacked capacitors can refer to No. 5,077,688. With the degree of accumulation The size of the DRAM memory cell will continue to shrink as it continues to increase. As is known to those skilled in the art, the reduction in the size of the memory cell will reduce the capacitance value of the storage capacitor. The reduction in the capacitance value will result in The chance of soft errors increases. Therefore, this artist is still constantly looking for new storage capacitor structures and manufacturing methods, hoping that the storage capacitors will be able to maintain the desired size 5 (Please ^ read (Note the item on the back and fill in this page) Γ. Pack. Order

The size of the C-line paper is applicable to the Chinese National Standard (CNS) 8 4 «1 grid (210Χ297 mm) 03 1 3twf.doc / 002 A7 B7 Printed by the Central Ministry of Economic Affairs Central Bureau of Unemployment Consumer Cooperative V. Invention description (彡) Of the capacitance value. Therefore, a main object of the present invention is to provide a semiconductor memory device having a capacitor whose capacitor has a tree structure to increase the surface area of the storage electrode of the capacitor. According to one feature of the present invention, a method for manufacturing a semiconductor memory device having a capacitor is provided, wherein the semiconductor memory device includes a substrate, a transfer transistor formed on the substrate, and a storage capacitor electrically coupled to the transfer circuit One of the drain and source regions of the crystal. The manufacturing method includes the following steps: a. Forming a first insulating layer on the substrate to cover the transfer transistor; b. Forming a first conductive layer through at least the first insulating layer, and the transfer transistor drain One of the source regions is electrically coupled; c. Forming a columnar layer on the first conductive layer; d. Forming a second conductive layer on the surface of the columnar layer and the first conductive layer; e. Defining the second The conductive layer separates the portion above the column-shaped layer; f. Defines the second conductive layer and the first conductive layer to form an opening; g. Forms a hollow cylindrical third conductive body on the side wall of the opening and connects to Around the first conductive layer, the third conductive layer and the first conductive layer constitute a type of trunk-shaped conductive layer, and one end of the second conductive layer is connected to the inner surface of the third conductive layer to constitute a type of dendritic conductive layer, and The first, second and third conductive layers constitute a storage electrode of the storage capacitor: h .. removing the columnar layer; i. Forming a dielectric layer on the exposed surface of the first, second and third conductive layers ; And j. On a surface of the dielectric layer, a fourth conductive layer is formed to constitute A storage capacitor counter electrode. According to a preferred embodiment of the present invention, the trunk-like conductive layer includes a trunk portion electrically coupled to one of the drain and source regions of the transfer transistor: and an upper trunk portion from the lower trunk portion The periphery extends generally upward. This paper scale is applicable to China® Family Standard (CNS > Α4 specification (210Χ297mm) η First Read Back Binding Line 309644 f.doc / 002 A7 Printed by the Ministry of Economic Affairs, Central Bureau of Industry and Commerce Bigong Consumer Cooperatives B7. Description of Invention (Law) The method of the present invention may further include the step of forming an etching protection layer on the first insulating layer after step a and before step b. In a preferred embodiment, step e may include etching away the second conductive layer The layer is located above the columnar layer. In another preferred embodiment, step e may include chemical mechanical grinding to remove the second conductive layer above the columnar layer. In another preferred embodiment of the invention, step c may include the following steps: forming a thick insulating layer on the first conductive layer; forming a photoresist on the thick insulating layer so as not to cover the planned notch; etching Remove a part of the thick insulating layer that is not covered; etch the photoresist, and then expose a part of the thick insulating layer; etch away a part of the exposed thick insulating layer until the first conductive layer is exposed, so that the formed pillar The layer has a stepped shape; According to yet another preferred embodiment of the present invention, after step a and before step b, the following steps are further included: first forming an etching protection layer on the first insulation layer, and then forming a fourth insulation layer in etching protection Layer. Step b further includes the step of forming a first conductive layer 'through the fourth insulating layer and the etching protection layer. Step h further includes the step of removing the fourth insulating layer. According to another preferred embodiment of the present invention' The manufacturing method of a semiconductor memory device with a capacitor includes the following steps: forming a first insulating layer on a substrate to cover the transfer transistor. Forming a first conductive layer, passing through at least the first insulating layer, and the transfer transistor One of the drain and source regions is electrically coupled. A columnar layer is formed on the first conductive layer and on the surface of the columnar layer and the first conductive layer, the first and second film layers are alternately formed at least once, Among them, the second film layer is made of conductive material 'and the first film layer is made of insulating material. Define the second film layer' to separate its part above the columnar layer. Define the second film layer, the first A film The first conductive layer is formed with an opening. In 7 papers, the New Zealand financial materials (CNS > 8 4 secrets (21GX297 public shame) (please read the note f on the back and fill in this page). Install. Order Line. 03 I 3twf.doc / 002 A7 Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs 5. Description of Invention (Xi) The opening side wall forms a hollow cylindrical second conductive layer connected to the periphery of the first conductive layer, The second conductive layer and the first conductive layer constitute a type of trunk-like conductive layer; and one end of the second film layer is connected to the inner surface of the second conductive layer to constitute a type of dendritic conductive layer, and the first conductive layer, the second The film layer and the second conductive layer constitute a storage electrode of the storage capacitor. The columnar layer and the first film layer are removed to form a dielectric on the exposed surfaces of the first conductive layer, the second film layer and the second conductive layer Floor. On a surface of the dielectric layer, a third conductive layer is formed to constitute a counter electrode of the storage capacitor. According to yet another preferred embodiment of the present invention, a method for manufacturing a semiconductor memory device having a capacitor includes the following steps: forming a first insulating layer on a substrate to cover the transfer transistor; forming a first conductive layer, passing through Through at least the first insulating layer, electrically coupled to one of the drain and source regions of the transfer transistor; forming at least one columnar layer on the first conductive layer; forming a second conductive layer on the side wall of the columnar layer Define the first conductive layer, forming an opening; forming a hollow cylindrical third conductive layer on the side wall of the opening, connected to the periphery of the first conductive layer, and an end of the second conductive layer connected to the first conductive layer On the upper surface, a type of dendritic conductive layer is formed, and the first, second, and third conductive layers constitute a storage electrode of the storage capacitor; the columnar layer is removed; the exposed surface of the first, second, and third conductive layers On top, a dielectric layer is formed; and on a surface of the dielectric layer, a fourth conductive layer is formed to form an opposite electrode of the storage capacitor. According to another preferred embodiment of the present invention, a method for manufacturing a semiconductor memory device having a capacitor includes the following steps: forming a first insulating layer on a substrate to cover the transfer transistor; forming a first conductive layer, passing through Pass at least the first insulating layer, and one of the drain and source regions of the transfer transistor. The size of this paper is based on the Chinese National Standard (CNS & A4 specification (210X297mm) (please read P9'-back (Notes and then fill out this page) Binding · Order 03 I 3twf.doc / 002 A7 B7 5. Description of the invention (6) Electrical coupling; at least one columnar layer is formed on the first conductive layer; on the side wall of the columnar layer , Forming a second conductive layer, one end of the second conductive layer is connected to the upper surface of the first conductive layer; on the surface of the second conductive layer and the columnar layer, and the first conductive layer, the first and the first The second film layer is made at least once. The second film layer is made of a conductive material, and the first film layer is made of an insulating material: define the second film layer and separate its part above the columnar layer; define the second The film layer, the first film layer and the first conductive layer form a Opening; forming a hollow cylindrical third conductive layer on the side wall of the opening, connected to the periphery of the first conductive layer, the third conductive layer and the first conductive layer constitute a type of trunk-shaped conductive layer, and one end of the second film layer is connected On the inner surface of the third conductive layer, the second film layer and the second conductive layer constitute a type of dendritic conductive coating, and the first, second, third conductive layer, and second film layer constitute a storage electrode of the storage capacitor; Removing the columnar layer and the first film layer; forming a dielectric layer on the exposed surfaces of the first, second, third conductive layers and the second film layer; and forming on a surface of the dielectric layer A fourth conductive layer constitutes a counter electrode of the storage capacitor. According to yet another feature of the present invention, a method for manufacturing a semiconductor memory device having a capacitor includes the following steps: forming an insulating layer on a substrate to cover the transfer circuit Crystal. Forming a kind of trunk-like conductive layer, the trunk-like conductive layer includes the following trunk portion electrically coupled to one of the drain and source regions of the transfer transistor, and an upper trunk portion from the lower trunk portion The periphery extends substantially upward. At least one type of dendritic conductive layer is formed, which includes at least one first extension and a second extension, one end of the first extension is connected to the inner surface of the trunk-like conductive layer, the second The extension section extends from the other end of the first extension section at an angle. The trunk-like conductive layer and the branch-like branches 9 This paper scale is remotely used by China National Standards (CNS) A4 (210X297). __1 --- ------ Installation-- (Please read the notes on the back of M- first and then fill out this page) Printed somi f.doc / 002 by the Ministry of Economic Affairs, Central Counseling Bureau Employee Consumer Cooperative Society A7 B7 printed by the Industrial and Consumer Cooperatives 5. Description of the invention (7) The conductive layer forms a storage electrode of the storage capacitor. A dielectric layer is formed on the exposed surface of the trunk-like conductive layer and the dendritic conductive layer. And on the dielectric layer, an upper conductive layer is formed to constitute an opposite electrode of the storage capacitor. According to still another feature of the present invention, a method of manufacturing a semiconductor memory device having a capacitor includes the following steps: forming an insulating layer on a substrate to cover the transfer transistor. A trunk-like conductive layer is formed. The trunk-like conductive layer includes a lower trunk portion electrically coupled to one of the drain and source regions of the transfer transistor, and an upper trunk portion extending generally upward from the periphery of the lower trunk portion . At least one type of dendritic conductive layer is formed, the shape of which is roughly a hollow cylinder, and one end of the dendritic conductive layer is connected to the upper surface of the trunk-like conductive layer, extending upward in a generally upward direction, trunk-like The conductive layer and the dendritic conductive layer constitute a storage electrode of the storage capacitor. A dielectric layer is formed on the exposed surface of the trunk-like conductive layer and the dendritic-like conductive layer. And on the dielectric layer, an upper conductive layer is formed to constitute an opposite electrode of the storage capacitor. According to still another feature of the present invention, a method of manufacturing a semiconductor memory device having a capacitor includes the following steps: forming an insulating layer on a substrate to cover the transfer transistor. A trunk-like conductive layer is formed. The trunk-like conductive layer includes a lower trunk portion electrically coupled to one of the drain and source regions of the transfer transistor, and an upper trunk portion extending generally upward from the periphery of the lower trunk portion . A first type of dendritic conductive layer is formed, the shape of which is roughly a hollow cylinder, and one end of the first type of dendritic conductive layer is connected to the upper surface of the trunk-like conductive layer, extending upward in a generally upward direction . Form at least one second-type dendritic conductive layer. The second-type dendritic conductive layer has (please read note f on the back before filling in this page). Packing. The paper size of the binding book is applicable to China National Standards (CNS) A4 Specifications (2 丨 Ο X 2mm) 03 1 3twf.doc / 002 A 7 Printed by the Consumers ’Cooperation Bureau of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Description (K) One end is connected to the inner surface of the trunk-like conductive layer Above, the second type of dendritic conductive layer has an outwardly extending portion, which extends outward from the end. The trunk-like conductive layer and the dendritic conductive layers constitute a storage electrode of the storage capacitor. A dielectric layer is formed on the exposed surface of the trunk-like conductive layer and the dendritic conductive layer. And on the dielectric layer, an upper conductive layer is formed to constitute an opposite electrode of the storage capacitor. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are described below in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: Figure 1 It is a circuit schematic diagram of a memory unit of a DRAM device. Figures 2A to 2H are a series of cross-sectional views for explaining a first preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a first preferred embodiment of a semiconductor memory device of the present invention. Figures 3A to 3E are a series of cross-sectional views for explaining a second preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a second preferred embodiment of a semiconductor memory device of the present invention. Figures 4A to 4D are a series of cross-sectional views for explaining a third preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a third preferred embodiment of a semiconductor memory device of the present invention. FIGS. 5A to 5C are a series of cross-sectional views for explaining a fourth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a fourth preferred embodiment of a semiconductor memory device of the present invention. Figures 6A to 6D are a series of cross-sectional views for explaining the fifth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and the present invention (please read the note f on the back side before filling in this page)- Binding. The paper size of the binding book is applicable to the Chinese National Standard (CNS) A4 «L grid (210X297mm: > 03 13twf.doc / 002, printed by the Central Sample Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperative A7 B7. V. Description of invention ( ?) A fifth preferred embodiment of a semiconductor memory device shown in FIGS. 7A to 7D is a series of cross-sectional views for explaining a sixth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and the present invention The sixth preferred embodiment of a semiconductor memory device of the same type. Figures 8A to 8E are a series of cross-sectional views for explaining the seventh preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention and a semiconductor of the present invention The seventh preferred embodiment of the memory device. Figures 9A to 9E are a series of cross-sectional views for explaining the eighth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention and a first embodiment of the present invention An eighth preferred embodiment of a semiconductor memory device. Figures 10A to 10D are a series of cross-sectional views for explaining a ninth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a semiconductor memory device of the present invention The ninth preferred embodiment. Next, referring to FIGS. 2A to 2H, a first preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention, and this preferred embodiment of a semiconductor memory device will be described in detail. Is manufactured by the first preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention. Referring to FIG. 2A, first, a surface of a silicon substrate 10 is subjected to a thermal oxidation process, such as local oxidation of silicon (LOCOS) To achieve this, a field oxide layer 12 is formed with a thickness of approximately 3000 angstroms. Then, the silicon substrate 10 is subjected to a thermal oxidation process to form a gate oxide layer 14 with a thickness of approximately 150 angstroms. Then, using a CVD (chemical vapor deposition) or LPCVD (low pressure CVD) method, a polycrystalline silicon layer is deposited on the entire surface of the silicon substrate 10, with a thickness of, for example, about 2000 Angstroms. In order to improve the conductivity of the polycrystalline silicon layer, phosphorus ions can be implanted into it (please read the precautions on the back before filling out this page). Packing. The paper size of the binding book is applicable to China National Standard (CNS) A4 Specification (210X 297mm) Printed by the Central Sample Bureau of the Ministry of Economic Affairs of the Employees Consumer Cooperative 3096f4twfdoc / 002 a? B7 Fifth, the invention description (R) in the polycrystalline silicon layer. Preferably, a refractory metal can be deposited ) Layer, and then perform an annealing (anneal) step, that is to form a metal polycrystalline silicon compound layer (polycide), to further improve its conductivity. The refractory metal may be, for example, tungsten (Tungsten), and the deposited thickness is, for example, about 2000 angstroms. After that, the metal polycrystalline silicon compound layer is patterned using traditional photolithography and etching techniques, thereby forming gates (or word lines) WL1 to WL4 as shown in FIG. 2A. Next, for example, arsenic ions are implanted into the silicon substrate 10 to form drain regions 16a and 16b and source regions 18a and 18b. In this step, the word lines WL1 to WL4 are used as the mask layer, and the dose of ion implantation is, for example, about 1 X 1015 atoms / cm2, which will be a huge amount of IJ about 70KeV. Please refer to FIG. 2B, then, The CVD method deposits a planarized insulating layer 20, such as BPSG (borophosphosilicate glass), with a thickness of about 7000 angstroms. Then, an etching protection layer (etching protection layer) 22 is deposited by CVD, which is, for example, a silicon nitride layer (silicon nitride) with a thickness of about 1000 angstroms. Afterwards, the etching protection layer 22, the planarization insulating layer 20, and the gate oxide layer 14 are sequentially etched using conventional photomask patterning and etching techniques to form storage electrode contact holes 24a and 24b, It extends from the upper surface of the etch protection layer 22 to the surfaces of the drain regions 16a and 16b, respectively. Next, a polycrystalline silicon layer 26 is deposited. In order to improve the conductivity of the polycrystalline silicon layer, for example, arsenic ions can be implanted into the polycrystalline silicon layer. As shown, the polycrystalline silicon layer 26 fills the storage electrode contact windows 24a and 24b, and covers the surface of the etching protection layer 22. Please refer to Figure 2C, and then deposit a thick insulating layer, which is, for example, two (please read the precautions on the back before filling in this page). The paper size of the binding and binding book is applicable to China National Falcon (CNS) A4 specification (210X297 Mm) 03 I3twf.doc / 002 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention ((丨) Silicon oxide layer with a thickness of about 7000 Angstroms. Then use traditional mask making and etching techniques to define insulation Layers, thus forming columnar insulating layers 28a and 28b (insulating pillars) as shown by circles. The preferred positions of the columnar insulating layers 28a and 28b generally correspond to the areas above the drain regions 16a and 16b, respectively. Notches 29 are formed between the layers. Please refer to FIG. 2D, and then sequentially deposit an insulating layer 30, a polycrystalline silicon layer 32, and an insulating layer 34 by CVD. The insulating layers 30 and 34 are, for example, silicon dioxide, The thickness of the insulating layer 30 and the polycrystalline silicon layer 32 are, for example, about 100 angstroms, and the thickness of the insulating layer 34 is preferably such that it at least fills the notch 29 between the columnar insulating layers 28a; 28b. In a preferred embodiment, the thickness of the insulating layer 34 is, for example, about 700 0 angstroms. In order to improve the conductivity of the polycrystalline silicon layer 32, for example, arsenic ions can be implanted into the polycrystalline silicon layer 32. Please refer to FIG. 2E, and then use the chemical mechanical polishing (CMP) technology, Grind the surface of the structure in Figure 2D until at least the portions above the columnar insulating layers 28a and 28b are exposed. Please refer to Figure 2F, and then etch the insulating layer 34 and the complex layer in sequence using traditional photomask patterning and etching techniques The crystalline silicon layer 32, the insulating layer 30, and the polycrystalline silicon layer 26 form an opening 36 to define the storage electrodes of the storage capacitors of each memory cell. That is, the polycrystalline silicon layers 32 and 26 are cut into several pieces by this step Sections 32a; 32b and 26a; 26b. Then, on the side walls (sidewalls) of the opening 36, polycrystalline sand sidewalls (spacers) 38a and 38b are formed. In the preferred embodiment, polycrystalline silicon sidewalls 38a and 38b can The following steps are formed: depositing a polycrystalline silicon layer with a thickness of, for example, about 1000 angstroms; and etching back. To improve the conductivity of the polycrystalline silicon layer, for example, arsenic ions can be implanted into the polycrystalline sand layer. r ---------- install-- (please read the back first Note $ item and then fill out this page) The paper size of the line book is printed in Chinese National Standard (CNS) A4 (210X 297 public curtain) 03l3twf.doc / 002 A7 B7 Printed by the Employees Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Explanation (ie) Please refer to FIG. 2G, and then use the wet etching method and the etching protection layer 22 as the etching end point to remove the exposed silicon dioxide layer, that is, remove the insulating layers 34 and 30, and the columnar insulation Layers 28a and 28b. With this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is shown as a trunk-like lower polycrystalline silicon layer 26a; 26b, a trunk-like upper polycrystalline silicon layer 38a; 38b And a dendritic polycrystalline silicon layer 32a; 32b having an L-shaped cross section. The trunk-like lower polycrystalline silicon layer 26a; 26b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a T-like profile. The lower end of the trunk-like upper polycrystalline silicon layer 38a; 38b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 26a; 26b, and extends substantially upward. The trunk-like upper polycrystalline silicon layer 38a; 38b is roughly a hollow cylindrical shape, and its horizontal section can be a figure, rectangle, or other suitable shape. The dendritic polycrystalline silicon layer 32a; 32b is recovered from the trunk-like upper layer The inner surface of the crystalline silicon layer 38a; 38b first extends inward in a horizontal direction, and then extends upward in a vertical direction. Since the shape of the storage electrode of the present invention is very special, it is referred to as a "tree-shaped storage electrode" in this specification, and the resulting capacitor is referred to as a "tree-shaped storage capacitor". Please refer to FIG. 2H, and then form a dielectric film layer 40a; 40b on the surfaces of the storage electrodes 26a, 32a, 38a; and 26b, 32b, 38b, respectively. The dielectric film layer 40a; 40b may be, for example, a silicon dioxide layer, a silicon nitride layer, a NO (silicon nitride / silicon dioxide) structure, a ΟΝΟ (silicon dioxide / silicon nitride / silicon dioxide) structure, or any Similar. Then, on the surfaces of the dielectric film layers 40a and 40b, the counter electrode 42 made of polycrystalline silicon is formed. The manufacturing process of the counter electrode can be achieved by the following steps: CVD method is used to precipitate a polycrystalline silicon layer with a thickness of, for example, 1000 angstroms: and then doped with, for example, N-type impurities to improve its conductivity (please read the notes on the back before filling in this Page) • The paper size of the binding and binding book is applicable to China National Standard (CNS) A4 (21〇 < 297 gong) 03 13twf.doc / 002 B7 Printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 2. Description of the invention (θ); Finally, the polysilicon layer is defined by traditional photomask patterning and etching techniques to complete the storage capacitor of each memory cell of DRAM. Although it is not shown in Figure 2H, those familiar with this art should understand that the structure of Figure 2H can be made according to the traditional process technology for bit lines, bonding pads, interconnection wires, and isolation protection layers (passivation) , And packaging, etc., to complete the DRAM integrated circuit. Since these processes are not related to the features of the present invention, they will not be repeated here. In the preferred embodiment, the lowermost polycrystalline silicon layer 26 is defined as a trunk-like lower polycrystalline silicon layer 26a; 26b, which is divided into memory cells in the process steps described in FIG. 2F. However, in accordance with another preferred embodiment of the present invention, the polycrystalline silicon layer 26 can also be defined as a trunk-like lower polycrystalline silicon layer 26a that is divided into memory cells after the deposition described in FIG. 2B; 26b, and then follow similar steps. In the above-mentioned preferred embodiment, the storage electrode has only one layer of dendritic electrode layer like an L-shaped cross section. However, the present invention is not limited to this, and the number of layers of the dendritic electrode layer having a storage electrode resembling an L-shaped cross-section may be two, three, or more. The next preferred embodiment will describe a storage electrode having two dendritic-like electrode layers having an L-shaped cross section. Next, referring to FIGS. 3A to 3E, a second preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is a semiconductor memory of the present invention. The second preferred embodiment of the device manufacturing method is manufactured. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2C, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figures 3A to 3E, the parts similar to those in Figure 2C are the same \ ml HH ί In m (please read the note f on the back of M before filling in this page). County (CNS) A4 present grid (plus X29V;! ^) 3096〇44wfd〇c / ° 02 A7 B7 The Ministry of Economic Affairs Central Bureau of Standardization Beigong Consumer Cooperative printed the fifth, invention description (leaf) number label. Please refer to FIGS. 2C and 3A, and then alternately deposit an insulating layer and a polycrystalline silicon layer by CVD, that is, as shown in FIG. 3A, sequentially insulate an insulating layer 44, a polycrystalline silicon layer 46, and an insulating layer 48 , A polycrystalline silicon layer 50, and an insulating layer 52. The insulating layers 44, 48 and 52 are, for example, silicon dioxide, and the insulating layers 44; 48 and the polycrystalline silicon layer 46; 50 have a thickness of, for example, about 1,000 angstroms, and the insulating layer 52 has a thickness of, for example, about 7000 angstroms. In order to improve the conductivity of the polycrystalline silicon layer, for example, arsenic ions can be implanted into the polycrystalline silicon layer. Please refer to FIG. 3B, and then use the CMP technique to grind the surface of the structure in FIG. 3A at least until the portions above the columnar insulating layers 28a and 28b come out. Please refer to FIG. 3C, and then use Fu Tong ’s photolithography and etching technology to sequentially etch the insulating layer 52, polycrystalline silicon 50, insulating layer 48, polycrystalline silicon layer 46, insulating layer 44, and polycrystalline silicon layer 26. An opening 54 is formed to define the storage electrode of the storage capacitor of each memory cell. That is, by this step, the polycrystalline silicon layers 50, 46, and 26 are cut into sections 50a; 50b, 46a; 46b, and 26a; 26b. Then, polycrystalline silicon sidewalls 56a; 56b are formed on the side walls of the opening 54. In the preferred embodiment, the polycrystalline silicon sidewalls 56a and 56b can be formed by the following steps: depositing a polycrystalline silicon layer with a thickness of, for example, about 1000 angstroms; and then etching back. In order to improve the conductivity of the polycrystalline silicon layer, for example, arsenic ions can be implanted into the polycrystalline silicon layer. Please refer to FIG. 3D, and then use the wet etching method and the etching protection layer 22 as the etching end point to remove the exposed silicon dioxide layer, that is, to remove the insulating layers 52, 48 and 44, and the columnar insulating layer 28a And 28b. Take this step to complete the storage of the storage capacitor of the dynamic random access memory (please read the precautions on the back before filling out this page). Install. The paper is stabbed again _ 家 县 （CNS) 以 秘 （2丨 0 > < 297 publication) 03 I3twf.doc / 002 A7 03 I3twf.doc / 002 A7 Printed B7 by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy V. Invention description (&) pole, as shown in Figure 3D Shown by the trunk-like lower polycrystalline silicon layer 26a; 26b, trunk-like upper polycrystalline silicon layer 56a; 56b, and two layers of dendritic polycrystalline silicon layer 46a, 50a with a L-like cross-section; 46b and 50b together. The trunk-like lower polycrystalline silicon layer 26a; 26b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a T-shaped cross section. The lower end of the trunk-like upper polycrystalline silicon layer 56a; 56b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 26a; 26b, and extends substantially upward. The trunk-like upper polycrystalline silicon layer 56a; 56b is generally hollow and cylindrical, and its horizontal cross-section may be circular, rectangular, or other suitable shape. Two layers of dendritic polycrystalline silicon layers 46a, 50a; 46b, 50b are respectively from the inner surface of the trunk-like upper polycrystalline silicon 56a; 56b, extending inward in the horizontal direction for a distance, and then approximately Extend vertically. Please refer to FIG. 3E, and then form a dielectric film layer 58a; 58b on the surfaces of the storage electrodes 26a, 46a, 50a; and 26b, 46b, 50b, respectively. Then, on the surfaces of the dielectric film layers 58a and 58b, a counter electrode 60 made of polycrystalline silicon is formed. The process of the counter electrode can be achieved by the following steps: depositing a polycrystalline silicon layer with a thickness of, for example, 1000 Angstroms by CVD; then doping with, for example, N-type impurities to improve its conductivity; and finally defined by traditional mask making and etching techniques The polycrystalline silicon layer completes the storage capacitor of each memory cell of the DRAM. In the first and second preferred embodiments described above, the dendritic electrode layers of the storage electrode each have an L-like cross-section. However, the present invention is not limited to this, and the next preferred embodiment will describe a type of dendritic electrode layer having a cylindrical cross-section. Next, with reference to FIGS. 4A to 4D, a third preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention, a semiconducting 18 (please read the note item on the back before filling this page) • Binding. -The paper size of the binding book is applicable to the Chinese National Standard (CNS) A4 (210X297mm) 03 1 3twf.doc / 002 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7_ V. Description of the invention (硌) This preferred embodiment of the volume memory device is manufactured by the third preferred embodiment of a semiconductor memory device manufacturing method of the present invention. The preferred embodiment is shown in FIG. 2C Based on the structure, the DRAM storage electrodes with different structures are made by different processes. In Figures 4A to 4D, the parts similar to those in Figure 2C are marked with the same numbers. Please refer to Figures 2C and 4A, Next, polysilicon sidewall spacers 62a; 62b are formed on the sidewalls of the columnar insulating layers 28a; 28b. In the preferred embodiment, the polysilicon sidewall spacers 62a; 62b can be formed by the following steps: depositing a polycrystalline silicon layer , The thickness of which is, for example, about 1000 angstroms; In order to improve the conductivity of the polycrystalline silicon layer, for example, arsenic ions can be implanted into the polycrystalline silicon layer. Then, a thick insulating layer 64 is deposited by CVD, preferably to fill the columnar insulating layer 28a; 28b of Please refer to Figure 4B, and then use CMP technology to polish the surface of the structure in Figure 4A, preferably until the columnar insulating layers 28a and 28b, and the parts above the polycrystalline sand sidewalls 62a and 62b are exposed Please refer to Figure 4C, and then use the traditional mask making and lithography techniques to sequentially etch the thick insulating layer 64 and the polycrystalline silicon layer 26 to form an opening 66 to define the storage capacitor storage of each memory cell Electrode. That is, this step cuts the polycrystalline layer 26 into sections 26a; 26b. Then, polysilicon sidewalls 68a; 68b are formed on the sidewalls of p 66. Please refer to Figure 4D, followed by wet The contact etching method uses the contact protection layer 22 as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layer M and the columnar insulating layers 28a and 2Sb. This step completes the dynamic random access memory The storage electrode of the body's storage capacitor is as shown in Figure 4D. The Zhang scale applies to the Chinese National Standard (CNS> A4 present format (210X297mm) (please read the precautions on the back before filling in this page) -install · line 03 1 3twf.doc / 002 A7 B7 Central Bureau of Standards of the Ministry of Economic Affairs Printed by the employee consumer cooperative V. Description of the invention (/ 1) Shown as a trunk-like lower polycrystalline silicon layer 26a; 26b, a trunk-like upper polycrystalline silicon layer 68a; 68b, and a class with a column-like profile The dendritic polycrystalline silicon layers 62a; 62b are formed together. The trunk-like lower polycrystalline silicon layers 26a; 26b are connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and have a T-shaped cross section. The lower end of the trunk-like upper polycrystalline silicon layer 68a; 68b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 26a; 26b, and extends substantially upward. The trunk-like upper polycrystalline silicon layer 68a; 68b is generally hollow and cylindrical, and its horizontal cross-section may be circular, rectangular, or other suitable shape. The dendrite-like polycrystalline silicon layers 62a; 62b extend from the upper surface of the trunk-like lower polycrystalline silicon layers 26a; 26b, respectively, generally upward. In this preferred embodiment, the dendrite-like polycrystalline silicon layer 62a; 62b is generally hollow cylindrical 'whose horizontal cross-section can be circular, rectangular, or other suitable shape, mainly in accordance with the columnar insulating layer 28a; 28b Depending on the shape. The dendritic polycrystalline silicon layer 62a; 62b is located inside the trunk-like upper polycrystalline silicon layer 68a; 68b. The following fourth preferred embodiment will describe a structure in which the storage electrode includes a dendritic electrode layer having an L-shaped cross section, and a columnar dendritic electrode layer. The fourth preferred embodiment uses the features of the manufacturing methods of the third and first preferred embodiments to achieve a structure combining the third and first preferred embodiments. Next, a fourth preferred embodiment of a semiconductor memory device with a tree-shaped storage capacitor of the present invention will be described in detail with reference to FIGS. 5A to 5C. This preferred embodiment of a semiconductor memory device is a semiconductor memory of the present invention. The fourth preferred embodiment of the device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2C, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figures 5A to 5C, the parts similar to those in Figure 2C are the same 20 (please read the note $ item on the back and then fill out this page). Pack. The paper size of the binding book is applicable to China National Standard (CNS) A4 specification (2 丨 〇Χ 297mm) 03! 3twf.doc / 002 A7 B7 The Ministry of Economic Affairs Central Prototype Bureau printed by the Consumer Labor Cooperative V. The description of the invention (丨?) Is numbered. Please refer to FIGS. 2C and 5A. Then, on the side walls of the columnar insulating layers 28a; 28b, polysilicon sidewall spacers 70a; 70b are formed, respectively. Polycrystalline silicon sidewall spacers 70a; 70b can be achieved by the following steps: depositing a polycrystalline silicon layer with a thickness of, for example, 100 angstroms by CVD; and then etching back to form the sidewalls. Then, an insulating layer 72 and a polycrystalline silicon layer 74 are sequentially deposited by CVD. After that, a thick insulating layer 76 is deposited. Please refer to FIG. 5B, and then complete the structure shown in FIG. 5B by the similar processes described above for 2E and 2F. That is, using CMP technology, the surface of the structure shown in FIG. 5A is polished, preferably until the columnar insulating layers 28a; 28b, and the polycrystalline silicon sidewall spacers 70a; 70b are exposed. Then, using traditional photomask patterning and etching techniques, the insulating layer 76, the polycrystalline silicon layer 74, the insulating coating 72, and the polycrystalline silicon layer 26 are sequentially etched to form an opening 78 to define the storage capacitor of each memory cell Storage electrode. That is, by this step, the polycrystalline silicon layers 74 and 26 are cut into sections 74a; 74b and 26a; 26b. Then, polysilicon sidewalls 80a; 80b are formed on the side walls of the opening 78. Please refer to FIG. 5C, and then use the wet etching method and the etching protection layer 22 as the etching end point to remove the exposed silicon dioxide layer, that is, remove the insulating layers 76 and 72, and the columnar insulating layers 28a and 28b . By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, as shown in FIG. 5C, which is composed of a trunk-like lower polycrystalline silicon layer 26a; 26b, a trunk-like upper polycrystalline silicon layer 80a 80b, a dendritic polycrystalline silicon layer 70a with a column-shaped cross section; 70b, and a dendritic polycrystalline silicon layer 74a; 74b with an L-like cross section are formed together; (Please read the precautions on the back before filling in this page)-Packing. The paper size of the binding is applicable to the Chinese National Standard (CNS) Μ specification (210X297mm) _6 gas. _02 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (/?) The trunk-like lower polycrystalline silicon layer 26a; 26b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a T-like profile. The trunk-like upper polycrystalline silicon noodle 80a; the lower end of 80b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 26a; 26b, and extends substantially upward. The trunk-like upper polycrystalline silicon layer 80a; 80b is roughly a hollow cylindrical shape, and its horizontal cross-section may be circular, rectangular, or other suitable shape. The dendritic polycrystalline silicon layer 74a with an L-shaped cross section; 74b extends from the inner surface of the trunk-like upper polycrystalline silicon layer 80a; 80b, extending inward in a horizontal direction first and then in a vertical direction Extend upward. The column-like dendritic polycrystalline silicon layer 70a; 70b respectively extends from the upper surface of the trunk-like lower polycrystalline silicon layer 26a; 26b, and extends upward. The dendrite-like polycrystalline silicon layer 70a; 70b is roughly hollow cylindrical. The following fifth preferred embodiment uses different manufacturing methods to form storage electrodes having a similar structural shape as the above fourth preferred embodiment. Next, with reference to FIGS. 6A to 6D, a fifth preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is a semiconductor memory Manufactured in the fifth preferred embodiment of the device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2C, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figs. 6A to 6D, the parts similar to those in Fig. 2C are marked with the same numbers. Please refer to FIGS. 2C and 6A, and then alternately deposit a polycrystalline silicon layer and an insulating layer by CVD, that is, sequentially deposit a polycrystalline silicon layer 84, an insulating layer 86, and a polycrystalline silicon layer as shown in FIG. 6A 88, and a thick insulating layer 90. Please refer to Figure 6B, and then use CMP technology to polish the 6A Figure 22 (please read the precautions on the back before filling this page) -install

、 1T line paper size is applicable to China National Anchor (CNS) A4 specification (210X297mm) 03 1 3twf.doc / 002 A7 B7 Central Provincial Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative Printed V. Invention Description (Μ) The surface, at least until the portions above the columnar insulating layers 28a and 28b are exposed. Please refer to FIG. 6C, and then etch the insulating layer 90, the polycrystalline sand layer 88, the insulating layer 86, the polycrystalline silicon layer 84, and the polycrystalline sand layer 26 in order to form an opening 92 using conventional photomask patterning and etching techniques To define the storage electrode of the storage capacitor of each memory cell. That is, by this step, the polycrystalline silicon layers 88, 84, and 26 are cut into sections 88a; 88b, 84a; 84b, and 26a; 26b. 94b is formed on the side wall of the opening 92 on the side wall of the polycrystalline silicon. Please refer to FIG. 6D, and then use the wet etching method and the etching protection layer 22 as the etching end point to remove the exposed silicon dioxide layer, that is, to remove the insulating layers 90, 86, and the columnar insulating layers 28a and 28b »In this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed. As shown in FIG. 6D, it is composed of a trunk-like lower polycrystalline silicon layer 26a; 26b, a trunk-like upper polycrystalline silicon layer. 94a; 94b, and two layers of dendritic polycrystalline silicon layers 84a, 88a; 84b, 88b having an L-shaped cross section. The trunk-like lower polycrystalline silicon layer 26a; 26b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM, and has a T-like profile. The lower end of the trunk-like upper polycrystalline silicon layer 94a; 94b is connected to the periphery of the trunk-like lower polycrystalline silicon layer 26a; 26b, and extends substantially upward. The trunk-like upper polycrystalline silicon layer 94a; 94b is roughly a hollow cylindrical shape, and its horizontal section may be a figure, a rectangle, or other appropriate shapes. The two dendritic polycrystalline silicon layers 84a, 88a; 84b, 88b respectively extend from the inner surface of the trunk-like upper polycrystalline silicon layer 94a; 94b, extending inward in the horizontal direction for a distance, and then approximately Extend vertically. This preferred embodiment and the above second preferred embodiment (No. 3A to 23 (please read the precautions on the back before filling in this page)-Packing. The paper size of the binding book is applicable to the Chinese National Standard (CNS) to wash the grid ( 210X297mm) 03 1 3twf.doc / 002 A7 B7 5. Description of the invention (d) 3E) The difference in structure lies in the dendritic polycrystalline silicon layer 84a; the lower part of 84b is under the trunk-like shape The upper surface of the polycrystalline silicon layer 26a; 26b is in direct contact, thus forming a shape similar to that of the storage electrode structure of the fourth preferred embodiment described above. In the next preferred embodiment, storage electrodes of different structures are formed by different processes. The storage electrode structure of this preferred embodiment is very similar to the structure of the second preferred embodiment described above, the only difference is that its trunk-like lower polycrystalline silicon layer has a hollow structure 'to increase the surface area of the storage electrode . Next, with reference to FIGS. 7A to 7D, a sixth preferred embodiment of a semiconductor memory device having a tree-type storage capacitor of the present invention will be described in detail. This preferred embodiment of a semiconductor memory device is a semiconductor memory Manufactured in the sixth preferred embodiment of the device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2A, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figs. 7A to 7D, the parts similar to those in Fig. 2A are marked with the same numbers. Please refer to FIGS. 7A and 2A. Next, a planarized insulating layer 96 is deposited by CVD, for example, BPSG. Then, an etch protection layer 98, such as a silicon nitride layer, is deposited by CVD. Afterwards, the etching protection layer 98, the planarization insulating layer 96, and the gate oxide layer I4 are sequentially etched in order to form storage electrode contact windows 100a and 100b, which are respectively etched The upper surface of the protective layer 98 extends to the surfaces of the drain regions 16a and 16b. Next, a polycrystalline silicon layer 102 is deposited. In order to improve the conductivity of the polycrystalline silicon layer, for example, arsenic ions can be implanted into the polycrystalline 24 (please read the precautions on the back before filling this page)-installed.

、 1T The standard paper size of the printed copy of the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is applicable to China ’s National Sample Rate (CNS) Α4 specification (210 × 2 () 7 mm) 03 \ 3twf.doc / 002 A7 B7 Ministry of Economic Affairs The Consumer Cooperative printed the five 'invention description (recognition) in the silicon layer. As shown, the polycrystalline silicon layer 102 covers the surface of the etching protection layer 98 and the inner wall surfaces of the storage electrode contact windows 100a and 100b, but the storage electrode contact windows 100a and 100b are not filled, so The polycrystalline silicon layer 102 has a hollow structure part with a U-shaped cross section. Please refer to FIG. 7B, and then deposit a thick insulating layer, such as a silicon dioxide layer, with a thickness of about 7000 angstroms. Then, the traditional photomask patterning and etching techniques are used to define the insulating layer, thereby forming the columnar insulating layers 104a and 104b as shown. The preferred positions of the columnar insulating layers 104a and 104b generally correspond to the areas above the drain regions 16a and 16b, respectively, and can fill the hollow structure portion of the polycrystalline silicon layer 102. Notches 106 are formed between the columnar insulating layers. Then, a manufacturing method similar to the second preferred embodiment, that is, those described in FIGS. 3A to 3D, is used to complete the storage electrode structure of the preferred embodiment. Please refer to FIG. 7C, then alternately deposit an insulating layer and a polycrystalline silicon layer by CVD, that is, sequentially deposit an insulating layer 106, a polycrystalline silicon layer 108, an insulating layer 110, a polycrystalline silicon layer 112, and One thick insulating layer 114. Then, using the CMP technique, the surface of the structure is polished at least until the portions above the columnar insulating layers 104a and 104b are exposed. Please refer to FIG. 7D, and then etch the insulating layer 114, the polycrystalline silicon layer 112, the insulating layer 110, the polycrystalline silicon layer 108, the insulating layer 106, and the polycrystalline sand layer 102 in sequence using traditional photomask patterning and etching techniques, An opening is formed to define the storage electrode of the storage capacitor of each memory cell. That is, by this step, the polycrystalline silicon layers II2, 108, and 102 are cut into sections 112a; 112b, 108a; 108b, and 102a; 102b. Then, polycrystalline silicon sidewalls 116a; 116b are formed on the side walls of the opening. After that, using wet etching method and etching protection layer 98 as the end point of etching, the exposed silicon dioxide layer is removed to 25. The paper standard is applicable to China National Standard (CNS) A4 specification (210X297mm) (Please read first Note on the back and then fill out this page) • Install.,?! Line 03 1 3twf doc / 〇〇2 B7 Economic Zou Central Standards Bureau employee consumer cooperative printed five. Description of invention () >) Except that the insulation is removed The layers 114, 110 and 106, and the columnar insulating layers ^ q and 104b. This step completes the storage electrode of the storage capacitor of the dynamic random access memory, which is very similar to the structure of FIG. 3D as shown in FIG. 7D. The difference is that the trunk-like lower polycrystalline silicon layer 102a; 102b has a hollow structure part to increase the surface area of the storage electrode. In the next preferred embodiment, different structures are formed by different processes The storage electrode structure of this preferred embodiment is very similar to the structure of the second preferred embodiment described above, except that its trunk-like surface of the lower part of the lower polycrystalline sand layer is not protected from etching underneath Floor Touch 'a distance away' to increase the surface area of the storage electrode. Next, referring to Figures 8A to 8E, the seventh preferred embodiment of a semiconductor memory device with a tree-shaped storage capacitor according to the present invention will be described in detail. This preferred embodiment is manufactured by the seventh preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2A 'The Dram storage electrodes with different structures are made in different processes. In Figures 8A to 8E, the parts similar to those in Figure 2A are marked with the same numbers. Please refer to Figures 8A and 2A, and then use the CVD method A planarized insulating layer 120 'is deposited, for example, BPSG. Then, a protective layer 122, which is a silicon nitride layer, is deposited by CVD, for example, a silicon nitride layer. An insulating layer 124' is deposited by CVD, for example: Silicon dioxide, for example, about 2000 Angstroms thick. Afterwards, using traditional photomask patterning and etching techniques, the insulating layer 124, the etching protective layer 122, the planarizing insulating layer 120, and the gate oxide layer 1 are etched in sequence 4 'to form storage electrode contact windows 126a and 126b, which are divided into 26

(Please read the precautions on the back before filling in this page)-Install ·, • 11 lines 309644 wf. Doc / 002 B7 5. Description of the invention (impediments) Do not extend from the upper surface of the insulating layer 124 to the drain region l6a and 1 surface. Next, a polycrystalline silicon layer 28 is deposited. As shown in the figure, the compound crystal is filled with the storage electrode contact window and 126b, and covers the surface of the insulating layer 128. Please refer to Figure 8B for 124, and then deposit a thick insulating layer of silicon oxide with a thickness of about 7000 angstroms. Reuse. 1. The insulation layer is defined as in the technique, thus forming the pillars and 130b as shown in the figure. The columnar insulating layers 130a and 130b are notched 129 corresponding to the areas above the drain regions 16a and 16b. Insulation-like insulation The Ministry of Economic Affairs Central Standards Bureau employee consumer cooperative printing and printing and then using a manufacturing method similar to the second preferred embodiment, # β 3Α to 3D figure described 'Complete the storage of this preferred embodiment of the electricity Figure 8C, then alternately sink the insulating structure by CVD method. The crystalline silicon layer, that is, depositing an insulating layer 132, a polycrystalline sand layer, an insulating layer 130, a polycrystalline silicon layer 138, and a thick insulating layer 140 in sequence, and then using CMP technology to polish the structure The surface, at least until the portions above the columnar insulating layers 130a and 130b are exposed. Please refer to Figure 8D for "following the use of traditional mask patterning and etching techniques" to sequentially etch the insulating layer 140, polycrystalline silicon layer 138, insulating layer 131, polycrystalline silicon layer 134, insulating layer 132, and polycrystalline silicon layer 128, an opening 142 'is formed to define the storage electrode of the storage capacitor of each memory cell! That is, the polycrystalline silicon layers 138, 134, and 128 are cut into sections 138a; 138b, 134a; 134b, And 128a; 128b. Then, a polycrystalline silicon edge wall is formed on the side wall of the opening M2 丨 44a; 丨 44b. Please refer to Figure 8E, followed by the wet etching method and the etching protection layer 27 papers (applicable to the Chinese National Sample Rate (CNS) A4 specification (2 丨 〇χ297)) {read the precautions before reading the back Refill " this page j etc .- * 1T · 03 1 3twf.doc / 002 A7 B7 5. Description of the invention (122 is the end point of the engraving 'remove the exposed sand dioxide layer', that is, remove the insulating layers 140, 136, 132 and 124, and columnar insulating layers 130a and 130b. With this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is very similar to the structure shown in FIG. In the trunk-like lower polycrystalline silicon layer 128a; the lower surface of the horizontal portion of 128b is not in contact with the etching protection layer 122 below it and is at a distance to further increase the surface area of the storage electrode. In the preferred embodiment, the dendritic electrode layer of the storage electrode is a single-node upright member or a two-section bent member with an L-shaped cross section. However, the present invention is not limited to this kind of dendritic electrode layer due to bending The number of sections can be three , Four sections, or more. The next preferred embodiment will describe a dendritic electrode layer with a four-section storage electrode. Next, referring to FIGS. 9A to 9E, a tree-shaped storage capacitor of the present invention will be described in detail. The eighth preferred embodiment of the semiconductor memory element of the semiconductor memory device, this-the preferred embodiment is manufactured by the eighth preferred embodiment of a method for manufacturing a semiconductor memory element of the present invention. Based on the structure of the preferred embodiment shown in Fig. 2B, DRAM storage electrodes with different structures are fabricated by different processes. In Figs. 9A to 9E, the parts similar to those in Fig. 2B are given the same number Please refer to Figures 9A and 2B, and then deposit a thick insulating layer, such as silicon dioxide, with a thickness of about 7000 angstroms. Then, a photoresist layer 152 is formed using traditional photomask plate-making technology Isotropically etch a part of the exposed insulating layer, thus forming a raised insulating layer as shown in the picture 丨 50a 28 (Please read the precautions on the back before filling this page)-* Employee of Central Falcon Bureau, Ministry of Economic Affairs Dispel This paper cooperatives printed poly scale applicable Chinese National Standard (CNS) Λ4 Size (210x 297 mm) 03 1 3twf.doc / 〇02

Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs V. Invention Instructions (4) and 150b. Please refer to FIG. 9B, and then the photoresist erosion (Photoresist erosion) technique is used to remove the photoresist layer i52-thickness to form a thinner and smaller photoresist layer 152a, thereby exposing one of the raised insulating layers 150a and 150b Part of the upper surface. Please refer to FIG. 9C again, and then anisotropically etch the raised insulating layers 150a and 15 (^ the exposed upper surface portion and the remaining insulating layer until the polycrystalline silicon layer 26 is exposed to form Stepped columnar insulating layer 15c and 150d structure. Finally, the photoresist is removed. Then, the present preferred embodiment is completed by a manufacturing method similar to the first preferred embodiment, that is, as described in FIGS. 2D to 2G The storage electrode structure. Please refer to FIG. 9D, and then sequentially deposit an insulating layer I54, a polycrystalline silicon layer 156, and a thick insulating layer 158 by CVD method. Then, using mechanical and chemical grinding technology, the structure of the electrode is polished. The surface is at least until the surface above the columnar insulating layers 150c and 150d is exposed. Please refer to FIG. 9E, and then etch the insulating layer 158 'polycrystalline silicon layer 156 and the insulating layer in sequence using traditional mask patterning and etching techniques The layer 154, and the polycrystalline silicon layer 26 form an opening to define the storage electrode of the storage capacitor of each memory cell. That is, the polycrystalline silicon layers 156 and 26 are cut into several sections 156a by this step; 156b and 26a ; 26b. Then form on the side wall of the opening The polysilicon sidewalls 159a and 159b are formed. Then, the exposed silicon dioxide layer is removed by the wet etching method and the etching protection layer 22 is used as the etching end point, that is, the insulating layers 158 and 154 and the columnar insulation are removed Layer 15〇c and I50d. This step is to complete the storage electrode of the storage capacitor of the dynamic random access memory, which is shown in Figure 9E 29. The paper size is not in line with the Chinese National Standard (CNS) A4 specification (2 丨0 < 297mm) (Please read the precautions on the back and fill in this page)-燊 · t · -sr 03 I 3twf.doc / 002 03 I 3twf.doc / 002 Central Standard Falcon Bureau Employee Consumer Cooperative Printed B7 V. Description of the invention (PΊ) consists of a trunk-like lower polycrystalline silicon layer 26a; 26b, a trunk-like upper polycrystalline silicon layer 159a; 159b, and a four-section bend-shaped section (or double L-shaped) (Section) of the dendritic polycrystalline silicon layer 156a; 156b together. Dendrite-like polycrystalline silicon layer 156a; 156b is from the inner surface of the trunk-like upper polycrystalline silicon layer 159a; 159b, first extending inward in a horizontal direction, then extending another segment in a vertical direction The distance then extends inward in a horizontal direction, and then extends upward in a vertical direction. According to the conception of this preferred embodiment, the different shapes of the columnar insulating layer or the convex insulating layer can change the extending shape and the extending angle of the dendritic polycrystalline silicon layer. Therefore, the columnar insulating layer or the convex of the present invention The shape of the insulating layer should not be limited to the above. In fact, other methods can also be used to change various shapes. For example, in the case of Figure 2C, if isotropic etching or wet etching is used instead of anisotropic saturation, By etching this thick insulating layer, a triangular-like insulating layer can be obtained; or in the case of FIG. 2C, after the columnar insulating layers 28a and 28b are formed, a side wall insulating layer is formed on the columnar insulating layer 28a and On the side wall of 28b, another column-shaped insulating layer of different shape can also be obtained. Therefore, the dendritic polycrystalline silicon layer can have various extended shapes at different angles. According to the conception of this preferred embodiment, to fabricate more sections of dendritic polycrystalline silicon layer structure, the structure of Figure 9B and 9C can be used as the basis, and then the photoresist etching step and the unevenness of the raised insulating layer Steps are engraved one or more times to form more stepped columnar insulating layers. In the above-mentioned first to eighth preferred embodiments, the polycrystalline silicon layer above the columnar insulating layer is removed by CMP technology. However, the '30 paper size is applicable to China's national standard falcon (CNS specifications (2 丨 0X 297mm (please read the notes on the back of the performance first and then fill in this page) Stranding 03 ntwf.doc / 002 A7 B7 Central Ministry of Economics Falcon Bureau Veritas Consumer Cooperation Du Yin ^ V. Description of the invention (β) The present invention is not limited to this. The next preferred embodiment will describe the use of traditional photomask plate-making and etching techniques to place the complex above the columnar insulating layer. The process of cutting the crystalline silicon layer and the different storage electrode structures thus formed. Next, the ninth preferred embodiment of a semiconductor memory device with a tree-shaped storage capacitor according to the present invention will be described in detail with reference to FIGS. 10A to 10D. This preferred embodiment of the memory element is manufactured by the ninth preferred embodiment of a semiconductor memory element manufacturing method of the present invention. This preferred embodiment is structured as the preferred embodiment shown in FIG. 2C As a basis, different processes are used to make DRAM storage electrodes with different structures. In Figures 10A to 10D, parts similar to those in Figure 2C are marked with the same numbers. Please refer to Figures 10A and 2C, Next, an insulating layer and a polycrystalline silicon layer are alternately deposited by CVD, that is, an insulating layer 160, a polycrystalline sand layer 162, an insulating layer 164, a polycrystalline sand layer 166, and 166 are sequentially deposited as shown in FIG. 10A. A thick insulating layer 168. The insulating layers 160, 164 and 168 are, for example, silicon dioxide, the insulating layer 160; 164 and the polycrystalline silicon layer 162; 166 have a thickness of, for example, about 1000 angstroms. The thickness of the thick insulating layer 168 is preferably Fill the notches on the uneven surface of the polycrystalline silicon layer 166. Please refer to Figure 10B, and then use the traditional mask making and etching techniques to sequentially insulate the insulating layer 168, polycrystalline silicon layer 166, insulating layer 164, polycrystalline The silicon layer 162, the insulating layer 160, and the polycrystalline silicon layer 26 'form an opening 170 to define the storage electrode of the storage capacitor of each memory cell. That is, the polycrystalline silicon layers 166, 162, and 26 are cut by this step Into several sections 166a; 166b '162a; 162b, and 26a; 26b. Then the polycrystalline silicon edge wall 172a is formed on the side wall of the opening 170; 172b ° This paper scale is applicable to China National Standard Falcon (CNS) Α4 specifications (2 丨0x297 male shovel) (Please read the precautions on the back before filling in this page) -Installation. -Β 线 0 3 1 3twf.doc / 0〇2 A7 B7 Fifth, the description of the invention (4) Please refer to figure i〇c 'then use the traditional photomask plate making and etching technology' to sequentially etch the polycrystalline silicon layer 166a; 166b, insulating layer 164, and the polycrystalline silicon layer 162a; 162b 'to form an opening 174a; 174b, for the polycrystalline silicon layer 166a; i66b and i62a; U2b is opened above the columnar insulating layer 28a; 28b, so as to expose the internal two Silicon oxide. * Please refer to Figure 10D, and then use wet etching method, and use the shaft engraved protective layer 22 as the end point of hunger to remove the exposed-oxidized sand layer, that is, remove the insulating layers 168, 164, and 160, and the columnar Insulation layers 28a and 28b. With this step, the storage capacitor storage electrode of the dynamic random access memory is completed, as shown in FIG. 10D, which is composed of a trunk-like lower polycrystalline sand layer 26a; 26b, a trunk-like upper polycrystalline silicon layer 172a; 172b And a two-layer dendritic polycrystalline silicon layer 162a, 166a; 162b, 166b with a three-section bend-shaped cross section. The two-layer dendritic polycrystalline sand layer 162a, 166a; 162b, i66b is from the inner surface of the trunk-like upper polycrystalline sand layer 172a; 172b, extending inward in the horizontal direction for some distance, then in the vertical direction Extend upward for a distance, and finally extend inward approximately horizontally. Those skilled in the art should understand that the above-mentioned conceptual features of the preferred embodiments of the present invention can be used alone or in combination to achieve storage electrodes and storage capacitors of many different structures. The structure of these storage electrodes and storage capacitors should fall within the protection scope of the present invention. It should be noted that although the drains of the transfer transistors in the drawings are all diffused region structures on the surface of the silicon substrate, the invention is not limited thereto, and any suitable drain structure can be applied to the invention, such as trench ) Jiji is—Example 0 32 The paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) (Please read the precautions on the back before filling this page) Printed by the Bureau ’s Consumer Cooperative Society 03 1 3twf. Doc / 002 A7 B7 V. Description of the invention (outside) Furthermore, the shape, size, and extension angle of each component in the diagram should also be noted, for convenience of illustration only The schematic representation made may be different from the actual situation, so it should not be used to limit the present invention. Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the attached patent application. (Please read the precautions on the back before filling in this page) • Packing. Printed and printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 33 This paper size is selected according to the Chinese National Standard (CNS) A4 specification (210X 297mm)

Claims (1)

309644 03 1 3twf.doc / 002 A8 B8 C8 D8 Employee Consumer Cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs Du Yin ¾ 6. Patent application 1. A method for manufacturing a semiconductor memory device with a capacitor, wherein the semiconductor memory device includes a The substrate, a transfer transistor formed on the substrate, and a storage capacitor are electrically coupled to one of the drain and source regions of the transfer transistor. The manufacturing method includes the following steps: a. On the substrate Forming a first insulating layer covering the transfer transistor, cell, b. Forming a first conductive layer, through at least the first insulating layer, and the transfer transistor of the drain and source regions of one Sexual coupling; c. Forming a columnar layer on the first conductive layer; d. Forming a second conductive layer on the surface of the columnar layer and the first conductive layer; e. Defining the second conductive layer , Separate the part above the columnar layer; f. Define the second conductive layer and the first conductive layer to form an opening; g. Form a hollow cylindrical third conductive layer on the side wall of the opening to connect Around the first conductive layer, The third conductive layer and the first conductive layer constitute a type of trunk-shaped conductive layer, and one end of the second conductive layer is connected to the inner surface of the third conductive layer to constitute a type of dendritic conductive layer, and the first , The second and third conductive layers constitute a storage electrode of the storage capacitor; h. Remove the columnar layer; i. Form a dielectric layer on the exposed surface of the first, second and third conductive layers ; And j. On a surface of the dielectric layer, a fourth conductive layer is formed to constitute a counter electrode of the storage capacitor. 2. The manufacturing method as described in item 1 of the patent application scope, wherein the second conductive layer constitutes a type of dendritic conductive layer, which includes an L-shaped cross section 34 (please read the precautions on the back before filling this page) -The size of the paper used for the binding is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 0 < 297). Printed by the Ministry of Economy Central Bureau of Accreditation and Employee Consumer Cooperative A8 03 1 3twf.doc / 002 B8 C8 D8 VI. Application In the patent scope, one end of the L-shaped cross-section is connected to the inner surface of the third conductive layer. 3. The manufacturing method as described in item 1 of the patent application park, wherein the trunk-like conductive layer includes a trunk portion electrically coupled to one of the drain and source regions of the transfer transistor, and has A T-shaped section; and an upper trunk extending substantially upward from the periphery of the lower trunk. 4. The manufacturing method as described in item 1 of the scope of the patent application, wherein the step b includes forming the first conductive layer to have a U-shaped cross-sectional portion. 5. The manufacturing method as described in item 1 of the scope of the patent application, wherein after step a and before step b, a step of forming an etching protection layer on the first insulating layer is further included. 6. The manufacturing method as described in item 1 of the patent application scope, wherein the step e includes etching away a part of the second conductive layer above the columnar layer. 7. The manufacturing method as described in item 1 of the scope of the patent application, wherein the step e includes using a chemical mechanical polishing method to remove the portion of the second conductive layer above the columnar layer. 8. The manufacturing method as described in item 1 of the patent application scope, wherein after step c and before step d, the following steps are further included: forming a second insulating layer on the surface of the columnar layer and the first conductive layer; The step h further includes the step of removing the second insulating layer. 9. The manufacturing method as described in item 1 of the patent application scope, wherein after step d and before step e, the following steps are further included: forming a third insulating layer on the second conductive layer, the third insulating layer is roughly Fill the space in the notch of the second conductive layer; wherein step h further includes removing the third paper 35. The paper size is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X2M mm) (please read the note on the back first Please fill in this page for details)-Install. Order i09644tw f.doc / 002 ABCD Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Steps for applying for the scope of patent scope. 10. The manufacturing method as described in item 1 of the patent application scope, wherein the step C includes the following steps: forming a thick insulating layer on the first conductive layer; forming a photoresist on the thick insulating layer without covering The notched part of the plan; etch away a part of the thick insulating layer that is not covered; etch the photoresist, and then expose a part of the thick insulating layer; etch away a part of the exposed thick insulating layer to the Until the first conductive layer is exposed, the columnar layer formed has a stepped shape; and the photoresist is removed. 11. The manufacturing method as described in item 1 of the patent application scope, wherein after step a and before step b, the following steps are further included: first forming an etching protection layer on the first insulating layer, and then forming a fourth An insulating layer on the etch protection layer; wherein the step b further includes the step of forming the first conductive layer through the fourth insulation layer and the etch protection layer; and wherein the step h further includes removing the fourth insulation layer step. 12. A method for manufacturing a semiconductor memory element having a capacitor, wherein the semiconductor memory element includes a substrate, a transfer transistor formed on the substrate, and a storage capacitor electrically coupled to the transfer transistor On one of the drain and source regions, the manufacturing method includes the following steps: a. Forming a first insulating layer on the substrate, covering the transfer transistor, b. Forming a first conductive layer, through at least The first insulation layer and the 36 (please read the precautions on the back before filling in this page) • Pack. The paper size of the binding book is applicable to the Chinese National Standard (CNS) A4 specification (2I0X297mm) 03 1 3twf.doc / 002 A8 B8 C8 D8 Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs. 6. The patent application scope transfer transistor is electrically coupled to one of the drain and source regions; c. Formed on the first conductive layer A columnar layer; d. On the surface of the columnar layer and the first conductive layer, alternately forming the first and second film layers at least once, the second film layer is made of a conductive material, and the first film The layer system is made of insulating material ; E. Define the second film layer, separating its portion above the columnar layer; f. Define the second film layer, the first film layer and the first conductive layer to form a ~ opening; g. A hollow cylindrical second conductive layer is formed on the side wall of the opening, connected to the periphery of the first conductive layer, the second conductive layer and the first conductive layer constitute a type of trunk-shaped conductive layer, and one of the second film layers The end is connected to the inner surface of the second conductive layer to form a kind of dendritic conductive layer, and the first conductive layer, the second film layer and the second conductive layer constitute a storage electrode of the storage capacitor; h. Remove the post Layer and the first film layer; i. Forming a dielectric layer on the exposed surface of the first conductive layer, the second film layer and the second conductive layer; and j · on a surface of the dielectric layer Above, a third conductive layer is formed to constitute an opposite electrode of the storage capacitor. 13. The manufacturing method as described in item 12 of the patent application scope, wherein the second film layer constitutes a type of dendritic conductive layer, which includes an L-shaped cross-sectional portion, and an end of the L-shaped cross-sectional portion is connected On the inner surface of the second conductive layer " I4 · manufacturing method as described in item 12 of the patent application scope, wherein the trunk-like conductive layer of this type includes the following trunk portion electrically coupled to the transfer transistor 37 (please Read the precautions on the back before filling in this page)-installed ·, 1T This paper standard is applicable to the Chinese national standard falcon (CNS > Α4 specifications (210Χ297 mm) ABCD 03 I 3twf.doc / 002 VI. On one of the drain and source regions, and having a T-shaped cross-section; and an upper trunk extending substantially upward from the periphery of the lower trunk. 15. Manufactured as described in item 12 of the patent application Method, wherein step b includes forming the first conductive layer to have a U-shaped cross-sectional portion. 16. The manufacturing method as described in item 12 of the patent application scope, wherein after step a and before step b, the method further includes Forming an etching protection layer on the The step on the first insulating layer 17. The manufacturing method as described in item 12 of the patent application scope, wherein the step e includes etching away a portion of the second film layer above the columnar layer. 18. If applying The manufacturing method as described in item 12 of the patent scope, wherein the step e includes using a chemical mechanical grinding method to grind away the portion of the second film layer located above the columnar layer. The manufacturing method according to item 1, wherein after step d and before step e, the following steps are further included: forming a second insulating layer on the second film layer, the second insulating layer substantially covering the second film layer The space in the notch; wherein the step h further includes the step of removing the second insulating layer. 20. The manufacturing method as described in item 12 of the patent application scope, wherein the step c includes the following steps: on the first conductive layer A thick insulating layer is formed; a photoresist is formed on the thick insulating layer so as not to cover the notch portion of the plan; a part of the thick insulating layer that is not covered is etched away; the photoresist is etched and then exposed A part of thick insulating layer; 38 ( Read the precautions on the back and then fill out this page) • Installed?,? Τ The paper standard printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is printed in accordance with China National Standard (CNS) Λ4 specifications (210XN7mm). Printed by Consumer Cooperatives 03 1 3twf.doc / 002 DO C8 D8 VI. Patent application scope Etching away part of the exposed thick insulating layer until the first conductive layer is exposed, so that the formed columnar layer has a stepped shape ; And photoresist removal. 21. The manufacturing method as described in item 12 of the patent application scope, wherein after step a and before step b, the method further includes the following steps: first forming an etching protection layer on the first insulating layer, Then, a third insulating layer is formed on the etch protection layer; wherein step b further includes the step of forming the first conductive layer through the third insulation layer and the etch protection layer; and wherein the step h further includes removing The third insulating layer. 22. The manufacturing method as described in item 12 of the patent application scope, wherein the step d includes the following steps: alternately forming the first and second film layers twice, and forming a second insulation on the uppermost second film layer Layer, the second insulating layer substantially fills the space in the recess of the upper second film layer; wherein step e includes the following steps: forming a photoresist that does not cover at least a portion of the area above the columnar layer , Sequentially remove an uncovered second film layer and a first film layer located above, etch the photoresist, and then expose a portion of the second film layer above, to remove the uncovered second film layer Film layer, and photoresist removal; wherein step h further includes the step of removing the second insulating layer. 23. A method for manufacturing a semiconductor memory element with a capacitor, wherein the semiconductor memory element includes a substrate, formed on the substrate 39 (read the precautions on the back side and then fill out this page), 1T textbook size is applicable China National Standard (CNS) Α4 specification (210Χ 297 mm) I096 ^^ twf • doc / 002 A8 B8 C8 D8 Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy Six, a transfer transistor on the scope of patent application, and a The storage capacitor is electrically coupled to one of the drain and source regions of the transfer transistor. The manufacturing method includes the following steps: a. Forming a first insulating layer on the substrate to cover the transfer transistor, b . Forming a first conductive layer through at least the first insulating layer, electrically coupled with one of the drain and source regions of the transfer transistor; c. Forming at least one post on the first conductive layer Stratified layer; d. Forming a second conductive layer on the side wall of the columnar layer; e. Defining the first conductive layer to form an opening; f. Forming a hollow cylindrical third conductive layer on the side wall of the opening, connection The periphery of the first conductive layer, and one end of the second conductive layer is connected to the upper surface of the first conductive layer to form a type of dendritic conductive layer, and the first, second and third conductive layers constitute the A storage electrode of the storage capacitor; g. Removing the columnar layer; h. Forming a dielectric layer on the exposed surfaces of the first, second and third conductive layers; and j. On the dielectric layer On a surface, a fourth conductive layer is formed to constitute an opposite electrode of the storage capacitor. 24. The manufacturing method as described in item 23 of the patent application scope, wherein the second conductive layer constitutes a type of dendritic conductive layer, which includes a cylindrical section-like portion, and an end of the cylindrical section-like portion is connected On the upper surface of the first conductive layer. 25. The manufacturing method as described in item 23 of the patent application range, wherein the first conductive layer has a T-shaped cross section. 40 (Please read the precautions on the back before filling in this page) The size of the paper for binding and ordering is applicable to the Chinese National Standard (CNS> Λ4 specifications (210X297 mm) 0313twf.doc / 002 ABCD Ministry of Economic Affairs Central Standards Bureau Employee's Consumer Cooperative Printed 6. Patent application scope 26. The manufacturing method described in item 23 of the patent application scope, the first conductive layer has a U-shaped cross-section. Wherein 27. The manufacturing method described in item 23 of the patent application scope, steps After a and before step b ', the step of forming-etching the protective layer on the first insulating layer is further included. 28. The manufacturing method as described in item 23 of the patent application scope, wherein after step d and before step e' The method includes the following steps: forming an fth insulating layer on the first conductive layer, the first insulating layer substantially fills the space in the recess of the second conductive layer; wherein the step g further includes removing the second insulating layer Step 29. The manufacturing method as described in item 23 of the patent application scope, wherein step c includes the following steps: forming a thick insulating layer on the first conductive layer; forming on the thick insulating layer Photoresist, does not cover the notch part of the plan; etch away a part of the thick insulating layer that is not covered; etch the photoresist, and then expose a part of the thick insulating layer; etch away the exposed thick insulating layer A part until the first conductive layer is exposed 'so that the columnar layer formed has a stepped shape; and the photoresist is removed. 30. The manufacturing method as described in item 23 of the patent application scope, wherein after step a Before step b, the method further includes the following steps: first forming an etching protection layer on the first insulating layer, and then forming a third insulation layer on the etching protection layer; wherein step b further includes forming the first conductive layer The step of passing through the third insulating layer and the etching protective layer; and among them step 41 (please read the precautions on the back before filling in this page). The paper size of the binding is applicable to the Chinese national standard falcon (CNS 丨 Λ4 Specification (2 × 297 mm) 03 1 3twf.doc / 002 A8 B8 C8 D8 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. The patent application scope h also includes the step of removing the third insulating layer. 31. If applying Patent Fan The manufacturing method according to item 23, wherein the horizontal cross section of the second conductive layer can be a graphic. 32. The manufacturing method according to item 23 of the patent application scope, wherein the horizontal cross section of the second conductive layer can be rectangular. 33. A method of manufacturing a semiconductor memory element having a capacitor, wherein the semiconductor memory element includes a substrate, a transfer transistor formed on the substrate, and a storage capacitor electrically coupled to the transfer transistor On one of the drain and source regions, the manufacturing method includes the following steps: a. Forming a first insulating layer on the substrate to cover the transfer transistor; b. Forming a first conductive layer through at least the A first insulating layer electrically coupled to one of the drain and source regions of the transfer transistor; c. Forming at least one columnar layer on the first conductive layer; d. On the sidewall of the columnar layer , Forming a second conductive layer, one end of the second conductive layer is connected to the upper surface of the first conductive layer; e. On the surface of the second conductive layer and the columnar layer, and the first conductive layer , The interaction forms the first and the first At least one second film layer, the second film layer is made of a conductive material, and the first film layer is made of an insulating material; f. Define the second film layer, separating its portion above the columnar layer Parts; g. Define the second film layer, the first film layer and the first conductive layer, forming an opening; h. Forming a hollow cylindrical third conductive layer on the side wall of the opening, connected to the first conductive The periphery of the layer, the third conductive layer and the first conductive layer structure 42 The paper scale is applicable to the Chinese National Standard (CNS) A4 present grid (210X297mm) I-II .--------- ^- ----- ir ------ ^ (Read the note $ item on the back before filling in this page) Printed by the Ministry of Economic Affairs Central Standard Falcon Bureau Employee Consumer Cooperative A8 Ο3 1 3 twf. doc / 002 β8 C8 D8 6. The scope of patent application is a type of trunk-like conductive layer, and one end of the second film layer is connected to the inner surface of the third conductive layer, and the second film layer and the second conductive layer constitute a type of dendritic conductive layer , And the first, second, third conductive layer and the second film layer constitute a storage electrode of the storage capacitor; i. Remove the columnar layer and the first film ; J. Forming a dielectric layer on the exposed surfaces of the first, second, third conductive layers and the second film layer; and k. Forming a fourth conductive layer on a surface of the dielectric layer The layer constitutes an opposite electrode of the storage capacitor. 34. The manufacturing method as described in item 33 of the patent application range, wherein the second conductive layer constitutes a part of a type of dendritic conductive layer, which includes a column-like section, the column-like section Is connected to the upper surface of the first conductive layer; the second film layer constitutes another part of a kind of dendritic conductive layer, which includes an L-shaped cross-sectional portion, the L-shaped cross-sectional portion One end is connected to the inner surface of the third conductive layer. . 35. The manufacturing method as described in item 33 of the patent application range, wherein the first conductive layer has a T-shaped cross section. 36. The manufacturing method as described in item 33 of the patent application range, wherein the first conductive layer has a U-shaped cross section. 37. The manufacturing method as described in item 33 of the patent application scope, wherein after step a and before step b, a step of forming an etching protection layer on the first insulating layer is further included. 38. The manufacturing method as described in item 33 of the patent application scope, wherein after step e and before step f, the following steps are further included: forming a second insulating layer on the second film layer, the second insulating layer is roughly塡 满 the second film 43 This paper size is suitable for China National Standard Falcon (CNS) A4 specification (210X 297 mm) (please read the precautions on the back before filling in this page) -install. Threading ... tm . Miao You ^^ l «|! F! * W. ^ '' IiuTiTV'-TTjagBfrr-wCTgr Printed 309 sail f.doc / 002 gg C8 D8 by the employee consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The space in the recess; wherein the step i further includes the step of removing the second insulating layer. 39. The manufacturing method as described in item 33 of the patent application scope, wherein the step c includes the following steps: forming a thick insulating layer on the first conductive layer; forming a photoresist on the thick insulating layer without covering The notched part of the plan; touch away a part of the thick insulating layer that is not covered; etch the photoresist and expose a part of the thick insulating layer; etch away a part of the exposed thick insulating layer to Until the first conductive layer is exposed, the formed columnar layer has a stepped shape; and the photoresist is removed. 40. The manufacturing method as described in item 33 of the patent application scope, wherein after step a and before step b, the following steps are further included: first forming an etching protection layer on the first insulating layer, and then forming a third The insulating layer is on the etch protection layer; wherein the step b further includes the step of forming the first conductive layer through the third insulation layer and the etch protection layer; and wherein the step h further includes removing the third insulation layer step. 41. The manufacturing method as described in item 33 of the patent application scope, wherein the horizontal section of the second conductive layer may be a pattern. 42. The manufacturing method as described in item 33 of the patent application scope, wherein the horizontal cross-section of the second conductive layer may be rectangular. 43. The manufacturing method as described in item 33 of the patent application scope, wherein the horizontal cross-section of the third conductive layer may be circular. 44 (Please read the precautions on the back before filling out this page)-Packing. Threading · The paper size is applicable to the national standard (CNS) of t country Λ4 format (210X297 mm) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 03 1 3twf.doc / 002 gg C8 D8 6. Patent application scope 44. The manufacturing method as described in item 33 of the patent application scope, wherein the horizontal section of the third conductive layer may be rectangular. 45. The manufacturing method as described in item 33 of the patent application scope, wherein the step f includes etching away a part of the second film layer above the columnar layer. 46. The manufacturing method as described in item 33 of the patent application scope, wherein the step f includes using chemical mechanical grinding to remove the portion of the second film layer above the columnar layer. 47. A method of manufacturing a semiconductor memory element having a capacitor, wherein the semiconductor memory element includes a substrate, a transfer transistor formed on the substrate, and a storage capacitor electrically coupled to the transfer transistor On one of the drain and source regions, the manufacturing method includes the following steps: forming an insulating layer on the substrate to cover the transfer transistor; forming a trunk-like conductive layer, the trunk-like conductive layer including the trunk portion Electrically coupled to one of the drain and source regions of the transfer transistor, and an upper trunk extending substantially upward from the periphery of the lower trunk; forming at least one type of dendritic conductive layer, including at least one A first extension and a second extension, one end of the first extension is connected to the inner surface of the trunk-like conductive layer, the second extension is at an angle from the other of the first extension The end extends out, and the trunk-like conductive layer and the dendritic-like conductive layer constitute a storage electrode of the storage capacitor; the trunk-like conductive layer and the dendritic-like conductive layer are exposed A dielectric layer is formed on the surface; and 45 (please read the precautions on the back before filling out this page) • Pack. The paper size of the binding book is applicable to the Chinese National Standard (CNS) A4 present grid (210X297mm) 03 I 3twf.doc / 002 A8 B8 C8 D8 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 6. The scope of patent application is on the dielectric layer, forming an upper conductive layer to form a counter electrode of the storage capacitor. 48. A method of manufacturing a semiconductor memory element having a capacitor, wherein the semiconductor memory element includes a substrate, a transfer transistor formed on the substrate, and a storage capacitor electrically coupled to the transfer transistor On one of the drain and source regions, the manufacturing method includes the following steps: forming an insulating layer on the substrate to cover the transfer transistor; forming a trunk-like conductive layer, the trunk-like conductive layer including the trunk portion Electrically coupled to one of the drain and source regions of the transfer transistor, and an upper trunk extending substantially upward from the periphery of the lower trunk; forming at least one type of dendritic conductive layer, the shape of which is approximately Hollow cylindrical, one end of the dendritic conductive layer is connected to the upper surface of the trunk-like conductive layer, and extends upward in a substantially upward direction. The trunk-like conductive layer and the dendritic-like conductive layer constitute A storage electrode of the storage capacitor; forming a dielectric layer on the exposed surface of the trunk-like conductive layer and the dendritic-like conductive layer: and on the A dielectric layer formed on a conductive layer, the storage capacitor to constitute a counter electrode. 49. A method of manufacturing a semiconductor memory device having a capacitor, wherein the semiconductor memory device includes a substrate, a transfer transistor formed on the substrate, and a storage capacitor electrically coupled to the pump transistor On one of the polar and source regions, the manufacturing method includes the following steps: 46 The paper cutting scale is applicable to the Chinese National Standard (CNS) Λ4 is now branded (210X2Q7 turbulence) (please read the note Ϋ on the back and fill in this page). _ Threading 309644 Ag 03 I 3twf.doc / 002 B8 C8 D8 Sixth, the scope of patent application Steps: forming an insulating layer on the substrate to cover the transfer transistor; forming a type of trunk-like conductive layer, the type of trunk-like conductive The layer includes a lower trunk portion electrically coupled to one of the drain and source regions of the transfer transistor, and an upper trunk portion extending generally upward from the periphery of the lower trunk portion; forming a first type of dendrite The conductive layer has a generally hollow cylindrical shape, and one end of the first type of dendritic conductive layer is connected to the upper surface of the trunk-like conductive layer of the type, in a generally upward direction Extending above; forming at least one second type dendritic conductive layer, the second type dendritic conductive layer having an end connected to the inner surface of the trunk type conductive layer, the second type dendritic conductive layer has a direction The outer extension extends outward from the end, and the trunk-like conductive layer and the dendritic conductive layers constitute a storage electrode of the storage capacitor; the trunk-like conductive layer and the dendritic conductive layers are exposed On the surface formed, a dielectric layer is formed; and on the dielectric layer, an upper conductive layer is formed to constitute an opposite electrode of the storage capacitor. (Please read the precautions on the back before filling in this page). Packing., 1T line Printed by the Cooperative Society of the Central Standards Bureau of the Ministry of Economic Affairs 47 This paper standard is applicable to the China National Standard Falcon (CNS) Λ4 specification (210X297 public f)