TW306034B - Semiconductor memory device with capacitor (part 1) - Google Patents

Abstract

A semiconductor memory device with capacitor comprises of: (1) one substrate; (2) one transfer transistor formed on the substrate, and including drain and source region; (3) one storage capacitor electrically coupled to one of drain and source region of the transfer transistor; The storage capacitor comprises of: (1) one trunk-type like conductive layer with one bottom electrically coupled to one of drain and source region of the transfer transistor, and with one upward extending part from the bottom with one approximately upward direction; (2) one branch-type like up conductive layer electrically coupled to above of the trunk-type like conductive layer; (3) at least one branch-type like down conductive layer with one cross section like L-shape and connected to on down surface of the branch-type like up conductive layer, in which the trunk-type like conductive layer, the branch-type like up conductive layer, and type branch-type like down conductive layer constitue one storage electrode of the storage capacitor;(4) one dielectric formed on the trunk-type like conductive layer, and exposed surface of the branch-type down conductive layer; and (5) one up conductive layer formed on the dielectric to constitute one opposed electrode of the storage capacitor.

Description

306034 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 ---___ Β7__ V. Description of the invention (1) The present invention relates to a semiconductor memory device with capacitors (Semiconductor Memory Device), and in particular to a dynamic random A memory cell (Memory Cell) structure of a DRAM (Dynamic Random Access Memory; DRAM), which includes a Transfer Transistor and a tree-type storage capacitor. Figure 1 is a schematic circuit diagram of a memory cell of a DRAM device. As shown in the figure, a memory cell is composed of a transfer transistor T and a storage capacitor C. The source of the transfer transistor τ is connected to a corresponding bit line BL, the drain is connected to a storage electrode 6 (storage e 1 ectrode) of the storage capacitor c, and the gate is connected to the corresponding character line. A counter electrode 8 (〇pp〇sed electrode) of the electric storage device C is connected to a fixed voltage source, and a dielectric film layer 7 is provided between the storage electrode 6 and the counter electrode 8. When the storage capacity of traditional DRAM is less than 1M (mega = million) bits, in the integrated circuit manufacturing process, it is mainly realized by capacitors with two-dimensional space, which is generally known as flat capacitors (pUnar type c- ). -Flat capacitors require a considerable area of the semiconductor substrate to store charge, so they are not suitable for high accumulation. Highly integrated DRAMs, such as those with a storage capacity greater than a bit, need to be realized with capacitors of one-degree space, such as so-called stacked type or trench type capacitors. Compared with the flat-type electronic valley device, the stacked or trench capacitor can still obtain a fairly large 3 "standard scale a" when the size of the memory cell has been further reduced. Please read the precautions on the back before filling out this page).

-IT Ministry of Economic Affairs Central Standard Falcon Bureau Employee Consumer Cooperation Cooperative Printed and Collected 306034 A7 ----- B7_ V. Description of Invention (2) Electric Capacity. Nonetheless, when memory devices enter a higher degree of integration, such as DRAMs with 64M-bit capacity, the simple three-dimensional spatial capacitor structure is no longer suitable. One of the solutions is to use so-called fin type stacking capacitors. For the related technology of green stacked capacitors, please refer to the paper "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs, International Electron Devices Meeting, pp. 592-595, Dec. 1988" by Ema et al. Fin-type stacked capacitors are mainly composed of a plurality of stacked layers of electrodes and dielectric film layers, which extend into a horizontal fin-like structure in order to increase the surface area of the electrodes. The relevant U.S. patents for DRAM fin-type stacked capacitors can be found in Nos. 5,071,783, 5,126,810, 5,196,365, and 5,206,787. Another solution is to use so-called cylindrical type (cylindrical type) stacked capacitors. The related technology of cylindrical stacked capacitors can refer to

The paper "Novel Stacked Capacitor Cell for 64-Mb DRAM" by Wakamiya et al., 1989 Symposium on VLSI Technology Digest

Of Technical Papers, pp. 69-70. Cylindrical stacked capacitors mainly consist of electrodes and dielectric film layers extending into a vertical cylindrical structure in order to increase the surface area of the electrodes. The related U.S. patent of the DRAM barrel stacked capacitor can be referred to No. 5,077,688. As the degree of accumulation continues to increase, the size of the dram memory cell will continue to shrink. As known to those skilled in the art, as the size of the memory cell decreases, the capacitance of the storage capacitor also decreases. Decreasing the capacitance value will increase the chance of soft errors caused by the incident α rays. Therefore, this artist still uses the 4 Chinese paper standards (CNS) Λ4 regulations ^ Τ2Κ) Χ ：! 97 公 f) (please read the precautions on the back and then fill out this page) — 装 ·,? Τ 3〇 6〇34 A7 B7 V. Description of the invention (3) ~ ~ We are constantly looking for new staggered capacitor structures and their manufacturing methods, hoping to maintain the desired capacitance value when the plane size occupied by the storage capacitor is reduced. Therefore, a main object of the present invention is to provide a semiconductor memory device having a capacitor, the capacitor having a tree structure to increase the surface area of the storage electrode of the capacitor. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy and Economics in accordance with the present invention-Features "-A semiconductor memory element with a capacitor includes-a substrate;-A transfer transistor is formed on the substrate and includes the set electrode and the source region · And—storage capacitor, electrically coupled to the pole-setting region of the switch transistor. The storage capacitor includes a trunk-like conductive layer with a bottom, electrically coupled to the drain region of the transfer transistor, and a trunk-like conductive layer with an upward extension in a generally upward direction from the bottom Stretch out. The storage capacitor also includes at least a dendritic conductive layer having an L-like cross-section, and the end of the dendritic conductive layer is connected to the outer surface of the trunk-like conductive layer. The trunk-like conductive layer and the dendritic-like conductive layer constitute the storage electrode of the storage capacitor. -The dielectric layer is formed on the exposed surface of the trunk-like conductive layer and the dendritic conductive layer. An upper conductive layer is formed on the electrical layer ± to constitute the opposing electrode of the storage capacitor. According to a preferred embodiment of the present invention, the storage capacitor may include two or more substantially parallel dendritic conductive layers, each of which has an L-shaped cross section, and one end thereof is connected to the trunk-like conductive The outer surface of the layer. The free ends of these dendritic conductive layers are unequal in height. According to another preferred embodiment of the present invention, the storage capacitor may further include a second conductivity increaser, which has an appearance connected to a trunk-like conductive layer at the end. The paper size is applicable to the Chinese National Standards (CNS) A4 specification (210 X 297 male seam) A7 ____________B7 printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (4) The surface and an external extension extend from the end outward in a generally horizontal direction. The second conductive layer is located below the dendritic conductive layer. According to yet another preferred embodiment of the present invention, the trunk-like conductive layer may include a lower trunk portion electrically coupled to the drain region of the switch transistor, and having a T-shaped cross section; and an upper trunk portion It extends from the upper surface of the lower trunk. The end of the dendritic conductive layer is connected to the outer surface of the upper trunk. The upper trunk portion may have a U-shaped section. The trunk-like conductive layer may also have a U-like profile. The dendritic conductive layer may also have a double l-shaped cross section. According to another feature of the present invention, a semiconductor memory device having a capacitor includes a substrate; a transfer transistor is formed on the substrate and has a drain and a source region; and a storage capacitor electrically coupled to the transfer circuit On the drain region of the crystal. The storage capacitor includes a type of trunk-like conductive layer with a bottom, which is electrically coupled to the drain region of the transfer transistor. The trunk-like conductive layer has-an upwardly extending portion-extending from the bottom in a substantially upward direction. The storage capacitor also includes at least one type of dendritic conductive layer, and the dendritic conductive layer includes at least a first extension and a second extension. One end of the first extension is connected to the outer surface of the trunk-like conductive layer, and the second extension extends from the other end of the first extension at an angle. The trunk-like conductive layer and the dendritic-like conductive layer constitute a storage electrode of the storage capacitor. A dielectric layer is formed on the exposed surface of the trunk-like conductive layer and the branch-like conductive layer. -An upper conductive layer is formed on the dielectric layer 'to constitute an opposite electrode of the storage capacitor. 6 The standard size of the paper (21GX297M) —————- (please read the precautions on the back before filling this page)

-C60 Printed Α7 Β7 · * ·, Description of Invention (5) ~~ In accordance with yet another preferred embodiment of the present invention, the dendritic conductive layer may further include a third extension section, It extends from the second extension at a second angle. Both the first extension and the third extension extend approximately in a horizontal direction, while the second extension extends approximately in a vertical direction. According to still another feature of the present invention, a semiconductor memory device having a capacitor includes a substrate; a transfer transistor is formed on the substrate and has drain and source regions; and a storage capacitor electrically coupled to the transfer circuit On the drain region of the crystal. The storage capacitor includes a trunk-like conductive layer with a bottom that is electrically coupled to the drain region of the transfer transistor. The trunk-like conductive layer has a cylindrical extension in a generally upward direction from The bottom extends out. The storage capacitor also includes at least one type of dendritic conductive layer having a factory end connected to the outer surface of the trunk-like conductive layer. The dendritic-like conductive layer further has an outwardly extending portion, and a trunk-like conductive layer and a dendritic-like conductive layer extending outward from the end constitute a storage electrode of the storage capacitor. A dielectric layer is formed on the exposed surface of the trunk-like conductive layer and the dendritic-like conductive layer. An upper conductive layer is formed on the dielectric layer to constitute an opposite electrode of the storage capacitor. According to yet another preferred embodiment of the present invention, the cylindrical extension of the trunk-like conductive layer includes a hollow portion. Also, the outwardly extending portion of the dendritic conductive layer has a section with a multi-node bending shape. The storage capacitor may also include a plurality of dendritic conductive layers extending substantially in parallel, and one end of each dendritic conductive layer is connected to the outer surface of the trunk-like conductive layer. The above and other objectives, features, and advantages of the present invention can be more clearly understood for the purpose of θ. The following are some preferred embodiments, in conjunction with the attached drawings, for details. 7 This paper size applies to China ^ ίΤ ^ Τ ^ Τ2 · Γ〇χ297 Gongchu) (Please read the precautions on the back before filling out this page) 丨 Installed-, 1T Printed by the employee consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 __ B7 V. Description of the invention (6) ~ '~~ ~~ — The detailed description is as follows: A brief description of the diagram: Figure 1 is a schematic diagram of the circuit of a DRAM component-Kede unit. Figures 2A to 2G are a series of cross-sectional views for explaining the first preferred embodiment of a method of manufacturing a semiconductor memory device of the present invention, and the first preferred embodiment of a semiconductor memory device of the present invention. Figures 3A to 3D are a series of cross-sectional views for explaining the second preferred embodiment of the semiconductor memory device manufacturing method of the present invention and the second preferred embodiment of a semiconductor memory device of the present invention. FIGS. 4A and 4B are cross-sectional views for explaining the third preferred embodiment of the semiconductor memory device manufacturing method of the present invention and the third preferred embodiment of the semiconductor memory device of the present invention. Figures 5A to 5D are a series of cross-sectional views for explaining a fourth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a fourth preferred embodiment of a semiconductor memory device of the present invention. FIGS. 6A and 6B are cross-sectional views for explaining a fifth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a fifth preferred embodiment of a semiconductor memory device of the present invention. FIGS. 7A and 7B It is a cross-sectional view for explaining a sixth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a sixth preferred embodiment of a semiconductor memory device of the present invention. 8A to 8F are a series of cross-sectional views for explaining a seventh preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a seventh preferred embodiment of a semiconductor memory device of the present invention. 8 The size of this paper is in accordance with Chinese National Standard (CNS) 8.4 specifications (210X297 mm) --- 1-,, --- {I installed ------, 玎 ------ ^ (please Read the precautions on the back before filling in this page} 306034 A7 is printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ ---—— __ V. Description of the invention (7)-~~-, 9A to 9D drawing system— A series of cross-sectional views to explain the eighth preferred embodiment of the semiconductor memory device manufacturing method of the present invention and the eighth preferred embodiment of the semiconductor memory device of the present invention. Is a series of cross-sectional diagrams for explaining a ninth preferred embodiment of a method for manufacturing a semiconductor memory device of the present invention, and a ninth preferred embodiment of a semiconductor memory device of the present invention. 2G, detailing the first preferred embodiment of a semiconductor memory device with a tree-shaped storage capacitor of the present invention, this preferred embodiment of a semiconductor self-memory device is manufactured by a semiconductor memory device of the present invention Manufactured by the first preferred embodiment of the method. Please refer to Figure 2A, first The surface of a silicon substrate 10 is subjected to a thermal oxidation process, for example, by local oxidation of silicon (L〇c〇s) technology, thus forming a field oxide layer 12, the thickness of which is about 300 angstroms (angstr〇). ms). Then, the silicon substrate 10 is subjected to a thermal oxidation process to form a gate oxide layer 14 ′ with a thickness of, for example, about 15 angstroms. Then, a CVD (chemical vapor deposition) or LPCVD (low pressure CVD) method is used On the entire surface of the silicon substrate 10, a polycrystalline silicon layer is deposited with a thickness of, for example, about 2000 angstroms. In order to improve the conductivity of the polycrystalline silicon layer, phosphorus ions can be implanted into the polycrystalline silicon layer. Preferably A refractory metal layer can be deposited, and then an annealing step is performed to form a metal polycrystalline silicon compound layer (polycide) to further improve its conductivity. The refractory metal can be, for example, tungsten ( Tungsten), the deposition thickness is for example about 2000 angstroms. After that, the metal polycrystalline silicon compound layer is defined using traditional photolithography and etching techniques, thus forming the paper wave scale as shown in Figure 2A. China Standard (CNS) Λ4 specifications (210X297mm) --- 1--L ---- ^ I installed ------ ordered ------ (Please read the notes on the back before filling this page } Α7 Β7 3〇6〇34, invention description (8) ~~~ 'shown gate (or word line) WL1 to WL4. Then, for example, arsenic ions are implanted into the silicon substrate 10 to form a The polar regions 16a and 16b, and the source regions 18a and 18b. In this step, the word lines WL1 to WL4 are used as a mask layer, and the dose of ion implantation is, for example, about ix 10i5 at〇ms / cm2, The energy is about 70KeV. 2. Please refer to FIG. 2B. Next, a planarized insulating layer 20 is deposited by CVD, which is, for example, bpsg (boron phosphorus silicon broken glass), and has a thickness of about 7000 angstroms. Then, an etching protection layer (etching technology layer) 22 is deposited by CVD, which is, for example, a silicon nitride layer (si [icon nitride]) with a thickness of about 1000 angstroms. After that, a thick insulating layer, for example a silicon dioxide layer, is deposited with a thickness of about 7000 Angstroms. The traditional photomask patterning and etching techniques are then used to define the insulating layer, thus forming a columnar insulating layer 24 as shown (insulatingpiiur > notch 23 is formed between the columnar insulating layers 24. Although the columnar insulating Layer 24 is drawn to be separated independently, but it is only for the convenience of drawing and explanation. In fact, from the top view, it is connected together. Please refer to Figure 2C, and then deposited in sequence by CVD method -An insulating layer 26,-a polycrystalline silicon layer 28, and an insulating layer 30. The green layers 26 and 30 are, for example, silicon dioxide, and the thickness of the insulating layer 26 and the polycrystalline silicon layer 28 are, for example, about 10,000 angstroms. The thickness of the insulating layer 30 is, for example, about 7000 angstroms. In order to improve the conductivity of the polycrystalline silicon layer 28, arsenic ions can be implanted into the polycrystalline wonderful layer. Please refer to FIG. 2D, and then use the mechanical CMp (mechanical poUsh; CMp) technology, which polishes the surface of the first figure structure, at least until the polycrystalline silicon layer 28 is cut into several sections 28a and 2 ribbed paper scales in the _ home standard (CNS) Μ specification (27 ^ 79_7 Public Broadcast) (Please read the precautions on the back before filling out this page) 丨 Install. 1Τ Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 51 Printed A7 B7, Invention Instructions (9) ~ by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, please refer to Figure 2E, then use traditional photomask plate making and etching techniques The insulating shield 30, the polycrystalline silicon layers 28a and 28b, the insulating layer 26, the etch protection layer 22, the planarization insulating layer 20, and the gate oxide layer 14 are sequentially etched to form a storage electrode contact window c〇ntact holes) 32a and 32b, which extend from the upper surface of the insulating layer 30 ^ the surface of the drain region 16a and 16b. Then 'refill (refiu) polycrystalline silicon 34a and 34b to the storage electrode contact window 32a and 3 ribs. This polysilicon refill process can be achieved by depositing a polysilicon layer by CVD and then etching back. Please refer to Figure 2F, then use wet etching (wet slave), and use The etching protection layer 22 is an etching end point, and the exposed silicon dioxide layer 2 is removed, that is, the insulating layers 30 and 26, and the columnar insulating layer 24 are removed. By this step, the storage capacitor of the dynamic random access memory is completed The storage electrode 'is shown in the figure by the class tree Dry polycrystalline silicon layer 34a; 3 bounces, and a dendritic polycrystalline broken layer 28a with an L-shaped cross-section; it is made up. 5 Dry polycrystalline sand layer such as Can is connected to the transfer transistor 16b. Dendrite-like polymorphic yushi (a); moved away from the trunk-like layer 34a; the outer surface of Can, firstly extends in a horizontal direction-segment: after separation, and then extends in a vertical direction. Due to the storage electrode of the present invention It is very special, so in this specification, it is called "tree-shaped storage electrode," and the capacitor made therefrom is called "tree-shaped storage capacitor." 2According to the 2G [g ', then on the storage electrode 34a, such as and ⑽, for example, πτ & form a dielectric film layer 36a; 36b, respectively. Dielectric film layer 36a; 36b silicon oxide; ceremonial oxidation layer 1 ′ 5 evening nitride layer, N0 ″ evening nitride / diode 〇N〇 (—silicon oxide / silicon nitride / silicon dioxide) structure , 1 1 paper-like degree Lai Zhong Coffee ^ ^ I installed ------ order ------ {V (please read the precautions on the back before filling out this page) A7 Employee consumption of Central Standard Falcon Bureau Cooperative Society Printed Fifth, Invention Description (10) or any similar. Then, on the surfaces of the dielectric film layers 36a and 36b, a counter electrode 38 made of polycrystalline silicon is formed. The process of the counter electrode can be achieved by the following steps Depositing a polycrystalline silicon oxide layer by CVD with a thickness of, for example, 1,000 Angstroms; then doping with, for example, N-type impurities to improve its conductivity; and finally defining the polycrystalline silicon layer by traditional photomask patterning and etching techniques, Complete storage capacitors for each memory cell of DRAM. Although not shown in Figure 2G, those familiar with this art should understand that the structure of Figure 1 can be used to manufacture bit lines, bonding pads, and interconnecting wires according to traditional manufacturing techniques. (Interc〇nnection), isolation protection layer (passivation), and packaging, etc., to complete the Maolai Circuit. Since these processes are not related to the features of the present invention, they will not be repeated here. In the preferred embodiment, the storage electrode has only one layer of dendritic electrode layer. However, the present invention is not limited to this. The number of layers of the dendritic electrode layer B of the storage electrode may be two, three, or more. The next preferred embodiment will describe a storage electrode having a two-layer dendritic electrode layer. 3D diagram, detailing the second preferred embodiment of the present invention-a semiconductor memory device with a tree-shaped storage capacitor, this preferred embodiment of a semiconductor memory device, a device, is a semiconductor memory device of the present invention Manufactured by the second preferred embodiment of the manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2B, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figures 3A to 3D, 'the parts similar to those in Figure 2β are marked with the same number, read the back 5 first, and then fill in this page I. Please refer to Figures 2B and 3A for binding. Then alternate deposition by CVD method Yuanmeihe

Printed A7 B7 by Employee Consumers Cooperative of Zhongshou Standard Falcon Bureau, Ministry of Economic Affairs 5. Description of invention (11) Polycrystalline silicon layer, that is, an insulating layer 40, a polycrystalline sand layer 42 and an insulating layer 44 are deposited in sequence as shown in the figure , A polycrystalline silicon layer 46, and an insulating layer 48. The insulating layers 40, 44, and 48 are, for example, silicon dioxide, and the insulating layers 40; 44 and the polycrystalline silicon layer 42; 46 have a thickness of, for example, about 1000 angstroms, and the insulating layer 48 has a thickness of, for example, about 7000 angstroms. In order to improve the conductivity of the polycrystalline silicon layer, arsenic ions can be implanted into the polycrystalline sand layer. Please refer to FIG. 3B, and then use CMP technology to polish the surface of the structure in FIG. 3A, at least until the polycrystalline silicon layers 42 and 46 are cut into sections 42a; 46a and 42b; 46b. Please refer to FIG. 3C, and then use the conventional mask making and lithography techniques to form a storage electrode contact window, which extends from the upper surface of the insulating layer 48 to the surfaces of the drain regions 16a and 16b, respectively. Then, the polycrystalline silicon 50a and 50b are refilled into the storage electrode contact window. This polycrystalline silicon refill process can be achieved by depositing a polycrystalline silicon layer by CVD and then etching back. Then, using the wet etching method and the etching protection layer 22 as the etching end point, the exposed silicon dioxide layer is removed, that is, the insulating layers 40, 44 and 48, and the columnar insulating layer 24 are removed. With this step mule, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is shown as a trunk-like polycrystalline silicon layer 50a; 50b, and a two-layer tree branch with an L-shaped cross section Shaped polycrystalline silicon layers 42a, 46a; 42b, 46b together. The trunk-like polycrystalline silicon layer 50a; 50b is connected to the drain region 16a of the transfer transistor of the DRAM; 16b. The dendritic polycrystalline silicon layers 42a, 46a; 42b, 46b extend from the outer surface of the trunk-like polycrystalline silicon layer 50a; 50b, extending a distance in the horizontal direction first, and then extending in the vertical direction 0- -i-^ --- Γ I installed ------ ordered ------ Γ bowl (please read the notes on the back before filling in this page) This paper standard is applicable to China National Standard Rate (CNS) A4 size (210X297 mm) The Central Standard Falcon Bureau of the Ministry of Economic Affairs, “Negative Workers’ Consumer Cooperative, Yinben A7 —____ B7_ V. Description of the invention (12) Please refer to the 3D drawing, and then at the storage electrodes 5〇a, 46a, 42 and A dielectric film layer 52a; 52b is formed on the surfaces of 50b, 46b, and 42b, respectively. Then, on the surfaces of the dielectric film layers 52a and 52b, a counter electrode 54 made of polycrystalline silicon is formed. The process of the counter electrode can be The following steps are achieved: depositing a polycrystalline silicon layer by eVD method; then doping with, for example, N-type impurities to improve its conductivity; and finally defining the polycrystalline silicon layer by traditional mask making and etching techniques to complete the storage of each memory cell of DRAM Capacitors. In the above first and second preferred embodiments, the dendritic electrode at the bottom layer of the storage electrode There is a distance between the lower surface and the etching protection layer 22, which is not in direct contact. However, the present invention is not limited to this, the next preferred embodiment will describe the lower surface of the lowermost dendritic electrode layer and the etching The storage electrode structure in which the protective layer 22 directly contacts. Next, referring to FIGS. 4A and 4B, a third preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. The preferred embodiment is manufactured by the third preferred embodiment of a method for manufacturing a semiconductor memory device according to the present invention. The preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2B. Process for making DRAM storage electrodes with different structures. In Figures 4A and 4B, the parts similar to those in Figure 2B are marked with the same numbers. Please refer to Figures 2B and 4A, and then deposit them in sequence by CVD. Crystalline silicon layer 60, an insulating layer 62, a polycrystalline silicon layer 64, and an insulating layer 66. Please refer to Figure 4B 'then use the CMp technique to polish the structure surface shown in Figure ο' at least until the polysilicon Floor 6〇 and 64 are cut into a number of districts ------ order ------ f line (please read the precautions on the back before filling in this page) This paper standard is applicable to China National Standard (CNS) Λ4 specifications (210x 297 Kuang Guang) Printed 306034 A7 by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (13) --- paragraph 60a; 64a and 60b; 64b. Then use traditional photomask to make and etch Technology to form the storage electrode contact window, and then refill the polycrystalline silicon 68a and 6 ribs into the storage electrode contact window. Then, the wet etching method and the etching protection layer 22 are used as the etching end point to remove the exposed silicon dioxide layer. At this point, the mule completes the storage electrode of the storage capacitor of the dynamic random access memory, which is shown as a trunk-like polycrystalline silicon layer 68a; 68b, and a two-layer dendritic polymorph with an L-shaped profile The silicon layer is composed of 6〇a, 64a; 6〇b, 64b. The trunk-like polycrystalline silicon layer 68a; 68b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM. The dendritic polycrystalline silicon layer 60a, 64a; 60b '64b extends from the outer surface of the trunk-like polycrystalline silicon layer 68a; 68b, extending a distance approximately horizontally, then extending approximately vertically The lower surface of the dendritic polycrystalline silicon layer 60a; 60b is in direct contact with the etching protection layer 22, forming a structure different from the above two preferred embodiments. In the first, second, and third preferred embodiments described above, the trunk-like electrode layer of the storage electrode is an integral member. However, the present invention is not limited to this, and the next preferred embodiment will describe the trunk-like electrode layer. It is a storage electrode composed of a plurality of parts. Next, a fourth preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail with reference to FIGS. 5A to 5D. This preferred embodiment of a semiconductor memory device is a semiconductor memory of the present invention. The fourth preferred embodiment of the device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2A. Then, different structures of DRAM storage electrodes are fabricated by different processes. In Figures 5A to 5D, the parts similar to those in Figure 2A are the same numbered specimen paper size applicable to the Chinese National Standard Falcon (CNS > Λ4 specifications (210X 297 mm). · ^ -Installed --- --- Subscribe ------ ^ ^ (Please read the precautions on the back before filling in this page) A7 ______B7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (14)-^ Instructions. Please Referring to FIGS. 2A and 5A, next, a CVD method is used to deposit and planarize the insulating latent 70, which is, for example, BPSG. Then, a CVD method is used to deposit and etch the protective layer 72, which is, for example, a silicon nitride layer. Then, the conventional Photomask patterning and etching techniques sequentially etch the silicon nitride layer 72 and the planarization insulating layer 70 to form storage electrode contact windows 76a and 76b, which extend from the upper surface of the silicon nitride layer 72 to the drain region, respectively The surfaces of 16a and 16b. Then, a polycrystalline silicon layer is deposited by CVD method, so that the polycrystalline silicon fills the storage electrode contact window and 76b, and impurities are added to increase its conductivity. After that, a traditional photomask is used to make a plate And etching technology, define the lower part of each memory cell storage electrode 74a; 74b, As shown in the figure, it has a τ-shaped cross-section. Please refer to Figure 5B, and then deposit a thick insulating layer, such as a silicon dioxide layer. The traditional photomask patterning and etching techniques are then used to define the insulating layer, thus forming The columnar insulating layer 78 is shown in the figure. Then, an insulating layer 80, a polycrystalline silicon layer 82, and an insulating layer 84 are sequentially deposited by the cyj) method. Please refer to FIG. 5C, and then use the CMP technique to polish the surface of the structure in FIG. 5β at least until the polycrystalline silicon layer 82 is cut into sections 82a and 82b. Please refer to FIG. 5D again, and then use traditional photomask patterning and etching techniques to sequentially insulate the insulating layer 84, the polycrystalline silicon layers 82a and 82b, and the insulating layer 80 to form contact windows, which are respectively insulated by The upper surface of the layer 84 extends to the surfaces of the lower portions 74a and 74b of the storage electrode. Then, refill the polycrystalline silicon into the contact window 'to form an upper portion 86a; 86b of each memory cell storage electrode. This polycrystalline silicon refilling process can be deposited by the cVD method—the polycrystalline silicon layer is then etched back 1 6 This paper size is applicable to the Chinese national standard ((please read the precautions on the back before filling this page), binding ----- -^ '-· ___ Printed A7 B7 by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the invention (15) Engraved "Next ⑽ 式 ㈣ 法' and μ engraved the protective layer? 2 is the point of engraving the paper, which will be exposed The oxidized sand layer is removed, that is, the insulating material and the columnar insulating layer 78 are removed. 'At this step, the storage capacitor storage electrode of the dynamic random access memory is completed. Its structural shape and the preferred implementation shown in Figure 2F The difference is that there is one more dendritic polycrystalline sand portion extending approximately horizontally, that is, the horizontally extending portion of the storage electrode lower portion 74a; 74b. In the first to fourth preferred embodiments described above The storage electrode_trunk electrode layer system is a solid member. However, the present invention is not limited to this. The next preferred embodiment will describe a storage electrode structure with a hollow portion like a trunk-like electrode layer system. Figures 6A and 6B detail one of the present invention A fifth preferred embodiment of a semiconductor memory element having a tree-shaped storage capacitor, this preferred embodiment of a semiconductor memory element is manufactured by a fifth preferred embodiment of a method of manufacturing a semiconductor memory element of the present invention. The preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 2D, and then the DRAM storage electrodes with different structures are made by different processes. In FIGS. 6A and 6B, the parts similar to those in FIG. 2D It is marked with the same number 0. Please refer to Figures 6A and 2D, and then use the traditional mask making and etching techniques to 'sequentially etch the insulating layer 30' polycrystalline silicon layers 28a and 28b, insulating layer 26, etching protective layer 22, The insulating layer 20 and the gate oxide layer 14 'are planarized to form storage electrode contact windows 87a and 87b, which extend from the upper surface of the insulating layer 30 to the surfaces of the drain regions 16a and 16b, respectively. Then, please (please Read the precautions on the back first and then fill out this page) 丨 Installation ·-Order (2I〇X 297 ^) Printed by the Ministry of Economic Affairs Central Standard Rate Bureau Employee Consumer Cooperative A7 ______ B7 '. Fifth, the invention description (16) ~~~~ '~ CVD method to deposit a polycrystalline silicon , So that in the storage electrode contact windows 87a and middle, compound bb silicon is only formed on the inner walls of the storage electrode contact windows 87a and 87b, but the storage electrode contact windows 87a and 87b are not filled. After that, the traditional photomask is used to make Etching technology defines the trunk-like polycrystalline silicon layers 88a; 88b of the storage electrodes of each memory cell, as shown in the figure, which has a u-shaped cross-section to increase the surface area of the storage electrode. Please refer to Figure 6B, followed by In the wet etching method, the etching protection layer 22 is used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layers 30 and 26 and the columnar insulating layer 24 are removed. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed. The structure and shape of the storage electrode are different from the preferred embodiment shown in FIG. 2F. The trunk-like polycrystalline silicon layer 88b has a hollow portion. , And presents a 1 | -shaped cross-section, so it has a larger storage capacity. The next preferred embodiment will also describe a storage electrode structure having a hollow portion like a trunk-like electrode layer. Next, referring to FIGS. 7A and 7B, a sixth preferred embodiment of the present invention, a semiconductor memory element having a tree-shaped storage capacitor, will be described in detail. This preferred embodiment of the semiconductor memory element is a semiconductor of the present invention. The sixth preferred embodiment of the manufacturing method of the memory device. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 5C, and then DRAM storage electrodes with different structures are manufactured by different processes. In Figures 7A and 7B | g, parts similar to those in Figure 5C are marked with the same numbers. Please refer to Figures 7A and 5C, and then use the traditional photomask to make and etch 18 paper standards ii / fl f country-country; (CNS) Λ4 specifications (2ι () χ297 Gongguang]-------- (Please read the precautions on the back before filling in this page)-Binding · Order 51 CCC034 a? Employee's Consumer Cooperative Printed by the Central Standards Bureau of the Ministry of Economic Affairs. The crystalline silicon layers 82a and 82b and the insulating layer 80 form contact windows 90a and 90b, which extend from the upper surface of the insulating layer 84 to the surfaces of the lower portions of the storage electrodes 74a and 74b, respectively. Then, a CVD method is used to deposit a The polycrystalline silicon layer is etched back to form side-wal 1 spacers 92a and 92b on the inner walls of the contact windows 90a and 90b. The polycrystalline silicon side walls 92a and 92b constitute the storage electrode The upper part of the trunk-like electrode has a hollow part and presents a U-shaped cross section to increase the surface area of the storage electrode. Please refer to FIG. 7B, followed by the wet etching method and the etching protection layer 72 as Etching the end point, removing the exposed silicon dioxide layer, that is, removing the insulating layers 84 and 80, and Columnar insulating layer 78. At this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, and its structural shape is different from the preferred embodiment shown in FIG. 5D, which is the upper part of the trunk-like electrode of the storage electrode It has a hollow portion and a ^ -shaped cross section. In the above-mentioned first to sixth preferred embodiments, the dendritic electrode layer of the storage electrode is a two-section bending member with an L-shaped cross section. The present invention is not limited to the number of nodes formed by this kind of dendritic electrode layer due to bending, and may be two nodes, four nodes, or more. The next preferred embodiment will describe the dendritic electrode layer having four nodes A storage electrode with a structure. Next, referring to FIGS. 8A to 8F, a seventh preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor according to the present invention will be described in detail. The seventh preferred embodiment of a semiconductor memory device manufacturing method of the invention is manufactured. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 4 Specifications (2jOX 297 ^ y (Please read the Notes on the back to fill out Page) - equipment -

、 1T A7 A7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy " V. Description of the invention (18) — =: Then use different processes to make different structures of glamourous storage electrodes. Please go to Shu 'for the similar parts to Figure 2A For the same temperature, please refer to Figures 8A and 2Α®ια-; Figure, then, a CVD method is used to deposit a planarized insulating layer 100, which is, for example, ΒρςΓ for BPSG. Then, an etch protection layer 102 is deposited by CVD, which is, for example, a nitride layer. After that, a thick insulating layer is deposited, which is for example a layer of sand dioxide. Then, the conventional photomask plate-making technology is used to form the photoresist eyebrow 106, and anisotropically etch the exposed part of the sand dioxide layer, thereby forming the raised layer 104 as shown in the figure. Please refer to FIG. 8β, and then the photoresist erosion technique is used to remove the photoresist layer 106-thickness to form a thinner and smaller photoresist layer 106a, thereby exposing the raised insulating layer 104 -Part of the upper surface. Please refer to FIG. 8C. Then, anisotropically etch the exposed upper surface portion of the raised insulating layer 104 and the remaining insulating layer until the silicon nitride layer 102 is exposed to form a stepped protrusion Insulation layer 丨 〇4a structure. Finally, remove the photoresist. Please refer to Figure 8D, and then follow similar steps described above for Figures 2C and 2D to complete the structure shown in Figure 8D. That is, an insulating layer 108, a polycrystalline silicon layer, and an insulating layer 112 are sequentially deposited by the cvd method. Next, the surface of the structure is polished using mechanochemical polishing technology, at least until the polycrystalline silicon layer is cut into several sections 1 10a and 1 10b. Please refer to Figure 8E, and then use the traditional photomask plate making and etching techniques. The paper size is applicable to the national standard (CNS) Λ4 specification (2 丨 0Χ 297 Gongchu) ---: _ 丨 卜 丨 _ί. 装— — (Please read the precautions on the back before filling out this page) * 1T_ Printed A7 _____ B7 ..... _______ _ by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (19) Sequentially etch the insulating layer 112, the polycrystalline silicon layers 11 Oa and 11 Ob, the insulating layer 108, the etch protection layer 102, the planarization insulating layer 100, and the gate oxide layer 14 'to form storage electrode contact windows U4a and 114b, which is They respectively extend from the upper surface of the insulating layer 112 to the surfaces of the drain regions 6a and 16b. Then, the polycrystalline silicon 116a and 116b are refilled into the storage electrode contact windows 114a and 114b. This polysilicon refill process can be achieved by depositing a polysilicon layer by cvd method and then etching back. Please refer to FIG. 8F, and then use the wet etching method and the etching protection layer 102 as the etching end point to remove the exposed silicon dioxide layer, that is, to remove the insulating layers 112 and 108, and the columnar insulating layer i 〇4a. By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed, which is shown as a trunk-like polycrystalline silicon layer 116a; 116b, and has a four-node bend-shaped cross-section (or double L-shaped (Section) of the dendritic polycrystalline silicon layer u〇a; u〇b together. The trunk-like polycrystalline silicon layer 116a; i16b is connected to the drain region 16a of the transfer transistor of the dram; 16b. The dendritic polycrystalline silicon layer i | 〇a; 11 〇b extends from the outer surface of the trunk-like polycrystalline silicon layer 116a; 116b, extending a distance in the horizontal direction, and then extending another distance in the vertical direction , And then extend a distance in the horizontal direction, and finally extend a distance in the vertical direction. According to the conception of this preferred embodiment, the difference in the shape of the columnar insulating layer or the convex insulating layer can change the extending shape and the extending angle of the dendritic polycrystalline silicon layer. The shape of the raised insulating layer should not be limited to the above. In fact, other methods can also be used to change various shapes, for example, in the case of Figure 2B, if the paper is based on the isotropy (is〇tr〇pic) 2 1 the Chinese National Standard (CNS) Α4 Specifications (2 丨 Οχ 297 Gongchu) (Please read the precautions on the back before filling out this page)

、 1T Yinxian A7 B7, Employee Cooperative of Central Bureau of Standards, Ministry of Economic Affairs V. Invention Description (20) ”Etching or wet etching instead of anisotropic (ani s〇tr〇pic) etching method, the thick insulation layer is implemented Etching can obtain a triangle-like insulating layer; or in the case of FIG. 2B, after forming the columnar insulating layer 24, and then forming a side wall insulating layer on the side wall of the columnar insulating layer 24, another type of Columnar insulating layers of different shapes. Therefore, the dendritic polycrystalline silicon layer can have various extended shapes at different angles. According to the conception of this preferred embodiment, if more sections of dendritic polycrystalline silicon layer structure are to be fabricated, the structure of Figures 8B and 8C can be used as the basis, followed by the photoresist etching step and the time control of the raised insulating layer The non-isotropic etching step mules one or more times to form a more stepped raised insulating layer structure. In the above-mentioned first to seventh preferred embodiments, the storage electrode of each memory cell is divided by CMP technology. However, the present invention is not limited to this, and the next preferred embodiment will describe the process of dividing the storage electrodes of each memory cell by using the conventional mask making and etching techniques, and the different storage electrode structures formed thereby. Next, referring to FIGS. 9A to 9D, the eighth preferred embodiment of the semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail. This preferred embodiment of the semiconductor memory device is provided by the present invention— Manufactured by the eighth preferred embodiment of a semiconductor memory device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 3A, and then DRAM storage electrodes of different structures are manufactured by different processes. In Figs. 9A to 9D, the parts similar to those in Fig. 3A are marked with the same numbers. Please refer to Figures 9A and 3A, and then etch the top layer of the second layer of dioxide dioxide. This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 public) ^ U --- f ^ ------ 、 玎 ------ f (Please read the precautions on the back before filling out this page) A7 A7 Printed B7 by the Ministry of Economy Central Standard Falcon Bureau Employee Consumer Cooperative V. Invention description (21) 48 'Or use CMP technology, The surface of the structure in FIG. 3A is polished until the top polysilicon layer 46 is exposed. This is the structure shown in Fig. 9A. Please refer to FIG. 9B, and then use the traditional mask-making technology to form the photoresist layer 120, and sequentially anisotropically etch the uncovered polycrystalline silicon layer 46, silicon dioxide layer 44, and polycrystalline Silicon layer 42. In this step, the storage electrodes of each memory cell are divided to form polycrystalline silicon sections 42c; 42d; 46c; 46d. Finally, remove the photoresist. Please refer to FIG. 9C 'Then use the traditional mask making and etching technology' to form storage electrode contact windows 122a and 122b, which extend from the upper surface of the insulating layer 48 to the surfaces of the drain regions 16a and 16b ❶ and then The polysilicon 124a and 124b are refilled into the storage electrode contact windows 122a and 122b. This polycrystalline silicon refilling process can be achieved by depositing a polycrystalline silicon layer by CVD and then etching back. Please refer to FIG. 9D. Then, the wet etching method and the etching protection layer 22 are used as the etching end point to remove the exposed silicon dioxide layer, that is, the insulating layers 40, 44 and 48, and the columnar insulating layer 24 are removed. . By this step, the storage electrode of the storage capacitor of the dynamic random access memory is completed. As shown in the figure, it is composed of a trunk-like polycrystalline silicon layer 124a; 124b, and a three-layer tp! J plane The dendrite polycrystal evening layer 42c, 46c; 42d, 46d together. The trunk-like polycrystalline silicon layer l24a; l24b is connected to the drain region 16a; 16b of the transfer transistor of the DRAM. The dendritic polycrystalline silicon layers 42c, 42d, 46d extend from the trunk-like polycrystalline silicon layer 124a; the outer surface of 124b 'first extends a distance in a horizontal direction, and then in a vertical direction 23 ----- --- {丨 装 ------ book ------ ^ Μ (please read the precautions on the back before filling in this page) This paper size is applicable to Chinese national standards (CNS > Λ4 specifications (210X 297 Mm) A7 306034 V. Description of the invention (22) --- extends a distance, and finally extends in a horizontal direction. In any of the above first to seventh preferred embodiments, the dendritic polycrystalline silicon layer The upper ends are approximately at the same horizontal plane; in the eighth preferred embodiment, the outer ends of the dendritic polycrystalline silicon layer are approximately at the same vertical plane. However, the present invention is not limited to this, the eighth In the preferred embodiment, if the photoresist immersion technique is used again, the upper end of the dendritic polymorphic layer 5 can be unequal in height; or the outer end of the dendritic polymorphic sand layer can be located at a different vertical 2 The next example will describe the storage electrode junction with inconsistencies at the upper end of the dendritic polycrystalline silicon layer. Next, the ninth preferred embodiment of a semiconductor memory device having a tree-shaped storage capacitor of the present invention will be described in detail with reference to I10AS l〇D ®, and this-preferred embodiment of a semiconductor memory It device is determined by the present invention -A ninth preferred embodiment of a semiconductor memory device manufacturing method. This preferred embodiment is based on the structure of the preferred embodiment shown in FIG. 9A, and then different structures are manufactured by different processes ⑽Storage electrode. In Figures 10A to 10D, parts similar to those in Figure 9A are marked with the same number. ^ Please refer to Figures 10A and 9A, and then use the traditional photomask plate-making technology to form a light Resist layer 13〇, and anisotropically etch the uncovered polycrystalline silicon layer 46 and the silicon dioxide layer 44❶ In this step, the polycrystalline silicon layer 46 is divided to form a polycrystalline silicon section 46e 46f. Refer to Figure 10B, and then use photoresist etching technique to remove the upper thickness of the nozzle layer to form a thinner and smaller photoresist layer 13〇a, thus exposing one of the polycrystalline silicon layers 46e and 46f Part of the upper surface ◊ Then, anisotropically etch the paper scale_ Home material (CNS) Λ4 specifications ((Please read the notes on the back before filling this page)

• Person-installed I. The Ministry of Economic Affairs, Central Standards Bureau employee consumption cooperation du printed by the Ministry of Economic Affairs, Central Standards Bureau employee consumption cooperative printed A7 ------ B7 V. Invention description (23) ~ ~ Uncovered Fujing 5 The evening layer 4 6 e; 4 6 f; and 4 2. In this step, the polycrystalline sand layers 46e and 46f are further reduced in size to form polycrystalline silicon sections 46g; 46h, and the polycrystalline sand eyebrow 42 is divided to form polycrystalline silicon sections 42g; 42h. Thereafter, the uncovered silicon dioxide layers 44 and 40 are anisotropically etched until the upper end surfaces of the polycrystalline silicon layers 42g and 42h are exposed. Finally, remove the photoresist. Referring to FIG. 10C, the storage electrode contact windows 132a and 132b are formed by conventional mask making and etching techniques, which extend from the upper surface of the insulating layer 48 to the surfaces of the drain regions 16a and 16b, respectively. Then, the polycrystalline silicon 134a and 134b are refilled into the storage electrode contact windows 132a and 132b. This polycrystalline refill process can be achieved by depositing a polycrystalline silicon layer by CVD and then etching back. Please refer to FIG. 10D, and then use the wet etching method and the etching protection layer 22 as the etching end point to remove the exposed silicon dioxide layer, that is, remove the insulating layers 40, 44 and 48, and the columnar insulating layer twenty four. In this way, the storage electrode of the storage capacitor of the dynamic random access memory is completed. As shown in the figure, it is composed of a trunk-like polycrystalline silicon layer 134a; 134b, and a layer of dendritic-like polycrystal with an l-shaped profile The silicon layer 42g, 46g; 42h, 46h together. The trunk-like polycrystalline silicon layer 134a; 134b is connected to the drain region 16a of the transfer transistor of the DRAM; 16b. The dendritic polycrystalline silicon layer 42g, 46g; 42h, 46h from the outer surface of the trunk-like polycrystalline silicon layer i34a; i34b, extending a distance in the horizontal direction, and then extending in the vertical direction, and The dendritic polycrystalline silicon layer 46g; the upper end of 46h is slightly higher than the dendritic polycrystalline silicon layer 42g; the upper end of 42h. Those skilled in the art should understand that the above-mentioned preferred embodiments of the present invention 25 are all suitable for the Chinese National Standard Falcon (CNS) 84 specifications (2i〇X297mm) (please read the precautions on the back before filling in this Page) Order A7 B7 V. Description of the invention (24) — ~ The "conceived features" can be used in addition to individual applications, but can also be used in combination, and then achieve a very wide variety of storage electrodes and storage capacitors of different structures. The structure of these storage electrodes and storage capacitors should fall within the protection scope of the present invention. It should be noted that although the drains of the transfer transistors in the drawings are all diffused region structures on the surface of the silicon substrate, although the present invention is not limited thereto, any suitable drain structure can be applied to the present invention, such as trench ) Jiji is an example. In addition, it should also be noted that the shapes, sizes, and extension angles of various components in the drawings are only schematic representations for convenience of illustration, which may be different from the actual situation, so it should not be used to limit the present invention. . Although the present invention has been disclosed above in a number of preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this art can make some changes and retouching without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the attached patent application. ----! ----- h -installed ------ order ----- k 4 (Please read the notes on the back before filling this page) Central Bureau of Standards, Ministry of Economic Affairs! Printed by Beigong Consumer Cooperative

The size of this paper is suitable for China ^^

Claims (1)

306034 ll -------- D8___ VI. Patent application 1. A semiconductor memory device with a capacitor includes: a substrate; a transfer transistor formed on the substrate and including the drain and source regions ; And a storage capacitor 'electrically coupled to the drain and source regions I ~ "of the transfer transistor, the storage capacitor includes a type of trunk-shaped conductive layer' has a bottom, electrically coupled to the transfer Above the drain and source regions of the transistor, the trunk-like conductive layer has an upward extension, extending from the bottom in a generally upward direction, and at least one type of dendritic conductive layer has a similar The shape of the profile, one end of the dendritic conductive layer is connected to the outer surface of the trunk-like conductive layer, the trunk-like conductive layer and the dendritic conductive layer constitute a storage electrode of the storage capacitor, a dielectric A layer formed on the exposed surface of the trunk-like conductive layer and the dendritic-like conductive layer, and an upper conductive layer formed on the dielectric layer to constitute a relative electricity of the storage capacitor . Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ............... One pack ... (Please read the precautions on the back before filling out this page) Line 2. If applying for a patent | The semiconductor memory device described in item 2, the storage capacitor includes two substantially parallel dendritic-like conductive layers, each of which has an L-like cross-section, and its ends are connected to the trunk-like shape "On the outer surface of the conductive layer" 3. The semiconductor memory device as described in item 2 of the patent application scope, in which the other free ends of the two types of dendritic conductive layers are not located at the same time. The paper size is applicable to the s g * standard (CNS) A4 specification (⑽ public) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4. The semiconductor memory device as described in item i of the patent application scope, wherein the storage capacitor further includes a second conductive layer having an end connected to the trunk-like conductive type The outer surface of the layer and an outwardly extending portion extend outwardly from the end in a substantially horizontal direction. 5. The semiconductor memory device as described in item 4 of the patent application, wherein the second conductive layer is located below the dendritic conductive layer. 6. The semiconductor memory device as described in item 1 of the patent application scope, wherein the trunk-like conductive layer includes a trunk portion electrically coupled to one of the drain and source regions of the transfer transistor, and Has a l-shaped cross section; and an upper trunk extends from the upper surface of the lower trunk. 7. The semiconductor memory device as described in item 6 of the patent application scope, wherein the end of the dendritic conductive layer is connected to the outer surface of the upper trunk portion. 8. The semiconductor memory device as described in item 6 of the patent application scope, wherein the upper trunk portion has a ϋ-shaped cross section. 9. The semiconductor memory device as described in item 1 of the patent application scope, wherein the trunk-like conductive layer of this type has a U-like cross-section. 10. The semiconductor memory device as described in item 丨 of the patent application range, wherein the dendritic conductive layer has a double L-shaped cross section. 11. A semiconductor memory device having a capacitor includes: a substrate; a transfer transistor is formed on the substrate and includes a wave electrode and a source region; and 28 (Please read the precautions on the back before filling in this page)-Install. Order% _ EQing patent scope,-Storage capacitor, electrically coupled to the drain and source regions of the transfer transistor, the storage capacitor It includes a trunk-like conductive layer 'having a bottom, electrically coupled to the garbage electrode and the source region of the transfer transistor, the trunk-like conductive layer having an upward extension' to-generally upward Direction extending from the bottom, at least one kind of dendritic conductive layer, including at least a first-extended section and a second extended section 'The first-extended (iv) -end is connected to the outer surface of the trunk-shaped conductive layer of this type' The first extension section extends from the other end of the first extension section at an angle-, and the trunk-like conductive layer and the dendritic-like conductive layer constitute a storage electrode and a dielectric layer of the storage capacitor. On the exposed surface of the trunk-like conductive layer and the dendritic-like conductive layer, and an upper conductive layer are formed on the dielectric layer to constitute a counter electrode of the storage capacitor. 12. The semiconductor memory element as described in item 1 of the patent application scope, wherein the dendritic conductive layer further includes a third extension extending from the second extension at a second angle. 13. The semiconductor memory element as described in item 12 of the patent application scope, in which both the first extension and the third extension extend substantially in a horizontal direction and the first extension extends substantially in a vertical direction. 14. The semiconductor memory device described in item 1 of the scope of patent application 'wherein the storage capacitor includes two substantially parallel dendritic conductive layers', one end of each dendritic conductive layer is connected to the trunk The patent application covers the outer surface of the conductive layer. 15. The semiconductor memory element as described in item 14 of the scope of the patent application wherein the free ends of the second extensions of the two dendritic conductive layers are not on the same plane. 16. The semiconductor memory device as recited in item 11 of the patent application range, wherein the storage capacitor further includes a second conductive layer having an end connected to the outer surface of the trunk-like conductive layer, and an outward extension 'Extend outward from the end in a substantially horizontal direction. Item Write this page 17. The semiconductor memory cell as described in item 16 of the patent application scope, wherein the second conductive layer is located below the dendritic conductive layer. Item 18. The semiconductor memory element as described in item u of the scope of the patent application wherein the trunk-like conductive layer includes a trunk portion electrically coupled to one of the drain and source regions of the transfer transistor, And has a τ-shaped cross-section; and an upper trunk extends from the upper surface of the lower trunk. 19. The semiconductor memory device as described in item 18 of the patent application range, wherein the end of the dendritic conductive layer is connected to the outer surface of the upper trunk portion. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 20. The semiconductor memory element as described in item 18 of the patent application scope, in which the upper trunk has a U-shaped profile. 21. The semiconductor memory element as described in item η of the scope of the patent application, in which the trunk-like conductive layer has a U-shaped cross-section. 22. A semiconductor memory device with a capacitor includes: a substrate; the transfer transistor is 'formed on the substrate' and includes the drain and the source 30. The paper standard is applicable to China ’s Standard A (CNS) A4 specification (employed 297 Gongmeng) · patent application area; and-a storage capacitor 'is electrically coupled to one of the areas of the transfer transistor, the storage capacitor includes a trunk-like conductive layer having a bottom, electrically coupled to the Above the drain and source regions of the transfer transistor, the trunk-like conductive layer has a columnar extension extending from the bottom in a generally upward direction, at least a dendritic conductive layer, having One end is connected to the outer surface of the trunk-like f-type skin, and the dendritic conductive layer has an outward extending portion, which extends outward from the end. The trunk-like conductive layer and the dendritic-like conductive layer constitute A storage electrode of the storage capacitor, a dielectric layer is formed on the exposed surface of the trunk-like conductive layer and dendritic conductive layer, and an upper conductive layer is formed on the dielectric layer to An opposite electrode constituting the storage capacitor. 23. The semiconductor memory element as described in item 22 of the scope of the patent application, wherein the cylindrical extension of the trunk-like conductive layer includes a hollow portion. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 24. The semiconductor memory device as described in item 22 of the patent scope, wherein the outwardly extending portion of the dendritic conductive layer has a section with a multi-bend shape ^ 25. The semiconductor memory device as described in item 22 of the scope of the patent application 'where the storage capacitor includes a plurality of dendritic conductive layers extending substantially in parallel'. One end of each dendritic conductive layer is connected to the category 3 1 This paper ruler / tiW ss Zhuzhun (CNS) Ege ⑽Χ297 public and private 8 8 8 8 ABCD Ministry of Economic Affairs Central Standards Bureau employee consumer cooperative printed on the outer surface of the trunk-like conductive layer of the patent scope. 32 (Please read the precautions on the back before filling out this page) Binding This paper size is applicable to China National Standard (CNS) A4 (210X297mm)