293175 A7 丨 B7 五、_明説明（/ ) 經濟部中央標準局貝工消費合作杜印製 發明背景 本發明是一製造流程，用以製造動態隨機存取記憶體（以下簡稱 DRAM )的細胞元（以下簡稱cell )的電容器。此電容器具有鶴狀特徵。 爲了增加單位面積之DRAM cell容量，cell的面積便愈來愈小，但 因電容器（每一cel丨由一電晶體串聯一電荷儲存電容器構成）的儲存電荷 量與其面積成正比，故降低cell面積的同時，便降低了電容量。當電容量 低於某一値，此記憶體元件便無法正常操作。因此，如何在有限平面面 積堆疊出足夠電容器總面積，便爲一重要技術課題此種堆疊電容器（stack type capacitor )有許多已發明之型態。其中較引人注目之一是鰭狀結構 (Fin structure )，如美國專利號碼5,290,726及5,128,273所記錄，此種 結構可使有效電容面積大爲增加，因此同時滿足了小的cell面積及大的儲 存電荷量兩基本需求。 · 但在前述專利中之製造方法皆需三道光罩步驟來完成緒狀電容器，眾 所週知，光罩數越多製造流程成本及時間皆越高，因此本發明便僅二 裏步驟完成鰭狀電容器。此電容器含一埋層複晶矽連到MOSFET之電晶 體之一擴散區，二複晶矽下電極，電容介電物質覆於下電極之上及一複晶 矽上電極。在製程中，一氮化矽及犧牲氧化層被利用來構築自我對準 (self-align )複晶埋層。僅需將沉積後的複晶矽直接回蝕刻（etch-back ) 即可構成鰭狀下電極。本發明之特點有： (1 )利用氮化矽抗氧化之特性製造self-aligned複晶矽節點接觸（node contact ) 〇 (2 )利用複晶矽蝕刻對氧化層的高選擇比（high selectivity of etch rate ) 來做etch back，可定義出下極圖案" (3 )以熱磷酸除去部份氮化矽可露出埋層複晶（節點）接觸區。圖式說明： (讀先聞讀背面之注意事項再填寫本頁) 訂 本紙争尺度適用中國國家榡率（CNS > A4規格（210X297公釐） 293175 H3 經濟部中央標準局貝工福利委含印製 圖la-lg表示了美國專利號碼5,128,273之製造流程。 圖2a-2h表示了美國專利號碼5,290,726之製造流程。 圖3a-3g表示了此發明之製造流程。 發明內容說明 首先簡述鰭狀結構，其剖面圖如圖la所示。P type晶片1中選擇 性地摻入n type雜質而成電晶體的源極及汲極。其閘極3位於兩極之間 而構成了此DRAM cell的控制開關。 —場氧化區2分離了兩電晶體元件。電晶體兩極之一被連接到位元 線14，而另一極則連到電容器的下電極9,7。除上述兩極之接觸區外， 晶片覆以一層絕緣層5。下電極之形狀則像似鰭狀（fm )因此，增加了 電容器之面積。上電極11，下電極9,7與其間介電物質共組成此DRAM cell之電容器。關於此鰭狀結構已有二種製造流程被提出：圖la-la ( US patent 5,128,273 )及圖 2a-2h ( US patent 5,290,726 )茲簡述如下。 如圖la，晶片1上以場氧化區2將之分爲元件區及隔離場氧化區 (isolation field oxide area )。閘氧化層 3a，複晶砂 poly-silicon 3 及帽蓋 (cap )氧化層3b依序沉積於晶片1以上。以光學照像顯影（photo lithography )法及乾式蝕刻（dry etch )方式（即一道光罩製程）製作出 控制電晶體的源極及汲極4。參考圖lb沉積氮化矽層（Si3N4 ) 5，此層 在未來將作爲蝕刻阻止（etch stop )層之用。如圖lc，氧化層6,複晶層7 及另一氧化層8依序沉積於氮化砂層5之上。以一道光罩製程挖出儲存節 點（storage node )接觸窗。參考圖Id，複晶矽9沉積於晶片上，因此， 將與節點接觸窗中之複晶矽7及晶片露出區（即電晶體之一極）連接。參 考圖le，再以第二道光罩製程形成下電極區。在触刻時由於是複晶矽9.7， 氧化層8,6交互錯置，因此，須來回更換蝕刻機。由於有攀化矽5做爲蝕 刻阻止層，因此不會破壞其下之電晶體結構。 如圖If，以溼蝕刻（wet etch )方式除去氧化層6,8及氮化矽層5， 之後即沉積電容介電物質薄膜10 (圖1g中之粗線所示）。圖lg中，複 晶矽11沉積後再以一道光罩製程形成上電極圖案，如此便完了此DRAM cell之電容器及電晶體部份。此製程在電容器部份共用了三道光罩製程， 另一 US patent 5,290,726之製作流程如圖2a-2h所示，其亦用了三道光罩 製程來製作DRAM cell之電容器，分別於圖2d，2f，2h中，詳細製程由附件 圖中可容易了解，在此不再詳述。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）h ί ::… ^ H3 經濟部中央梂準局員工福利委貝會印製 以下就本次發明之製程做一介紹（圖3a-3g ) 圖3a :形成元件隔離區及電晶體。 圖3b :依序沉積一薄複晶矽6，氮化矽13及犧牲氧化層（SAC oxide ) 14於晶片上。因此，複晶矽6直接跟電晶體之兩極接觸，形成了埋 層接觸（buried contact )。以一道光罩15定出下電極區域（即電 容器區域）。 圖3c : SAC oxide I4触刻後即將光阻去除。以熱磷酸液（Η3Ρ04 )浸泡 晶片以蝕去部份Si3N4 13 »因此，SAC oxide 14將有如一屋灌般 凸出於Si3N413之上。 圖3d :晶片隨後置入氧化爐管中氧化之。複晶矽6露出之部份將被氧化成 氧化矽，而在氮化矽13下之部份則因Si3N4具有抗氧入侵之特性， 因此不會被轉化成氧化矽。另複晶矽之氧化速率約爲矽晶的三倍’ 因此，熱處理時間將大爲減少，而其所轉換出的氧化層厚度約爲原 複晶矽厚度的二倍。 氮化矽13再進一步於磷酸槽中除去一部份，使其下的複晶矽露出。 此露出的部份18將作爲電容器下電極複晶矽與埋層複晶矽6接觸之 用。 圖3e :複晶矽17沉積於晶片上，與埋層複晶矽6接觸於節點（node contact ) 18。此種接觸方式具自我對準特性（self-aligned )»以 回蝕刻（etch back )將複晶矽17曝露出的部份去除，因此僅會留 下在SAC 9xide 14屋簷下的複矽晶Π。此乃因氧化層對複晶矽蝕刻 氣體具很強的抗蝕刻性及乾式電漿回蝕刻具有之單向性蝕刻 (anisotropic etching )特性。 圖3f :以HF液或BOE或乾式電漿蝕刻方式，將SAC oxide 14去除乾淨， 以Ρ3Η04液將氮化矽13去除。可以以離子植入方式將雜質離子如磷 或砷等植入複晶矽6，17中。如此便完成此DRAM cell電容器之下 電極部份- 圖3g :沉積一層介電材料薄膜（以粗線表示）19和上電極複晶矽20。此 介電層可以是ONO ( oxide-nitride-oxide )複合結構或其他高介電 係數材料。以一道光罩步驟將晶片上不需要上電極覆蓋的區域的複 晶矽20如此整個電容器便告完成》 下表比較此發明之電容器與前述二發明在製程步驟上的差異。從此表可看 出，本發明節省了一道光罩步驟。 本紙张尺度適用中國國家碎準（CNS ) A4規格（210X297公釐） 細 17S4 H3 美國專利 5,128,273 美國專利 5,290,726 本發明 進爐管製程次數 5 4 5 乾電漿蝕刻次數 7 2 2 濕蝕刻次數 1 4 4 以上總和 13 10 11 光罩歩驟次數 3 3 2 本發明具有下列優點 1·經由 self-aligned buried node contact 技術節省了一道光罩。 2. 由於下電極複晶砂與node contact是self-alignment因此元件面積可縮小。 因毋需考慮相關之design rule. 3. 由於無node contact蝕刻，故控制電晶體之閘極（word line )與下電極間之絕緣無問題。 4. 電容量因此鰭狀結構而增加。 此方法亦可同樣適用於n-type雜質上。 經濟部中央標準局貝工福利委員會印製 本纸張尺度適用中國國家梂準（CNS ) A4規格（210X297公釐）293175 A7 丨 B7 V. _Ming explanation (/) Bei Printing Consumption Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs Du Printed Background of the Invention The present invention is a manufacturing process for manufacturing cells of dynamic random access memory (hereinafter referred to as DRAM) (Hereinafter referred to as cell) capacitor. This capacitor has a crane-like characteristic. In order to increase the capacity of the DRAM cell per unit area, the area of the cell is getting smaller and smaller, but because the storage charge of the capacitor (each cel is composed of a transistor in series with a charge storage capacitor) is proportional to its area, the cell area is reduced At the same time, the capacity is reduced. When the capacitance is lower than a certain value, the memory device cannot operate normally. Therefore, how to stack enough total area of capacitors in a limited plane area is an important technical issue. There are many invented types of such stack type capacitors. One of the more striking is the fin structure (Fin structure), as recorded in US Patent Nos. 5,290,726 and 5,128,273, this structure can greatly increase the effective capacitance area, thus satisfying both small cell area and large storage Two basic requirements for the amount of charge. · However, the manufacturing methods in the aforementioned patents require three photomask steps to complete the threaded capacitor. It is well known that the greater the number of photomasks, the higher the manufacturing process cost and time. Therefore, the present invention only completes the fin capacitor in two steps. This capacitor contains a buried layer of polycrystalline silicon connected to one of the diffusion regions of the electrical crystal of the MOSFET, two polycrystalline silicon lower electrodes, a capacitor dielectric material overlying the lower electrode, and a polycrystalline silicon upper electrode. In the process, silicon nitride and sacrificial oxide layers are used to build a self-aligned polycrystalline buried layer. It is only necessary to etch-back the deposited polycrystalline silicon directly to form the fin-shaped lower electrode. The features of the present invention are: (1) The self-aligned polycrystalline silicon node contact is manufactured using the anti-oxidation characteristics of silicon nitride. (2) The high selectivity of the oxide layer using polycrystalline silicon etching to the oxide layer (high selectivity of etch rate) to do etch back, the lower electrode pattern can be defined " (3) removing part of silicon nitride with hot phosphoric acid can expose the buried polycrystalline (node) contact area. Graphic description: (Read the precautions on the back and then fill out this page) The standard of the paper is applicable to the national rate of China (CNS & A4 specifications (210X297 mm) 293175 H3 Beigong Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs The printed drawing la-lg shows the manufacturing process of US Patent No. 5,128,273. Figures 2a-2h show the manufacturing process of US Patent No. 5,290,726. Figures 3a-3g show the manufacturing process of this invention. Brief description of the invention The cross-sectional view of the structure is shown in Figure la. P-type wafer 1 is selectively doped with n-type impurities to form the source and drain of the transistor. The gate 3 is located between the two poles to constitute the DRAM cell. Control the switch.-The field oxide zone 2 separates the two transistor elements. One of the two poles of the transistor is connected to the bit line 14, and the other pole is connected to the lower electrode 9, 7 of the capacitor. In addition to the contact area of the above two poles, The chip is covered with an insulating layer 5. The shape of the lower electrode looks like a fin (fm). Therefore, the area of the capacitor is increased. The upper electrode 11, the lower electrodes 9, 7 and the dielectric material between them form a capacitor of this DRAM cell. About this fin knot Two manufacturing processes have been proposed: Figure la-la (US patent 5,128,273) and Figure 2a-2h (US patent 5,290,726) are briefly described as follows. As shown in Figure la, the wafer 1 is divided into components by field oxide regions 2 Area and isolation field oxide area. Gate oxide layer 3a, poly-silicon 3 and cap oxide layer 3b are deposited on the wafer 1 in sequence. Photo lithography ) Method and dry etch (a photomask process) to produce the source and drain of the control transistor 4. Refer to Figure 1b to deposit a silicon nitride layer (Si3N4) 5. This layer will be used as an etch in the future The use of etch stop layer. As shown in Figure lc, oxide layer 6, polycrystalline layer 7 and another oxide layer 8 are deposited on the nitrided sand layer 5 in sequence. The storage node is dug out with a photomask process ) Contact window. Referring to FIG. Id, polycrystalline silicon 9 is deposited on the wafer, so it will be connected to the polycrystalline silicon 7 in the node contact window and the exposed area of the wafer (ie, one pole of the transistor). Refer to FIG. Le, and then The second photomask process forms the lower electrode area. Because it is polycrystalline silicon 9.7 The oxide layers 8 and 6 are staggered, so the etching machine must be replaced back and forth. Since Panhua Silicon 5 is used as an etching stop layer, it will not damage the transistor structure underneath. As shown in If, wet etch (wet etch) ) Method to remove the oxide layers 6, 8 and the silicon nitride layer 5, after which the capacitor dielectric material film 10 is deposited (shown by the thick line in FIG. 1g). In FIG. 1g, the polysilicon 11 is deposited and then the upper electrode pattern is formed by a photomask process, thus completing the capacitor and transistor parts of the DRAM cell. This process shares three mask processes in the capacitor part. Another US patent 5,290,726 is shown in Figures 2a-2h. It also uses three mask processes to make DRAM cell capacitors, as shown in Figures 2d and 2f. In 2h, the detailed process can be easily understood from the attached drawings, and will not be described in detail here. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) h ί ::… ^ H3 Printed by the Employee Welfare Committee of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs The following is an introduction to the process of this invention (Figure 3a -3g) Figure 3a: Formation of element isolation regions and transistors. Figure 3b: A thin polycrystalline silicon 6, a silicon nitride 13 and a sacrificial oxide layer (SAC oxide) 14 are sequentially deposited on the wafer. Therefore, the polycrystalline silicon 6 directly contacts the two poles of the transistor to form a buried contact. The lower electrode area (i.e. the capacitor area) is defined by a mask 15. Figure 3c: The photoresist will be removed after the SAC oxide I4 is touched. Soak the wafer with hot phosphoric acid solution (Η3Ρ04) to etch away part of Si3N4 13 »Therefore, SAC oxide 14 will protrude above Si3N413 like a house. Figure 3d: The wafer is then placed in an oxidation furnace tube and oxidized. The exposed part of the polycrystalline silicon 6 will be oxidized to silicon oxide, and the part under the silicon nitride 13 will not be converted to silicon oxide because Si3N4 has the property of resisting oxygen invasion. In addition, the oxidation rate of polycrystalline silicon is about three times that of silicon crystals. Therefore, the heat treatment time will be greatly reduced, and the thickness of the converted oxide layer is about twice the thickness of the original polycrystalline silicon. The silicon nitride 13 is further removed in the phosphoric acid tank to expose the polycrystalline silicon underneath. This exposed portion 18 will serve as a contact between the polycrystalline silicon of the capacitor lower electrode and the polycrystalline silicon 6 of the buried layer. Figure 3e: Polycrystalline silicon 17 is deposited on the wafer, and is in contact with the buried polycrystalline silicon 6 at a node contact 18. This contact method is self-aligned »etched back to remove the exposed part of polycrystalline silicon 17, so only the polycrystalline silicon under the eaves of SAC 9xide 14 will remain . This is because the oxide layer has strong etching resistance to polycrystalline silicon etching gas and the anisotropic etching characteristic of dry plasma etch back. Figure 3f: SAC oxide 14 is removed by HF liquid or BOE or dry plasma etching, and silicon nitride 13 is removed by Ρ3Η04 liquid. Impurity ions such as phosphorus or arsenic can be implanted into polycrystalline silicon 6, 17 by ion implantation. This completes the lower electrode portion of the DRAM cell capacitor-Figure 3g: a layer of dielectric material film (represented by thick lines) 19 and the upper electrode polysilicon 20 are deposited. The dielectric layer may be an ONO (oxide-nitride-oxide) composite structure or other high dielectric constant materials. In a photomask step, the polysilicon 20 on the area that does not need to be covered by the upper electrode on the wafer is completed. The entire capacitor is completed. As can be seen from this table, the present invention saves a mask step. This paper scale is applicable to China National Crushing Standard (CNS) A4 specification (210X297mm). Fine 17S4 H3 US Patent 5,128,273 US Patent 5,290,726 The number of control procedures of the invention into the furnace 5 4 5 Dry plasma etching times 7 2 2 Wet etching times 1 4 4 The sum of the above 13 10 11 The number of steps of the photomask 3 3 2 The present invention has the following advantages 1. A photomask is saved through the self-aligned buried node contact technology. 2. Since the lower electrode polycrystalline sand and node contact are self-aligned, the device area can be reduced. There is no need to consider the related design rule. 3. Since there is no node contact etching, there is no problem in the insulation between the word line of the control transistor and the lower electrode. 4. The capacitance increases due to the fin structure. This method can also be applied to n-type impurities. Printed by the Beigong Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs. The paper size is applicable to China National Standards (CNS) A4 (210X297 mm)