DE3888632D1 - Schichtstruktur für eine Speicherzelle für eine dynamische Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür. - Google Patents

Schichtstruktur für eine Speicherzelle für eine dynamische Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür.

Info

Publication number
DE3888632D1
DE3888632D1 DE88310650T DE3888632T DE3888632D1 DE 3888632 D1 DE3888632 D1 DE 3888632D1 DE 88310650 T DE88310650 T DE 88310650T DE 3888632 T DE3888632 T DE 3888632T DE 3888632 D1 DE3888632 D1 DE 3888632D1
Authority
DE
Germany
Prior art keywords
manufacturing
random access
layer structure
dynamic random
method therefor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE88310650T
Other languages
English (en)
Inventor
Taiji Ema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3888632D1 publication Critical patent/DE3888632D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE88310650T 1987-11-17 1988-11-11 Schichtstruktur für eine Speicherzelle für eine dynamische Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür. Expired - Lifetime DE3888632D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62288510A JPH0666437B2 (ja) 1987-11-17 1987-11-17 半導体記憶装置及びその製造方法

Publications (1)

Publication Number Publication Date
DE3888632D1 true DE3888632D1 (de) 1994-04-28

Family

ID=17731162

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88310650T Expired - Lifetime DE3888632D1 (de) 1987-11-17 1988-11-11 Schichtstruktur für eine Speicherzelle für eine dynamische Speicheranordnung mit wahlfreiem Zugriff und Herstellungsverfahren dafür.

Country Status (5)

Country Link
US (2) US4910566A (de)
EP (1) EP0317199B1 (de)
JP (1) JPH0666437B2 (de)
KR (1) KR910009788B1 (de)
DE (1) DE3888632D1 (de)

Families Citing this family (62)

* Cited by examiner, † Cited by third party
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DE3856143T2 (de) * 1987-06-17 1998-10-29 Fujitsu Ltd Verfahren zum Herstellen einer dynamischen Speicherzelle mit wahlfreiem Zugriff
US5650647A (en) * 1987-06-17 1997-07-22 Fujitsu Limited Dynamic random access memory device and method of producing same
US5734188A (en) * 1987-09-19 1998-03-31 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5264712A (en) * 1989-03-20 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
JP2588732B2 (ja) * 1987-11-14 1997-03-12 富士通株式会社 半導体記憶装置
US5374576A (en) * 1988-12-21 1994-12-20 Hitachi, Ltd. Method of fabricating stacked capacitor cell memory devices
US20010008288A1 (en) * 1988-01-08 2001-07-19 Hitachi, Ltd. Semiconductor integrated circuit device having memory cells
US5140389A (en) * 1988-01-08 1992-08-18 Hitachi, Ltd. Semiconductor memory device having stacked capacitor cells
JPH01290255A (ja) * 1988-05-18 1989-11-22 Toshiba Corp 半導体記憶装置およびその製造方法
KR900019227A (ko) * 1988-05-18 1990-12-24 아오이 죠이치 적층형 캐피시터를 갖춘 반도체기억장치 및 그 제조방법
KR910010167B1 (ko) * 1988-06-07 1991-12-17 삼성전자 주식회사 스택 캐패시터 dram셀 및 그의 제조방법
JP2838412B2 (ja) * 1988-06-10 1998-12-16 三菱電機株式会社 半導体記憶装置のキャパシタおよびその製造方法
US5180683A (en) * 1988-06-10 1993-01-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing stacked capacitor type semiconductor memory device
DE3918924C2 (de) * 1988-06-10 1996-03-21 Mitsubishi Electric Corp Herstellungsverfahren für eine Halbleiterspeichereinrichtung
DE3943617C2 (de) * 1988-06-10 1996-03-14 Mitsubishi Electric Corp DRAM und Herstellungsverfahren dafür
US5091761A (en) * 1988-08-22 1992-02-25 Hitachi, Ltd. Semiconductor device having an arrangement of IGFETs and capacitors stacked thereover
US5917211A (en) * 1988-09-19 1999-06-29 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
JP2731197B2 (ja) * 1988-11-28 1998-03-25 株式会社東芝 半導体記憶装置およびその製造方法
US5227649A (en) * 1989-02-27 1993-07-13 Texas Instruments Incorporated Circuit layout and method for VLSI circuits having local interconnects
JP2859288B2 (ja) * 1989-03-20 1999-02-17 株式会社日立製作所 半導体集積回路装置及びその製造方法
US5059548A (en) * 1989-04-03 1991-10-22 Hyundai Electronics Industries Co., Ltd. Method of making a semiconductor memory device having a double stacked capacitor
US5162249A (en) * 1989-04-03 1992-11-10 Hyundai Electronics Industries Co., Ltd. Method of making semiconductor memory device having a double stacked capacitor
US5175121A (en) * 1989-05-10 1992-12-29 Samsung Electronics Co., Ltd. Method for manufacturing a stacked capacitor DRAM semiconductor device
KR940005729B1 (ko) * 1989-06-13 1994-06-23 삼성전자 주식회사 디램셀의 제조방법 및 구조
JP2724209B2 (ja) * 1989-06-20 1998-03-09 シャープ株式会社 半導体メモリ素子の製造方法
US5314835A (en) * 1989-06-20 1994-05-24 Sharp Kabushiki Kaisha Semiconductor memory device
JP2503661B2 (ja) * 1989-06-28 1996-06-05 日本電気株式会社 半導体メモリ素子およびその製造方法
KR910013554A (ko) * 1989-12-08 1991-08-08 김광호 반도체 장치 및 그 제조방법
KR950000500B1 (ko) * 1989-08-31 1995-01-24 금성일렉트론 주식회사 디램셀 커패시터 제조방법 및 구조
KR920010204B1 (ko) * 1989-12-02 1992-11-21 삼성전자 주식회사 초고집적 디램셀 및 그 제조방법
KR930000581B1 (ko) * 1990-04-04 1993-01-25 금성일렉트론 주식회사 자기 정렬된 캐패시터 콘택을 갖는 셀 제조방법 및 구조
US5240872A (en) * 1990-05-02 1993-08-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions
JP2524863B2 (ja) * 1990-05-02 1996-08-14 三菱電機株式会社 半導体装置およびその製造方法
US5114873A (en) * 1990-05-21 1992-05-19 Samsung Electronics Co., Ltd. Method for manufacturing a stacked capacitor DRAM cell
FR2663786A1 (fr) * 1990-06-21 1991-12-27 Samsung Electronics Co Ltd Procede de fabrication de condensateurs dans une cellule dram.
DE4122038C2 (de) * 1990-07-03 1994-08-25 Mitsubishi Electric Corp Herstellungsverfahren für einen DRAM
DE69118771T2 (de) * 1990-07-31 1996-10-31 Nec Corp Ladungsspeicherelektrode eines Kondensators und Methode zu deren Herstellung
JPH04109668A (ja) * 1990-08-29 1992-04-10 Nec Ic Microcomput Syst Ltd 半導体集積回路装置
US5196364A (en) * 1990-10-24 1993-03-23 Micron Technology, Inc. Method of making a stacked capacitor dram cell
US5266513A (en) * 1990-10-24 1993-11-30 Micron Technology, Inc. Method of making stacked W-cell capacitor
JP3344485B2 (ja) * 1990-11-09 2002-11-11 富士通株式会社 半導体装置の製造方法
JP3079637B2 (ja) * 1991-04-30 2000-08-21 ソニー株式会社 半導体メモリの製造方法
JP2802455B2 (ja) * 1991-05-10 1998-09-24 三菱電機株式会社 半導体装置およびその製造方法
US5223448A (en) * 1991-07-18 1993-06-29 Industrial Technology Research Institute Method for producing a layered capacitor structure for a dynamic random access memory device
JP3055242B2 (ja) * 1991-09-19 2000-06-26 日本電気株式会社 半導体装置およびその製造方法
US5149668A (en) * 1991-11-19 1992-09-22 Micron Technology, Inc. Method of preventing storage node to storage node shorts in fabrication of memory integrated circuitry having stacked capacitors and stacked capacitor memory integrated circuits
US5134085A (en) * 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US5126916A (en) * 1991-12-20 1992-06-30 Industrial Technology Research Institute Stacked capacitor dram cell and method of fabricating
US5192702A (en) * 1991-12-23 1993-03-09 Industrial Technology Research Institute Self-aligned cylindrical stacked capacitor DRAM cell
JPH0677428A (ja) * 1992-08-25 1994-03-18 Nec Corp 半導体記憶装置及びその製造方法
US5330928A (en) * 1992-09-28 1994-07-19 Industrial Technology Research Institute Method for fabricating stacked capacitors with increased capacitance in a DRAM cell
US5374577A (en) * 1992-12-21 1994-12-20 Industrial Technology Research Institute Polysilicon undercut process for stack DRAM
KR960011652B1 (ko) * 1993-04-14 1996-08-24 현대전자산업 주식회사 스택캐패시터 및 그 제조방법
US5468669A (en) * 1993-10-29 1995-11-21 At&T Corp. Integrated circuit fabrication
US5380675A (en) * 1994-03-21 1995-01-10 United Microelectronics Corporation Method for making closely spaced stacked capacitors on DRAM chips
JPH08236683A (ja) * 1995-02-28 1996-09-13 Nec Corp リードフレーム
KR0144902B1 (ko) * 1995-04-17 1998-07-01 김광호 불휘발성 메모리장치 및 그 제조방법
TW377464B (en) * 1996-04-15 1999-12-21 Promos Technologies Inc Method of increasing the surface area of capacitor construct
US5821573A (en) * 1996-10-17 1998-10-13 Mitsubishi Semiconductor America, Inc. Field effect transistor having an arched gate and manufacturing method thereof
US6104055A (en) * 1997-03-27 2000-08-15 Nec Corporation Semiconductor device with memory cell having a storage capacitor with a plurality of concentric storage electrodes formed in an insulating layer and fabrication method thereof
US6204115B1 (en) * 1999-06-03 2001-03-20 Stanford University Manufacture of high-density pillar memory cell arrangement
US6429123B1 (en) * 2000-10-04 2002-08-06 Vanguard International Semiconductor Corporation Method of manufacturing buried metal lines having ultra fine features

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5623771A (en) * 1979-08-01 1981-03-06 Hitachi Ltd Semiconductor memory
US4649406A (en) * 1982-12-20 1987-03-10 Fujitsu Limited Semiconductor memory device having stacked capacitor-type memory cells
JPS59231851A (ja) * 1983-06-14 1984-12-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリセル
JPS61144862A (ja) * 1984-12-19 1986-07-02 Hitachi Ltd 半導体記憶装置
JPH0682783B2 (ja) * 1985-03-29 1994-10-19 三菱電機株式会社 容量およびその製造方法
JPS6248062A (ja) * 1985-08-28 1987-03-02 Sony Corp メモリセル
JPH0736437B2 (ja) * 1985-11-29 1995-04-19 株式会社日立製作所 半導体メモリの製造方法
US4812885A (en) * 1987-08-04 1989-03-14 Texas Instruments Incorporated Capacitive coupling
KR900019227A (ko) * 1988-05-18 1990-12-24 아오이 죠이치 적층형 캐피시터를 갖춘 반도체기억장치 및 그 제조방법
KR910010167B1 (ko) * 1988-06-07 1991-12-17 삼성전자 주식회사 스택 캐패시터 dram셀 및 그의 제조방법

Also Published As

Publication number Publication date
KR910009788B1 (ko) 1991-11-30
JPH0666437B2 (ja) 1994-08-24
US4977102A (en) 1990-12-11
JPH01130556A (ja) 1989-05-23
US4910566A (en) 1990-03-20
EP0317199A2 (de) 1989-05-24
KR890008987A (ko) 1989-07-13
EP0317199B1 (de) 1994-03-23
EP0317199A3 (en) 1990-09-05

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Legal Events

Date Code Title Description
8332 No legal effect for de