DE3856143T2 - Verfahren zum Herstellen einer dynamischen Speicherzelle mit wahlfreiem Zugriff - Google Patents

Verfahren zum Herstellen einer dynamischen Speicherzelle mit wahlfreiem Zugriff

Info

Publication number
DE3856143T2
DE3856143T2 DE3856143T DE3856143T DE3856143T2 DE 3856143 T2 DE3856143 T2 DE 3856143T2 DE 3856143 T DE3856143 T DE 3856143T DE 3856143 T DE3856143 T DE 3856143T DE 3856143 T2 DE3856143 T2 DE 3856143T2
Authority
DE
Germany
Prior art keywords
making
memory cell
random access
access memory
dynamic random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3856143T
Other languages
English (en)
Other versions
DE3856143D1 (de
Inventor
Maso Taguchi
Taiji Ema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62149143A external-priority patent/JPH073860B2/ja
Priority claimed from JP62306416A external-priority patent/JP2642364B2/ja
Priority claimed from JP62314764A external-priority patent/JP2627515B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3856143D1 publication Critical patent/DE3856143D1/de
Publication of DE3856143T2 publication Critical patent/DE3856143T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
DE3856143T 1987-06-17 1988-06-16 Verfahren zum Herstellen einer dynamischen Speicherzelle mit wahlfreiem Zugriff Expired - Lifetime DE3856143T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62149143A JPH073860B2 (ja) 1987-06-17 1987-06-17 半導体記憶装置の製造方法
JP62306416A JP2642364B2 (ja) 1987-12-03 1987-12-03 半導体記憶装置及びその製造方法
JP62314764A JP2627515B2 (ja) 1987-12-10 1987-12-10 半導体記憶装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE3856143D1 DE3856143D1 (de) 1998-04-16
DE3856143T2 true DE3856143T2 (de) 1998-10-29

Family

ID=27319692

Family Applications (2)

Application Number Title Priority Date Filing Date
DE3856528T Expired - Lifetime DE3856528T2 (de) 1987-06-17 1988-06-16 Dynamisches Speicherbauteil mit wahlfreiem Zugriff und Verfahren zu seiner Herstellung
DE3856143T Expired - Lifetime DE3856143T2 (de) 1987-06-17 1988-06-16 Verfahren zum Herstellen einer dynamischen Speicherzelle mit wahlfreiem Zugriff

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE3856528T Expired - Lifetime DE3856528T2 (de) 1987-06-17 1988-06-16 Dynamisches Speicherbauteil mit wahlfreiem Zugriff und Verfahren zu seiner Herstellung

Country Status (4)

Country Link
US (2) US4974040A (de)
EP (2) EP0295709B1 (de)
KR (1) KR910002815B1 (de)
DE (2) DE3856528T2 (de)

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Also Published As

Publication number Publication date
DE3856528D1 (de) 2002-06-13
EP0750347B1 (de) 2002-05-08
EP0295709A2 (de) 1988-12-21
KR910002815B1 (ko) 1991-05-04
US5021357A (en) 1991-06-04
EP0295709B1 (de) 1998-03-11
KR890001189A (ko) 1989-03-18
DE3856528T2 (de) 2002-12-05
EP0750347A1 (de) 1996-12-27
US4974040A (en) 1990-11-27
EP0295709A3 (de) 1990-12-05
DE3856143D1 (de) 1998-04-16

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