DE69131638D1 - Verfahren zum Herstellen einer Halbleiterspeicheranordnung mit erhöhter Speicherzellenkapazität - Google Patents

Verfahren zum Herstellen einer Halbleiterspeicheranordnung mit erhöhter Speicherzellenkapazität

Info

Publication number
DE69131638D1
DE69131638D1 DE69131638T DE69131638T DE69131638D1 DE 69131638 D1 DE69131638 D1 DE 69131638D1 DE 69131638 T DE69131638 T DE 69131638T DE 69131638 T DE69131638 T DE 69131638T DE 69131638 D1 DE69131638 D1 DE 69131638D1
Authority
DE
Germany
Prior art keywords
producing
cell capacity
memory cell
semiconductor memory
increased
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131638T
Other languages
English (en)
Other versions
DE69131638T2 (de
Inventor
Taiji Ema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69131638D1 publication Critical patent/DE69131638D1/de
Publication of DE69131638T2 publication Critical patent/DE69131638T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
DE69131638T 1990-07-09 1991-07-08 Verfahren zum Herstellen einer Halbleiterspeicheranordnung mit erhöhter Speicherzellenkapazität Expired - Fee Related DE69131638T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2181896A JPH0468566A (ja) 1990-07-09 1990-07-09 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE69131638D1 true DE69131638D1 (de) 1999-10-28
DE69131638T2 DE69131638T2 (de) 2000-01-05

Family

ID=16108782

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131638T Expired - Fee Related DE69131638T2 (de) 1990-07-09 1991-07-08 Verfahren zum Herstellen einer Halbleiterspeicheranordnung mit erhöhter Speicherzellenkapazität

Country Status (5)

Country Link
US (1) US5554556A (de)
EP (1) EP0466426B1 (de)
JP (1) JPH0468566A (de)
KR (1) KR950009895B1 (de)
DE (1) DE69131638T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2976842B2 (ja) * 1995-04-20 1999-11-10 日本電気株式会社 半導体記憶装置の製造方法
EP0788164A1 (de) * 1996-02-02 1997-08-06 United Memories, Inc. Speicherzellenanordnung für erhöhte Kondensatoroberfläche
US5930618A (en) * 1997-08-04 1999-07-27 United Microelectronics Corp. Method of Making High-K Dielectrics for embedded DRAMS
KR100434506B1 (ko) * 2002-06-27 2004-06-05 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
KR100480602B1 (ko) * 2002-06-28 2005-04-06 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
US6914286B2 (en) 2002-06-27 2005-07-05 Samsung Electronics Co., Ltd. Semiconductor memory devices using sidewall spacers
US7118958B2 (en) * 2005-03-03 2006-10-10 Texas Instruments Incorporated Method of manufacturing a metal-insulator-metal capacitor using an etchback process

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124822A (ja) * 1983-12-09 1985-07-03 Fujitsu Ltd 縮小投影露光装置を用いたパタ−ン形成方法
JPS6235560A (ja) * 1985-08-08 1987-02-16 Nec Corp Ｍｉｓ型半導体記憶装置
DE3918924C2 (de) * 1988-06-10 1996-03-21 Mitsubishi Electric Corp Herstellungsverfahren für eine Halbleiterspeichereinrichtung
JP2703275B2 (ja) * 1988-08-22 1998-01-26 株式会社日立製作所 半導体記憶装置
JPH0276257A (ja) * 1988-09-12 1990-03-15 Sharp Corp 半導体メモリ素子
US4927772A (en) * 1989-05-30 1990-05-22 General Electric Company Method of making high breakdown voltage semiconductor device
JPH0320736A (ja) * 1989-06-16 1991-01-29 Matsushita Electron Corp フォトマスク
US5272103A (en) * 1991-02-08 1993-12-21 Mitsubishi Denki Kabushiki Kaisha DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof
KR0152901B1 (ko) * 1993-06-23 1998-10-01 문정환 플라스틱 반도체 패키지 및 그 제조방법

Also Published As

Publication number Publication date
KR950009895B1 (ko) 1995-09-01
DE69131638T2 (de) 2000-01-05
EP0466426B1 (de) 1999-09-22
US5554556A (en) 1996-09-10
EP0466426A2 (de) 1992-01-15
JPH0468566A (ja) 1992-03-04
EP0466426A3 (en) 1992-09-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee