DE3575813D1 - Verfahren zum herstellen einer halbleiteranordnung mit einer gateelektrodenstapel-struktur. - Google Patents
Verfahren zum herstellen einer halbleiteranordnung mit einer gateelektrodenstapel-struktur.Info
- Publication number
- DE3575813D1 DE3575813D1 DE8585105571T DE3575813T DE3575813D1 DE 3575813 D1 DE3575813 D1 DE 3575813D1 DE 8585105571 T DE8585105571 T DE 8585105571T DE 3575813 T DE3575813 T DE 3575813T DE 3575813 D1 DE3575813 D1 DE 3575813D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- gate electrode
- stack structure
- electrode stack
- semiconductor arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59090414A JPS60234372A (ja) | 1984-05-07 | 1984-05-07 | 半導体装置の製造方法 |
JP14533684A JPS6124283A (ja) | 1984-07-13 | 1984-07-13 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3575813D1 true DE3575813D1 (de) | 1990-03-08 |
Family
ID=26431898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585105571T Expired - Lifetime DE3575813D1 (de) | 1984-05-07 | 1985-05-07 | Verfahren zum herstellen einer halbleiteranordnung mit einer gateelektrodenstapel-struktur. |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP0160965B1 (de) |
DE (1) | DE3575813D1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4789883A (en) * | 1985-12-17 | 1988-12-06 | Advanced Micro Devices, Inc. | Integrated circuit structure having gate electrode and underlying oxide and method of making same |
EP0253014B1 (de) * | 1986-07-18 | 1990-04-11 | Nippondenso Co., Ltd. | Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeicheranordnung mit Möglichkeit zum Einschreiben und Löschen |
US4905062A (en) * | 1987-11-19 | 1990-02-27 | Texas Instruments Incorporated | Planar famos transistor with trench isolation |
FR2634318B1 (fr) * | 1988-07-13 | 1992-02-21 | Commissariat Energie Atomique | Procede de fabrication d'une cellule de memoire integree |
US5336628A (en) * | 1988-10-25 | 1994-08-09 | Commissariat A L'energie Atomique | Method for fabricating semiconductor memory device |
US4992391A (en) * | 1989-11-29 | 1991-02-12 | Advanced Micro Devices, Inc. | Process for fabricating a control gate for a floating gate FET |
JPH0637317A (ja) * | 1990-04-11 | 1994-02-10 | General Motors Corp <Gm> | 薄膜トランジスタおよびその製造方法 |
JPH088317B2 (ja) * | 1990-04-24 | 1996-01-29 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
US5310692A (en) * | 1992-05-29 | 1994-05-10 | Sgs-Thomson Microelectronics, Inc. | Method of forming a MOSFET structure with planar surface |
US6034410A (en) * | 1994-01-14 | 2000-03-07 | Stmicroelectronics, Inc. | MOSFET structure with planar surface |
FR2820751B1 (fr) | 2001-02-09 | 2005-01-14 | Bostik Findley | Adhesifs thermofusibles auto-adhesifs extrudables a chaud et leur utilisation dans les films multicouches |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4183134A (en) * | 1977-02-15 | 1980-01-15 | Westinghouse Electric Corp. | High yield processing for silicon-on-sapphire CMOS integrated circuits |
JPS53124084A (en) * | 1977-04-06 | 1978-10-30 | Hitachi Ltd | Semiconductor memory device containing floating type poly silicon layer and its manufacture |
US4258466A (en) * | 1978-11-02 | 1981-03-31 | Texas Instruments Incorporated | High density electrically programmable ROM |
JPS5713772A (en) * | 1980-06-30 | 1982-01-23 | Hitachi Ltd | Semiconductor device and manufacture thereof |
US4412310A (en) * | 1980-10-14 | 1983-10-25 | Intel Corporation | EPROM Cell with reduced programming voltage and method of fabrication |
-
1985
- 1985-05-07 EP EP85105571A patent/EP0160965B1/de not_active Expired - Lifetime
- 1985-05-07 DE DE8585105571T patent/DE3575813D1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0160965A3 (en) | 1987-09-09 |
EP0160965B1 (de) | 1990-01-31 |
EP0160965A2 (de) | 1985-11-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |