DE3884698D1 - Verfahren zum Herstellen einer Speicherzelle. - Google Patents

Verfahren zum Herstellen einer Speicherzelle.

Info

Publication number
DE3884698D1
DE3884698D1 DE88401777T DE3884698T DE3884698D1 DE 3884698 D1 DE3884698 D1 DE 3884698D1 DE 88401777 T DE88401777 T DE 88401777T DE 3884698 T DE3884698 T DE 3884698T DE 3884698 D1 DE3884698 D1 DE 3884698D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory cell
cell
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE88401777T
Other languages
English (en)
Other versions
DE3884698T2 (de
Inventor
Pierre Jeuch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE3884698D1 publication Critical patent/DE3884698D1/de
Publication of DE3884698T2 publication Critical patent/DE3884698T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE88401777T 1987-07-10 1988-07-07 Verfahren zum Herstellen einer Speicherzelle. Expired - Lifetime DE3884698T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8709844A FR2618011B1 (fr) 1987-07-10 1987-07-10 Procede de fabrication d'une cellule de memoire

Publications (2)

Publication Number Publication Date
DE3884698D1 true DE3884698D1 (de) 1993-11-11
DE3884698T2 DE3884698T2 (de) 1994-05-05

Family

ID=9353075

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88401777T Expired - Lifetime DE3884698T2 (de) 1987-07-10 1988-07-07 Verfahren zum Herstellen einer Speicherzelle.

Country Status (5)

Country Link
US (1) US4851365A (de)
EP (1) EP0299853B1 (de)
JP (1) JP2588486B2 (de)
DE (1) DE3884698T2 (de)
FR (1) FR2618011B1 (de)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3059442B2 (ja) 1988-11-09 2000-07-04 株式会社日立製作所 半導体記憶装置
US4980309A (en) * 1987-11-30 1990-12-25 Texas Instruments, Incorporated Method of making high density EEPROM
US5677867A (en) * 1991-06-12 1997-10-14 Hazani; Emanuel Memory with isolatable expandable bit lines
US5304505A (en) * 1989-03-22 1994-04-19 Emanuel Hazani Process for EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells
FR2634318B1 (fr) * 1988-07-13 1992-02-21 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire integree
FR2635410B1 (fr) * 1988-08-11 1991-08-02 Sgs Thomson Microelectronics Memoire de type eprom a haute densite d'integration avec une organisation en damier et un facteur de couplage ameliore et procede de fabrication
US4945067A (en) * 1988-09-16 1990-07-31 Xerox Corporation Intra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabrication
US5336628A (en) * 1988-10-25 1994-08-09 Commissariat A L'energie Atomique Method for fabricating semiconductor memory device
US5238855A (en) * 1988-11-10 1993-08-24 Texas Instruments Incorporated Cross-point contact-free array with a high-density floating-gate structure
US5200350A (en) * 1988-11-10 1993-04-06 Texas Instruments Incorporated Floating-gate memory array with silicided buried bitlines
JPH0783122B2 (ja) * 1988-12-01 1995-09-06 富士電機株式会社 半導体装置の製造方法
FR2642900B1 (fr) * 1989-01-17 1991-05-10 Sgs Thomson Microelectronics Procede de fabrication de circuits integres a transistors de memoire eprom et a transistors logiques
US5070032A (en) * 1989-03-15 1991-12-03 Sundisk Corporation Method of making dense flash eeprom semiconductor memory structures
US5149667A (en) * 1989-05-31 1992-09-22 Samsung Electronics Co., Ltd. Mask ROM device having double polycrystalline silicone and process for producing the same
JPH0783066B2 (ja) * 1989-08-11 1995-09-06 株式会社東芝 半導体装置の製造方法
FR2655194B1 (fr) * 1989-11-28 1992-04-10 Sgs Thomson Microelectronics Procede de fabrication de circuits integres constituant des memoires eprom.
US5215933A (en) * 1990-05-11 1993-06-01 Kabushiki Kaisha Toshiba Method of manufacturing nonvolatile semiconductor memory device
JP2672184B2 (ja) * 1990-08-27 1997-11-05 シャープ株式会社 半導体装置の製造方法
US5343063A (en) * 1990-12-18 1994-08-30 Sundisk Corporation Dense vertical programmable read only memory cell structure and processes for making them
US5202272A (en) * 1991-03-25 1993-04-13 International Business Machines Corporation Field effect transistor formed with deep-submicron gate
US5240870A (en) * 1991-04-18 1993-08-31 National Semiconductor Corporation Stacked gate process flow for cross-point EPROM with internal access transistor
FR2677481B1 (fr) * 1991-06-07 1993-08-20 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire non volatile et cellule de memoire obtenue.
US5120668A (en) * 1991-07-10 1992-06-09 Ibm Corporation Method of forming an inverse T-gate FET transistor
US5397726A (en) * 1992-02-04 1995-03-14 National Semiconductor Corporation Segment-erasable flash EPROM
US5379253A (en) * 1992-06-01 1995-01-03 National Semiconductor Corporation High density EEPROM cell array with novel programming scheme and method of manufacture
US5246874A (en) * 1992-06-02 1993-09-21 National Semiconductor Corporation Method of making fast access AMG EPROM
KR950011556B1 (ko) * 1992-07-03 1995-10-06 현대전자산업주식회사 반도체 접속장치 형성방법
US5376578A (en) * 1993-12-17 1994-12-27 International Business Machines Corporation Method of fabricating a semiconductor device with raised diffusions and isolation
KR970009617B1 (en) * 1993-12-31 1997-06-14 Hyundai Electronics Ind Contact forming method of semiconductor device
KR0129125B1 (ko) * 1994-01-21 1998-04-07 문정환 반도체 소자의 ldd mosfet 제조방법
WO1995022837A1 (en) * 1994-02-17 1995-08-24 National Semiconductor Corporation A method for reducing the spacing between the horizontally-adjacent floating gates of a flash eprom array
US5617328A (en) * 1994-05-23 1997-04-01 Winbond Electronics Corporation Automatic code pattern generator for repetitious patterns in an integrated circuit layout
JPH08321545A (ja) * 1995-05-24 1996-12-03 Yamaha Corp 配線形成法
DE19548058C2 (de) * 1995-12-21 1997-11-20 Siemens Ag Verfahren zur Herstellung eines MOS-Transistors
US5923981A (en) * 1996-12-31 1999-07-13 Intel Corporation Cascading transistor gate and method for fabricating the same
EP1071134A1 (de) 1999-07-22 2001-01-24 STMicroelectronics S.r.l. Verfahren zur Herstellung eines Halbleiterbauelementes mit EEPROM-Speicherzellen unter Kontrolle der Abmessungen der Floating-Gate-Gebiete
US6124167A (en) * 1999-08-06 2000-09-26 Micron Technology, Inc. Method for forming an etch mask during the manufacture of a semiconductor device
KR100437470B1 (ko) * 2001-01-31 2004-06-23 삼성전자주식회사 플래쉬 메모리 셀을 갖는 반도체 장치 및 그 제조 방법
KR100368594B1 (ko) * 2001-02-23 2003-01-24 삼성전자 주식회사 스플릿 게이트형 플래쉬 메모리소자
KR100470388B1 (ko) * 2002-05-03 2005-02-07 주식회사 하이닉스반도체 독립적이고 비대칭적인 소스/드레인을 포함하는 디램 셀및 그 형성 방법
US6583009B1 (en) * 2002-06-24 2003-06-24 Advanced Micro Devices, Inc. Innovative narrow gate formation for floating gate flash technology
US20060157773A1 (en) * 2005-01-14 2006-07-20 Yu Andy T Non-volatile electrically alterable memory cell for storing multiple data and manufacturing thereof
US20070166971A1 (en) * 2006-01-17 2007-07-19 Atmel Corporation Manufacturing of silicon structures smaller than optical resolution limits
EP2089898A1 (de) * 2006-11-06 2009-08-19 Nxp B.V. Verfahren zur herstellung eines fet-gates
KR100854504B1 (ko) * 2007-03-12 2008-08-26 삼성전자주식회사 플래쉬 메모리 소자의 제조방법 및 그에 의해 제조된플래쉬 메모리 소자
US8575683B1 (en) * 2012-05-16 2013-11-05 United Microelectronics Corp. Semiconductor device and method of fabricating the same
US9023726B1 (en) 2013-11-18 2015-05-05 United Microelectronics Corp. Method of fabricating semiconductor device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53124084A (en) * 1977-04-06 1978-10-30 Hitachi Ltd Semiconductor memory device containing floating type poly silicon layer and its manufacture
US4184207A (en) * 1978-01-27 1980-01-15 Texas Instruments Incorporated High density floating gate electrically programmable ROM
US4493057A (en) * 1980-01-07 1985-01-08 Texas Instruments Incorporated Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like
US4312680A (en) * 1980-03-31 1982-01-26 Rca Corporation Method of manufacturing submicron channel transistors
US4400865A (en) * 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4378627A (en) * 1980-07-08 1983-04-05 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
JPS5836508B2 (ja) * 1980-12-25 1983-08-09 富士通株式会社 半導体装置の製造方法
NL188432C (nl) * 1980-12-26 1992-06-16 Nippon Telegraph & Telephone Werkwijze voor het vervaardigen van een mosfet.
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
JPS60182171A (ja) * 1984-02-29 1985-09-17 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS6182482A (ja) * 1984-09-29 1986-04-26 Toshiba Corp ＧａＡｓ電界効果トランジスタの製造方法
FR2593327B1 (fr) * 1986-01-23 1988-10-28 Commissariat Energie Atomique Procede de fabrication d'un transistor en couches minces utilisant deux ou trois niveaux de masquage
FR2603128B1 (fr) * 1986-08-21 1988-11-10 Commissariat Energie Atomique Cellule de memoire eprom et son procede de fabrication

Also Published As

Publication number Publication date
FR2618011A1 (fr) 1989-01-13
US4851365A (en) 1989-07-25
EP0299853A1 (de) 1989-01-18
JPS6459870A (en) 1989-03-07
FR2618011B1 (fr) 1992-09-18
DE3884698T2 (de) 1994-05-05
JP2588486B2 (ja) 1997-03-05
EP0299853B1 (de) 1993-10-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition