DE68920094D1 - Verfahren zum Herstellen einer Halbleiteranordnung. - Google Patents

Verfahren zum Herstellen einer Halbleiteranordnung.

Info

Publication number
DE68920094D1
DE68920094D1 DE68920094T DE68920094T DE68920094D1 DE 68920094 D1 DE68920094 D1 DE 68920094D1 DE 68920094 T DE68920094 T DE 68920094T DE 68920094 T DE68920094 T DE 68920094T DE 68920094 D1 DE68920094 D1 DE 68920094D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68920094T
Other languages
English (en)
Other versions
DE68920094T2 (de
Inventor
Jan Haisma
Den Meerakker Johannes Eng Van
Vegchel Josephus Henricus Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE68920094D1 publication Critical patent/DE68920094D1/de
Application granted granted Critical
Publication of DE68920094T2 publication Critical patent/DE68920094T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Pressure Sensors (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)
DE68920094T 1988-08-09 1989-08-03 Verfahren zum Herstellen einer Halbleiteranordnung. Expired - Fee Related DE68920094T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8801981A NL8801981A (nl) 1988-08-09 1988-08-09 Werkwijze voor het vervaardigen van een halfgeleiderinrichting.

Publications (2)

Publication Number Publication Date
DE68920094D1 true DE68920094D1 (de) 1995-02-02
DE68920094T2 DE68920094T2 (de) 1995-06-29

Family

ID=19852732

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68920094T Expired - Fee Related DE68920094T2 (de) 1988-08-09 1989-08-03 Verfahren zum Herstellen einer Halbleiteranordnung.

Country Status (6)

Country Link
US (1) US4970175A (de)
EP (1) EP0357116B1 (de)
JP (1) JPH0281431A (de)
KR (1) KR900003968A (de)
DE (1) DE68920094T2 (de)
NL (1) NL8801981A (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200808A (en) * 1989-11-29 1993-04-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having smooth contact holes formed through multi-layer insulators of different etching speeds
US5334281A (en) * 1992-04-30 1994-08-02 International Business Machines Corporation Method of forming thin silicon mesas having uniform thickness
US5234846A (en) * 1992-04-30 1993-08-10 International Business Machines Corporation Method of making bipolar transistor with reduced topography
US5258318A (en) * 1992-05-15 1993-11-02 International Business Machines Corporation Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
JP2739018B2 (ja) * 1992-10-21 1998-04-08 三菱電機株式会社 誘電体分離半導体装置及びその製造方法
JPH06216093A (ja) * 1993-01-18 1994-08-05 Mitsubishi Materials Shilicon Corp 半導体基板の研磨方法とこれを用いた半導体基板の製造方法
US5413952A (en) * 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making
US5453396A (en) * 1994-05-31 1995-09-26 Micron Technology, Inc. Sub-micron diffusion area isolation with SI-SEG for a DRAM array
JPH0831791A (ja) * 1994-07-11 1996-02-02 Mitsubishi Electric Corp 半導体層の製造方法
US5668045A (en) * 1994-11-30 1997-09-16 Sibond, L.L.C. Process for stripping outer edge of BESOI wafers
US6420269B2 (en) 1996-02-07 2002-07-16 Hitachi Chemical Company, Ltd. Cerium oxide abrasive for polishing insulating films formed on substrate and methods for using the same
JPH1070187A (ja) * 1996-08-28 1998-03-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100281109B1 (ko) * 1997-12-15 2001-03-02 김영환 에스오아이(soi)소자및그의제조방법
US6348715B1 (en) 1997-12-15 2002-02-19 Lg Semicon Co., Ltd. SOI (silicon on insulator) device
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6563133B1 (en) 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US7642566B2 (en) * 2006-06-12 2010-01-05 Dsm Solutions, Inc. Scalable process and structure of JFET for small and decreasing line widths
US6294413B1 (en) * 2000-12-27 2001-09-25 Vanguard International Semiconductor Corp. Method for fabricating a SOI (silicon on insulator) device
JP2004103946A (ja) * 2002-09-11 2004-04-02 Canon Inc 基板及びその製造方法
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3850707A (en) * 1964-09-09 1974-11-26 Honeywell Inc Semiconductors
US3997381A (en) * 1975-01-10 1976-12-14 Intel Corporation Method of manufacture of an epitaxial semiconductor layer on an insulating substrate
JPS58197739A (ja) * 1982-04-23 1983-11-17 Jido Keisoku Gijutsu Kenkiyuukumiai 半導体集積回路用基板の製造方法
JPS58192346A (ja) * 1982-05-06 1983-11-09 Toshiba Corp 半導体装置の製造方法
US4554570A (en) * 1982-06-24 1985-11-19 Rca Corporation Vertically integrated IGFET device
JPS5919350A (ja) * 1982-07-23 1984-01-31 Jido Keisoku Gijutsu Kenkiyuukumiai 集積回路用基板の製造方法
US4501060A (en) * 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
JPS6054452A (ja) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd 半導体装置の製造方法
DE3583183D1 (de) * 1984-05-09 1991-07-18 Toshiba Kawasaki Kk Verfahren zur herstellung eines halbleitersubstrates.
JPS6116544A (ja) * 1984-07-03 1986-01-24 Nec Corp 半導体装置の製造方法
JPH0783050B2 (ja) * 1985-06-21 1995-09-06 株式会社東芝 半導体素子の製造方法
US4601779A (en) * 1985-06-24 1986-07-22 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
US4849371A (en) * 1986-12-22 1989-07-18 Motorola Inc. Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices
US4902641A (en) * 1987-07-31 1990-02-20 Motorola, Inc. Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure
US4851366A (en) * 1987-11-13 1989-07-25 Siliconix Incorporated Method for providing dielectrically isolated circuit
US4820653A (en) * 1988-02-12 1989-04-11 American Telephone And Telegraph Company Technique for fabricating complementary dielectrically isolated wafer
US4879258A (en) * 1988-08-31 1989-11-07 Texas Instruments Incorporated Integrated circuit planarization by mechanical polishing
US4908328A (en) * 1989-06-06 1990-03-13 National Semiconductor Corporation High voltage power IC process

Also Published As

Publication number Publication date
US4970175A (en) 1990-11-13
EP0357116B1 (de) 1994-12-21
EP0357116A1 (de) 1990-03-07
NL8801981A (nl) 1990-03-01
JPH0281431A (ja) 1990-03-22
DE68920094T2 (de) 1995-06-29
KR900003968A (ko) 1990-03-27

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee