DE68917995D1 - Verfahren zum Herstellen einer Halbleitervorrichtung. - Google Patents
Verfahren zum Herstellen einer Halbleitervorrichtung.Info
- Publication number
- DE68917995D1 DE68917995D1 DE68917995T DE68917995T DE68917995D1 DE 68917995 D1 DE68917995 D1 DE 68917995D1 DE 68917995 T DE68917995 T DE 68917995T DE 68917995 T DE68917995 T DE 68917995T DE 68917995 D1 DE68917995 D1 DE 68917995D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8813303A GB2219434A (en) | 1988-06-06 | 1988-06-06 | A method of forming a contact in a semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68917995D1 true DE68917995D1 (de) | 1994-10-13 |
DE68917995T2 DE68917995T2 (de) | 1995-05-04 |
Family
ID=10638124
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68917995T Expired - Fee Related DE68917995T2 (de) | 1988-06-06 | 1989-05-31 | Verfahren zum Herstellen einer Halbleitervorrichtung. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4956312A (de) |
EP (1) | EP0345875B1 (de) |
JP (1) | JPH0680651B2 (de) |
CN (1) | CN1018309B (de) |
DE (1) | DE68917995T2 (de) |
GB (1) | GB2219434A (de) |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5201993A (en) * | 1989-07-20 | 1993-04-13 | Micron Technology, Inc. | Anisotropic etch method |
KR910013463A (ko) * | 1989-12-29 | 1991-08-08 | 김광호 | 반도체 소자의 개구형성방법 |
US5049525A (en) * | 1990-06-29 | 1991-09-17 | Texas Instruments Incorporated | Iterative self-aligned contact metallization process |
DE69128050D1 (de) * | 1990-06-29 | 1997-12-04 | Applied Materials Inc | Zweistufiges Selbstreinigungsverfahren einer Reaktionskammer |
US5162261A (en) * | 1990-12-05 | 1992-11-10 | Texas Instruments Incorporated | Method of forming a via having sloped sidewalls |
KR920015542A (ko) * | 1991-01-14 | 1992-08-27 | 김광호 | 반도체장치의 다층배선형성법 |
KR950000519B1 (ko) * | 1991-02-28 | 1995-01-24 | 현대전자산업 주식회사 | 폴리실리콘층을 이용한 자기정렬콘택 제조방법 |
JPH04356944A (ja) * | 1991-04-03 | 1992-12-10 | Matsushita Electron Corp | 半導体装置およびその製造方法 |
JP3166221B2 (ja) * | 1991-07-23 | 2001-05-14 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH0529254A (ja) * | 1991-07-24 | 1993-02-05 | Sony Corp | 配線形成方法 |
JPH0562967A (ja) * | 1991-09-02 | 1993-03-12 | Sharp Corp | 半導体装置の製造方法 |
US5356722A (en) * | 1992-06-10 | 1994-10-18 | Applied Materials, Inc. | Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity |
KR100260577B1 (ko) * | 1992-09-09 | 2000-08-01 | 김영환 | 자기정렬형 콘택 형성방법 |
US5756397A (en) * | 1993-12-28 | 1998-05-26 | Lg Semicon Co., Ltd. | Method of fabricating a wiring in a semiconductor device |
US6111319A (en) * | 1995-12-19 | 2000-08-29 | Stmicroelectronics, Inc. | Method of forming submicron contacts and vias in an integrated circuit |
US6066555A (en) | 1995-12-22 | 2000-05-23 | Cypress Semiconductor Corporation | Method for eliminating lateral spacer erosion on enclosed contact topographies during RF sputter cleaning |
US6337266B1 (en) | 1996-07-22 | 2002-01-08 | Micron Technology, Inc. | Small electrode for chalcogenide memories |
US6149974A (en) | 1997-05-05 | 2000-11-21 | Applied Materials, Inc. | Method for elimination of TEOS/ozone silicon oxide surface sensitivity |
US6780776B1 (en) * | 2001-12-20 | 2004-08-24 | Advanced Micro Devices, Inc. | Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer |
KR100467021B1 (ko) * | 2002-08-20 | 2005-01-24 | 삼성전자주식회사 | 반도체 소자의 콘택 구조체 및 그 제조방법 |
US7749911B2 (en) * | 2004-11-30 | 2010-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an improved T-shaped gate structure |
US7442649B2 (en) * | 2005-03-29 | 2008-10-28 | Lam Research Corporation | Etch with photoresist mask |
US8575026B2 (en) * | 2011-11-03 | 2013-11-05 | Infineon Technologies Ag | Method of protecting sidewall surfaces of a semiconductor substrate |
KR102178986B1 (ko) | 2013-01-18 | 2020-11-18 | 예일 유니버시티 | 적어도 하나의 인클로저를 구비하는 초전도 디바이스 |
SG11201505617UA (en) * | 2013-01-18 | 2015-09-29 | Univ Yale | Methods for making a superconducting device with at least one enclosure |
US20150187701A1 (en) | 2013-03-12 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Devices and Methods of Manufacture Thereof |
US9076715B2 (en) | 2013-03-12 | 2015-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for connecting dies and methods of forming the same |
US20140357083A1 (en) * | 2013-05-31 | 2014-12-04 | Applied Materials, Inc. | Directed block copolymer self-assembly patterns for advanced photolithography applications |
US10541659B2 (en) | 2013-10-15 | 2020-01-21 | Yale University | Low-noise josephson junction-based directional amplifier |
US9412719B2 (en) * | 2013-12-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US10056353B2 (en) | 2013-12-19 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US9425150B2 (en) | 2014-02-13 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-via interconnect structure and method of manufacture |
US9948254B2 (en) | 2014-02-21 | 2018-04-17 | Yale University | Wireless Josephson bifurcation amplifier |
JP2014160846A (ja) * | 2014-04-10 | 2014-09-04 | Renesas Electronics Corp | 半導体記憶装置 |
US9543257B2 (en) | 2014-05-29 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect devices and methods of forming same |
US9455158B2 (en) | 2014-05-30 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect devices and methods of forming same |
US9449914B2 (en) | 2014-07-17 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuits with redistribution lines |
KR102493109B1 (ko) | 2015-02-27 | 2023-01-30 | 예일 유니버시티 | 조셉슨 접합-기반 서큘레이터 및 관련 시스템 및 방법 |
US10404214B2 (en) | 2015-02-27 | 2019-09-03 | Yale University | Techniques for producing quantum amplifiers and related systems and methods |
WO2016138395A1 (en) | 2015-02-27 | 2016-09-01 | Yale University | Techniques for coupling plannar qubits to non-planar resonators and related systems and methods |
SG11201708202TA (en) | 2015-04-17 | 2017-11-29 | Univ Yale | Wireless josephson parametric converter |
CN106158765B (zh) * | 2015-04-24 | 2019-03-12 | 旺宏电子股份有限公司 | 半导体元件及其制造方法 |
CN106601793B (zh) * | 2015-10-15 | 2020-05-01 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
US11184006B2 (en) | 2016-01-15 | 2021-11-23 | Yale University | Techniques for manipulation of two-qubit quantum states and related systems and methods |
WO2019118442A1 (en) | 2017-12-11 | 2019-06-20 | Yale University | Superconducting nonlinear asymmetric inductive element and related systems and methods |
US10546992B2 (en) | 2018-06-28 | 2020-01-28 | International Business Machines Corporation | Buried electrode geometry for lowering surface losses in superconducting microwave circuits |
US11223355B2 (en) | 2018-12-12 | 2022-01-11 | Yale University | Inductively-shunted transmon qubit for superconducting circuits |
US11791818B2 (en) | 2019-01-17 | 2023-10-17 | Yale University | Josephson nonlinear circuit |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4322883A (en) * | 1980-07-08 | 1982-04-06 | International Business Machines Corporation | Self-aligned metal process for integrated injection logic integrated circuits |
US4507853A (en) * | 1982-08-23 | 1985-04-02 | Texas Instruments Incorporated | Metallization process for integrated circuits |
FR2549293B1 (fr) * | 1983-07-13 | 1986-10-10 | Silicium Semiconducteur Ssc | Transistor bipolaire haute frequence et son procede de fabrication |
US4641420A (en) * | 1984-08-30 | 1987-02-10 | At&T Bell Laboratories | Metalization process for headless contact using deposited smoothing material |
SE453547B (sv) * | 1985-03-07 | 1988-02-08 | Stiftelsen Inst Mikrovags | Forfarande vid framstellning av integrerade kretsar der pa en substratplatta ledare och s k gate-strukturer uppbygges |
JPS62517A (ja) * | 1985-06-26 | 1987-01-06 | Daicel Chem Ind Ltd | 光素子用封止剤 |
US4751198A (en) * | 1985-09-11 | 1988-06-14 | Texas Instruments Incorporated | Process for making contacts and interconnections using direct-reacted silicide |
US4818723A (en) * | 1985-11-27 | 1989-04-04 | Advanced Micro Devices, Inc. | Silicide contact plug formation technique |
JPH07121864B2 (ja) * | 1987-06-26 | 1995-12-25 | 日本ケミファ株式会社 | 脳障害抑制作用を有する医薬組成物 |
JP3437328B2 (ja) * | 1995-06-16 | 2003-08-18 | 株式会社内田洋行 | Oa機器固定用具 |
JPH091943A (ja) * | 1995-06-19 | 1997-01-07 | Fuji Photo Film Co Ltd | 熱転写受像材料 |
-
1988
- 1988-06-06 GB GB8813303A patent/GB2219434A/en not_active Withdrawn
-
1989
- 1989-05-19 US US07/354,001 patent/US4956312A/en not_active Expired - Lifetime
- 1989-05-31 DE DE68917995T patent/DE68917995T2/de not_active Expired - Fee Related
- 1989-05-31 EP EP89201391A patent/EP0345875B1/de not_active Expired - Lifetime
- 1989-06-03 JP JP1140261A patent/JPH0680651B2/ja not_active Expired - Fee Related
- 1989-06-03 CN CN89104990.8A patent/CN1018309B/zh not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0345875A3 (en) | 1990-03-21 |
JPH0680651B2 (ja) | 1994-10-12 |
JPH0225026A (ja) | 1990-01-26 |
EP0345875B1 (de) | 1994-09-07 |
CN1042274A (zh) | 1990-05-16 |
US4956312A (en) | 1990-09-11 |
GB2219434A (en) | 1989-12-06 |
GB8813303D0 (en) | 1988-07-13 |
CN1018309B (zh) | 1992-09-16 |
DE68917995T2 (de) | 1995-05-04 |
EP0345875A2 (de) | 1989-12-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE68917995D1 (de) | Verfahren zum Herstellen einer Halbleitervorrichtung. | |
DE68919549D1 (de) | Verfahren zum Herstellen einer Halbleiteranordnung. | |
DE69022087D1 (de) | Verfahren zum Herstellen einer Halbleiteranordnung. | |
DE68911621D1 (de) | Verfahren zum Herstellen einer Einrichtung. | |
DE69030229D1 (de) | Verfahren zum Herstellen einer Halbleitervorrichtung | |
DE69033736D1 (de) | Verfahren zum Herstellen einer Halbleitervorrichtung | |
DE69133316D1 (de) | Verfahren zum Herstellen einer Halbleitervorrichtung | |
DE69031184D1 (de) | Verfahren zum Herstellen einer Halbleiterbauelement-Packung | |
DE69031543D1 (de) | Verfahren zum Herstellen einer Halbleitervorrichtung | |
DE68920094D1 (de) | Verfahren zum Herstellen einer Halbleiteranordnung. | |
DE3750325D1 (de) | Verfahren zum Herstellen eines Halbleiterbauelements. | |
DE3780369D1 (de) | Verfahren zum herstellen einer halbleiterstruktur. | |
DE3686600D1 (de) | Verfahren zum herstellen einer harzumhuellten halbleiteranordnung. | |
DE3583934D1 (de) | Verfahren zum herstellen einer halbleiterverbundanordnung. | |
DE69004842D1 (de) | Strahlungemittierende Halbleiteranordnung und Verfahren zum Herstellen einer derartigen Halbleiteranordnung. | |
DE69028964D1 (de) | Verfahren zum Herstellen einer Halbleitervorrichtung | |
DE68926656D1 (de) | Verfahren zum Herstellen eines Halbleiterbauelementes | |
DE68925632D1 (de) | Verfahren zum Metallisieren einer Halbleitervorrichtung | |
DE69006434D1 (de) | Herstellungsverfahren einer Halbleiteranordnung. | |
DE3784605D1 (de) | Verfahren zum herstellen einer halbleitervorrichtung und halbleitervorrichtung. | |
DE68906034D1 (de) | Verfahren zum herstellen einer halbleiteranordnung. | |
DE69017332D1 (de) | Verfahren zum Herstellen einer eine Mesa enthaltenden Halbleiteranordnung. | |
DE3671324D1 (de) | Verfahren zum herstellen einer halbleiteranordnung. | |
DE3877282D1 (de) | Verfahren zum herstellen einer halbleiter-vorrichtung. | |
DE69120975D1 (de) | Verfahren zum Herstellen einer Halbleitervorrichtung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8327 | Change in the person/name/address of the patent owner |
Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL |
|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N |
|
8320 | Willingness to grant licences declared (paragraph 23) | ||
8339 | Ceased/non-payment of the annual fee |