GB2199695B - Dynamic random access memory with selective well biasing - Google Patents
Dynamic random access memory with selective well biasingInfo
- Publication number
- GB2199695B GB2199695B GB8729622A GB8729622A GB2199695B GB 2199695 B GB2199695 B GB 2199695B GB 8729622 A GB8729622 A GB 8729622A GB 8729622 A GB8729622 A GB 8729622A GB 2199695 B GB2199695 B GB 2199695B
- Authority
- GB
- United Kingdom
- Prior art keywords
- random access
- access memory
- dynamic random
- well biasing
- selective well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US74787A | 1987-01-06 | 1987-01-06 |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8729622D0 GB8729622D0 (en) | 1988-02-03 |
GB2199695A GB2199695A (en) | 1988-07-13 |
GB2199695B true GB2199695B (en) | 1990-07-25 |
Family
ID=21692854
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8729622A Expired - Fee Related GB2199695B (en) | 1987-01-06 | 1987-12-18 | Dynamic random access memory with selective well biasing |
Country Status (5)
Country | Link |
---|---|
KR (1) | KR880009440A (en) |
DE (1) | DE3744376A1 (en) |
FR (1) | FR2609351A1 (en) |
GB (1) | GB2199695B (en) |
NL (1) | NL8800008A (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910000246B1 (en) * | 1988-02-15 | 1991-01-23 | 삼성전자 주식회사 | Semiconductor memory device |
KR930006144B1 (en) * | 1990-07-12 | 1993-07-07 | 삼성전자 주식회사 | Semiconductor device and manufacturing method thereof |
KR930001392A (en) * | 1991-06-19 | 1993-01-16 | 김광호 | Power Ground Wire Wiring Method for Semiconductor Memory Device |
US5264716A (en) * | 1992-01-09 | 1993-11-23 | International Business Machines Corporation | Diffused buried plate trench dram cell array |
EP0550894B1 (en) * | 1992-01-09 | 1999-08-04 | International Business Machines Corporation | Trench DRAM cell array |
JP2904635B2 (en) * | 1992-03-30 | 1999-06-14 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US5595925A (en) * | 1994-04-29 | 1997-01-21 | Texas Instruments Incorporated | Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein |
US7005338B2 (en) | 2002-09-19 | 2006-02-28 | Promos Technologies Inc. | Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0066429A2 (en) * | 1981-05-22 | 1982-12-08 | Hitachi, Ltd. | Semiconductor memory |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57194565A (en) * | 1981-05-25 | 1982-11-30 | Toshiba Corp | Semiconductor memory device |
JPH0671067B2 (en) * | 1985-11-20 | 1994-09-07 | 株式会社日立製作所 | Semiconductor device |
-
1987
- 1987-12-18 GB GB8729622A patent/GB2199695B/en not_active Expired - Fee Related
- 1987-12-26 KR KR870014950A patent/KR880009440A/en not_active Application Discontinuation
- 1987-12-29 DE DE19873744376 patent/DE3744376A1/en not_active Withdrawn
-
1988
- 1988-01-05 NL NL8800008A patent/NL8800008A/en not_active Application Discontinuation
- 1988-01-06 FR FR8800058A patent/FR2609351A1/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0066429A2 (en) * | 1981-05-22 | 1982-12-08 | Hitachi, Ltd. | Semiconductor memory |
Also Published As
Publication number | Publication date |
---|---|
GB2199695A (en) | 1988-07-13 |
KR880009440A (en) | 1988-09-15 |
NL8800008A (en) | 1988-08-01 |
GB8729622D0 (en) | 1988-02-03 |
DE3744376A1 (en) | 1988-07-14 |
FR2609351A1 (en) | 1988-07-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |