FR2816110B1 - Lignes de bit en memoire dram - Google Patents

Lignes de bit en memoire dram

Info

Publication number
FR2816110B1
FR2816110B1 FR0013854A FR0013854A FR2816110B1 FR 2816110 B1 FR2816110 B1 FR 2816110B1 FR 0013854 A FR0013854 A FR 0013854A FR 0013854 A FR0013854 A FR 0013854A FR 2816110 B1 FR2816110 B1 FR 2816110B1
Authority
FR
France
Prior art keywords
bit lines
memory dram
dram
memory
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0013854A
Other languages
English (en)
Other versions
FR2816110A1 (fr
Inventor
Jerome Ciavatti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0013854A priority Critical patent/FR2816110B1/fr
Priority to US10/044,307 priority patent/US6716715B2/en
Publication of FR2816110A1 publication Critical patent/FR2816110A1/fr
Application granted granted Critical
Publication of FR2816110B1 publication Critical patent/FR2816110B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • H10B12/485Bit line contacts
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/954Making oxide-nitride-oxide device
FR0013854A 2000-10-27 2000-10-27 Lignes de bit en memoire dram Expired - Fee Related FR2816110B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0013854A FR2816110B1 (fr) 2000-10-27 2000-10-27 Lignes de bit en memoire dram
US10/044,307 US6716715B2 (en) 2000-10-27 2001-10-26 Dram bit lines

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0013854A FR2816110B1 (fr) 2000-10-27 2000-10-27 Lignes de bit en memoire dram

Publications (2)

Publication Number Publication Date
FR2816110A1 FR2816110A1 (fr) 2002-05-03
FR2816110B1 true FR2816110B1 (fr) 2003-03-21

Family

ID=8855840

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0013854A Expired - Fee Related FR2816110B1 (fr) 2000-10-27 2000-10-27 Lignes de bit en memoire dram

Country Status (2)

Country Link
US (1) US6716715B2 (fr)
FR (1) FR2816110B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6710381B1 (en) * 2002-10-08 2004-03-23 Macronix International Co., Ltd. Memory device structure with composite buried and raised bit line
US10083734B1 (en) * 2017-11-06 2018-09-25 Micron Technology, Inc. Memory arrays

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910009805B1 (ko) * 1987-11-25 1991-11-30 후지쓰 가부시끼가이샤 다이나믹 랜덤 액세스 메모리 장치와 그의 제조방법
JPH0824169B2 (ja) * 1989-05-10 1996-03-06 富士通株式会社 半導体記憶装置の製造方法
US6140705A (en) * 1995-01-03 2000-10-31 Texas Instruments Incorporated Self-aligned contact through a conducting layer
JP3532325B2 (ja) * 1995-07-21 2004-05-31 株式会社東芝 半導体記憶装置
JP3241242B2 (ja) * 1995-09-22 2001-12-25 株式会社東芝 半導体記憶装置の製造方法
US5789289A (en) * 1996-06-18 1998-08-04 Vanguard International Semiconductor Corporation Method for fabricating vertical fin capacitor structures
JPH10178160A (ja) * 1996-12-17 1998-06-30 Hitachi Ltd 半導体集積回路装置およびその製造方法
KR100276387B1 (ko) * 1998-01-08 2000-12-15 윤종용 반도체 장치의 자기정렬 콘택 형성 방법
US5893734A (en) * 1998-09-14 1999-04-13 Vanguard International Semiconductor Corporation Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts
US6083790A (en) * 1999-02-11 2000-07-04 Taiwan Semiconductor Manufacturing Company Ltd. Method for making y-shaped multi-fin stacked capacitors for dynamic random access memory cells

Also Published As

Publication number Publication date
US6716715B2 (en) 2004-04-06
FR2816110A1 (fr) 2002-05-03
US20020126548A1 (en) 2002-09-12

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090630