AU2001280547A1 - Partitioned random access memory - Google Patents

Partitioned random access memory

Info

Publication number
AU2001280547A1
AU2001280547A1 AU2001280547A AU8054701A AU2001280547A1 AU 2001280547 A1 AU2001280547 A1 AU 2001280547A1 AU 2001280547 A AU2001280547 A AU 2001280547A AU 8054701 A AU8054701 A AU 8054701A AU 2001280547 A1 AU2001280547 A1 AU 2001280547A1
Authority
AU
Australia
Prior art keywords
random access
access memory
partitioned random
partitioned
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001280547A
Inventor
Ronald Melanson
Gregory Papadopoulos
Renu Raman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of AU2001280547A1 publication Critical patent/AU2001280547A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
AU2001280547A 2000-07-14 2001-07-13 Partitioned random access memory Abandoned AU2001280547A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US21834600P 2000-07-14 2000-07-14
US60/218,346 2000-07-14
US09/904,884 US6854084B2 (en) 2000-07-14 2001-07-12 Partitioned random access memory
US09/904,884 2001-07-12
PCT/US2001/022201 WO2002008901A2 (en) 2000-07-14 2001-07-13 Partitioned random access memory

Publications (1)

Publication Number Publication Date
AU2001280547A1 true AU2001280547A1 (en) 2002-02-05

Family

ID=26912817

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001280547A Abandoned AU2001280547A1 (en) 2000-07-14 2001-07-13 Partitioned random access memory

Country Status (3)

Country Link
US (1) US6854084B2 (en)
AU (1) AU2001280547A1 (en)
WO (1) WO2002008901A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7676730B2 (en) * 2005-09-30 2010-03-09 Quantum Corporation Method and apparatus for implementing error correction coding in a random access memory
TWI326413B (en) * 2007-02-12 2010-06-21 Nanya Technology Corp Control method for memory access
US9368199B2 (en) * 2014-09-02 2016-06-14 Kabushiki Kaisha Toshiba Memory device
US10552258B2 (en) * 2016-09-16 2020-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device, and driving method thereof
KR102545189B1 (en) * 2018-09-07 2023-06-19 삼성전자주식회사 Storage device, storage system and method of operating storage device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611042A (en) * 1995-10-10 1997-03-11 Lordi; Angela L. Data error detection and correction for a shared SRAM
US5916314A (en) 1996-09-11 1999-06-29 Sequent Computer Systems, Inc. Method and apparatus for cache tag mirroring
US6237124B1 (en) * 1998-03-16 2001-05-22 Actel Corporation Methods for errors checking the configuration SRAM and user assignable SRAM data in a field programmable gate array

Also Published As

Publication number Publication date
WO2002008901A3 (en) 2002-08-15
WO2002008901A2 (en) 2002-01-31
US6854084B2 (en) 2005-02-08
US20020046383A1 (en) 2002-04-18

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