FR2829278B1 - Memoire a lignes de bits partagees - Google Patents
Memoire a lignes de bits partageesInfo
- Publication number
- FR2829278B1 FR2829278B1 FR0111298A FR0111298A FR2829278B1 FR 2829278 B1 FR2829278 B1 FR 2829278B1 FR 0111298 A FR0111298 A FR 0111298A FR 0111298 A FR0111298 A FR 0111298A FR 2829278 B1 FR2829278 B1 FR 2829278B1
- Authority
- FR
- France
- Prior art keywords
- memory
- bit lines
- shared bit
- shared
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0111298A FR2829278B1 (fr) | 2001-08-31 | 2001-08-31 | Memoire a lignes de bits partagees |
JP2002247169A JP4321022B2 (ja) | 2001-08-31 | 2002-08-27 | 共有のビットラインを備えたメモリ |
US10/232,256 US6775179B2 (en) | 2001-08-31 | 2002-08-30 | Memory with shared bit lines |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0111298A FR2829278B1 (fr) | 2001-08-31 | 2001-08-31 | Memoire a lignes de bits partagees |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2829278A1 FR2829278A1 (fr) | 2003-03-07 |
FR2829278B1 true FR2829278B1 (fr) | 2005-04-15 |
Family
ID=8866854
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0111298A Expired - Lifetime FR2829278B1 (fr) | 2001-08-31 | 2001-08-31 | Memoire a lignes de bits partagees |
Country Status (3)
Country | Link |
---|---|
US (1) | US6775179B2 (fr) |
JP (1) | JP4321022B2 (fr) |
FR (1) | FR2829278B1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7366046B2 (en) * | 2005-08-16 | 2008-04-29 | Novelics, Llc | DRAM density enhancements |
US8760955B2 (en) * | 2011-10-21 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse memory arrays |
ITTO20120682A1 (it) * | 2012-07-31 | 2014-02-01 | St Microelectronics Pvt Ltd | Dispositivo di memoria non volatile con celle raggruppate |
KR102475446B1 (ko) * | 2016-09-20 | 2022-12-08 | 에스케이하이닉스 주식회사 | 반도체 메모리 소자 및 그 제조방법 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2600304B2 (ja) * | 1988-06-30 | 1997-04-16 | 三菱電機株式会社 | 半導体記憶装置とこれを用いたデータパス |
US5276650A (en) * | 1992-07-29 | 1994-01-04 | Intel Corporation | Memory array size reduction |
JP2732762B2 (ja) * | 1992-09-21 | 1998-03-30 | 株式会社東芝 | 半導体記憶装置 |
JPH06334138A (ja) * | 1993-03-26 | 1994-12-02 | Sony Corp | 半導体記憶装置 |
-
2001
- 2001-08-31 FR FR0111298A patent/FR2829278B1/fr not_active Expired - Lifetime
-
2002
- 2002-08-27 JP JP2002247169A patent/JP4321022B2/ja not_active Expired - Fee Related
- 2002-08-30 US US10/232,256 patent/US6775179B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2003152112A (ja) | 2003-05-23 |
JP4321022B2 (ja) | 2009-08-26 |
FR2829278A1 (fr) | 2003-03-07 |
US6775179B2 (en) | 2004-08-10 |
US20030063501A1 (en) | 2003-04-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
GC | Lien (pledge) constituted |
Effective date: 20150630 |
|
PLFP | Fee payment |
Year of fee payment: 16 |
|
PLFP | Fee payment |
Year of fee payment: 17 |