FR2885727B1 - Plan de memoire morte a lignes de bit torsadees - Google Patents

Plan de memoire morte a lignes de bit torsadees

Info

Publication number
FR2885727B1
FR2885727B1 FR0504870A FR0504870A FR2885727B1 FR 2885727 B1 FR2885727 B1 FR 2885727B1 FR 0504870 A FR0504870 A FR 0504870A FR 0504870 A FR0504870 A FR 0504870A FR 2885727 B1 FR2885727 B1 FR 2885727B1
Authority
FR
France
Prior art keywords
torsadees
bit lines
dead memory
memory plan
plan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0504870A
Other languages
English (en)
Other versions
FR2885727A1 (fr
Inventor
Francois Jacquet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0504870A priority Critical patent/FR2885727B1/fr
Priority to US11/433,046 priority patent/US7327594B2/en
Publication of FR2885727A1 publication Critical patent/FR2885727A1/fr
Application granted granted Critical
Publication of FR2885727B1 publication Critical patent/FR2885727B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
FR0504870A 2005-05-13 2005-05-13 Plan de memoire morte a lignes de bit torsadees Expired - Fee Related FR2885727B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0504870A FR2885727B1 (fr) 2005-05-13 2005-05-13 Plan de memoire morte a lignes de bit torsadees
US11/433,046 US7327594B2 (en) 2005-05-13 2006-05-12 Read-only memory with twisted bit lines

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0504870A FR2885727B1 (fr) 2005-05-13 2005-05-13 Plan de memoire morte a lignes de bit torsadees

Publications (2)

Publication Number Publication Date
FR2885727A1 FR2885727A1 (fr) 2006-11-17
FR2885727B1 true FR2885727B1 (fr) 2007-07-20

Family

ID=35709051

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0504870A Expired - Fee Related FR2885727B1 (fr) 2005-05-13 2005-05-13 Plan de memoire morte a lignes de bit torsadees

Country Status (2)

Country Link
US (1) US7327594B2 (fr)
FR (1) FR2885727B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8344429B2 (en) 2008-09-17 2013-01-01 Infineon Technologies Ag Compact memory arrays
JP5580981B2 (ja) * 2008-11-21 2014-08-27 ラピスセミコンダクタ株式会社 半導体素子及び半導体装置
US8988917B2 (en) * 2012-11-15 2015-03-24 Sandisk Technologies Inc. Bit line resistance compensation
US9583209B1 (en) 2015-12-08 2017-02-28 Arm Limited High density memory architecture
US10672459B2 (en) 2018-02-07 2020-06-02 Arm Limited Transition coupling circuitry for memory applications

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107459A (en) * 1990-04-20 1992-04-21 International Business Machines Corporation Stacked bit-line architecture for high density cross-point memory cell array
US7259464B1 (en) * 2000-05-09 2007-08-21 Micron Technology, Inc. Vertical twist scheme for high-density DRAMs
US6259621B1 (en) * 2000-07-06 2001-07-10 Micron Technology, Inc. Method and apparatus for minimization of data line coupling in a semiconductor memory device
CA2342496A1 (fr) * 2001-03-30 2002-09-30 Atmos Corporation Connexions metalliques torsadees pour canal mot

Also Published As

Publication number Publication date
US7327594B2 (en) 2008-02-05
FR2885727A1 (fr) 2006-11-17
US20060256604A1 (en) 2006-11-16

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20140131