DE112005002302B4 - Verfahren zur Herstellung von Metallgate-Transistoren mit epitaktischen Source- und Drainregionen und MOS-Transistor - Google Patents
Verfahren zur Herstellung von Metallgate-Transistoren mit epitaktischen Source- und Drainregionen und MOS-Transistor Download PDFInfo
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- DE112005002302B4 DE112005002302B4 DE112005002302T DE112005002302T DE112005002302B4 DE 112005002302 B4 DE112005002302 B4 DE 112005002302B4 DE 112005002302 T DE112005002302 T DE 112005002302T DE 112005002302 T DE112005002302 T DE 112005002302T DE 112005002302 B4 DE112005002302 B4 DE 112005002302B4
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- Prior art keywords
- source
- drain regions
- metal
- substrate
- silicon
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 38
- 239000002184 metal Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 25
- 239000002019 doping agent Substances 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000008021 deposition Effects 0.000 description 5
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000008450 motivation Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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Abstract
Verfahren zur Fertigung von Halbleitertransistoren, welches folgendes umfaßt:
Wachsen einer undotierten oder leicht dotierten Siliziumschicht auf einem stark dotierten Substrat;
Ausbilden von Polysilizium-Opfergates auf der Siliziumschicht;
Ätzen der Siliziumschicht und Unterschneiden der Gatestrukturen, um Siliziumkörper unter den Gatestrukturen auszubilden;
Wachsen von Source- und Drainregionen, die sich in die Unterschneidungen angrenzend an die Siliziumkörper erstrecken;
Entfernen der Polysiliziumgates; und
Ausbilden von Metallgates an Stelle der Polysiliziumgates.
Wachsen einer undotierten oder leicht dotierten Siliziumschicht auf einem stark dotierten Substrat;
Ausbilden von Polysilizium-Opfergates auf der Siliziumschicht;
Ätzen der Siliziumschicht und Unterschneiden der Gatestrukturen, um Siliziumkörper unter den Gatestrukturen auszubilden;
Wachsen von Source- und Drainregionen, die sich in die Unterschneidungen angrenzend an die Siliziumkörper erstrecken;
Entfernen der Polysiliziumgates; und
Ausbilden von Metallgates an Stelle der Polysiliziumgates.
Description
- ERFINDUNGSGEBIET
- Die Erfindung betrifft das Gebiet der MOS-Transistoren, und zwar solche, die mit epitaktischen Source- und Drainregionen gefertigt werden.
- STAND DER TECHNIK UND VERWANDTE VERFAHREN
- Delta-dotierte Transistoren werden in „0.1 μm Delta-Doped MOSFET Using Post Low Energy Implanting Selective Epitaxy," VLSI Technology 1994, Digest of Technical Papers von Noda et al. beschrieben. Die Motivation für delta-dotierte Transistoren liegt darin, daß eine höhere Mobilität (weniger Störstellenstreuung) mit einem nicht-dotierten oder leicht dotierten Kanal erreicht wird.
- Solche Vorrichtungen werden auch in der
WO 2005/041288 A1 -
US 6,777,761 B2 beschreibt eine Halbleiterstruktur, die sowohl Metall- als auch Polysilizium-Gates auf einem Substrat aufweist. Jede thermische Bearbeitung der Halbleiterstruktur über einer für das Metall schädlichen Temperatur wird vor der Beschichtung mit Metall durchgeführt. - Die Fertigung dieser Transistoren beruht zum großen Teil auf dem Unterschied in den Dotierungspegeln zwischen dem stark dotierten Substrat und der leicht dotierten oder undotierten epitaktisch ausgebildeten Oberfläche des Substrats. Ein Ätzmittel kann wegen dieses Unterschieds im Dotierungspegel zwischen der Oberflächenregion und dem Hauptkörper des Substrats unterscheiden. Ein auftretendes Problem liegt jedoch darin, daß, wenn die Gatestrukturen ausgebildet werden, eine Hochtemperaturverarbeitung nötig ist, um beispielsweise das Dotiermittel in einem Polysiliziumgate zu aktivieren. Dies führt zu einer Diffusion des Dotiermittels aus dem Substrat in die Kanalregion, wobei die Leistung der Transistoren verschlechtert wird.
- Die Erfindung sieht zur Lösung des Problems ein Verfahren nach Anspruch 1 und einen MOS-Transistor nach Anspruch 15 vor.
- KURZE BESCHREIBUNG DER ZEICHNUNGEN
-
1 ist ein seitlicher Querschnitt des oberen Teils eines Siliziumsubstrats, der verwendet wird, um das Dotierungsprofil im oberen Bereich des Substrats darzustellen. -
2 stellt das Substrat von1 dar, nachdem eine undotierte oder leicht dotierte Halbleiterschicht auf dem Substrat gewachsen ist. -
3 ist ein seitlicher Querschnitt des Substrats und der Halbleiterschicht von2 zusätzlich zu anderen Schichten, die zum Ausbilden von Gates verwendet werden. -
4 stellt das Substrat von3 dar, nachdem die Gates ausgebildet wurden. -
5 stellt das Substrat von4 dar, nachdem die Seitenwand-Abstandhalter auf den Gates ausgebildet wurden. -
6 stellt das Substrat von5 nach einem Ätzschritt dar, der zum Ätzen der Halbleiterschicht verwendet wird. Diese Figur zeigt das Unterschneiden des Gates. -
7 stellt das Substrat von6 dar, nachdem Source- und Drainregionen epitaktisch gewachsen wurden. -
8 stellt die Struktur von7 dar, nachdem zusätzliche Abstandhalter und die Dotierung des ausgesetzten Teils der Source- und der Drainregionen ausgebildet wurden. -
9 stellt die Struktur von8 dar, nachdem eine Salicide-Schicht ausgebildet wurde. -
10 stellt die Struktur von9 dar, wobei zwei Transistoren Seite an Seite gezeigt werden, genauer werden ein n-Kanal-Transistor und ein p-Kanal-Transistor abgebildet. -
11 stellt die Struktur von10 dar, nachdem eine chemisch-mechanische Politur (CMP) eines Zwischenschicht-Dielektrikums (ILD) durchgeführt wurde. -
12 stellt die Struktur von11 dar, nachdem eine Photoresistschicht über der p-Kanal-Transistorregion ausgebildet wurde und das Polysiliziumgate und seine darunter liegende Isolierschicht von dem n-Kanal-Gate entfernt wurden. -
13 stellt die Struktur von12 dar, nachdem eine n-Metall-Schicht ausgebildet wurde. -
14 stellt die Struktur von13 nach einem CMP-Verfahren dar. -
15 stellt die Struktur von14 dar, nachdem das Polysiliziumgate und die darunter liegende Isolierschicht von dem p-Kanal-Gate entfernt wurden. -
16 stellt die Struktur von15 dar, nachdem ein p-Metall abgelagert wurde. -
17 stellt die Struktur von16 nach einem CMP-Verfahren dar. - DETAILLIERTE BESCHREIBUNG
- Es werden ein Verfahren zur Fertigung von komplementären Metall-Oxid-Halbleiter(MOS)-Feldeffekttransistoren und der resultierende Transistor beschrieben. In der folgenden Beschreibung werden viele spezifische Details angegeben, wie etwa spezifische Dotiermittel-Konzentrationspegel, spezifische Chemikalien usw., um ein gründliches Verständnis der vorliegenden Erfindung bereitzustellen. Es wird für einen Fachmann deutlich sein, daß diese spezifischen Details nicht notwendig sind, um die vorliegende Erfindung anzuwenden. In anderen Fällen werden bekannte Verfahrensschritte, wie etwa Reinigungsschritte, nicht im Detail beschrieben, um die folgende Offenlegung nicht unnötig zu verdunkeln.
- In
1 sind die oberen etwa 200 Nanometer (nm) eines monokristallinen Siliziumsubstrats10 dargestellt. Wie gezeigt ist, ist der obere Bereich dieses Substrats stark mit einem Dotiermittel, wie etwa Bor, dotiert. Das Dotierungsprofil zeigt, daß der Dotierungspegel ein Maximum unter der Oberfläche jenseits von 1019 Atomen/cm3 oder mehr aufweist. Dieses Dotierungsprofil kann mittels Ionenimplantation erreicht werden. - Anschließend an die Dotierung des Substrats wird eine epitaktische Schicht, die als eine monokristalline Siliziumschicht
12 gezeigt ist, auf der Deckfläche des Substrats10 ausgebildet. Die Ablagerung der epitaktischen Siliziumschicht12 wird beispielsweise mittels einer auf Dichlorsilan basierenden Chemie in einer Ein-Wafer-CVD-Anlage, wie etwa der ASM E3000 Anlage, durchgeführt. Der Film wird mit einer Gasströmung von 140–250 sccm von Dichlorsilan (SiH2Cl2), 100–150 sccm HCl, 20 slm von H2 bei 825°C und einem Prozeßdruck von 20 Torr abgelagert. Unter diesen Verarbeitungsbedingungen wird eine Ablagerungsrate von 10–15 nm/Min für Silizium auf dem ausgesetzten Substrat erreicht, während eine hervorragende Selektivität für Abstandhalter- und Oxidregionen erreicht wird. Die Schicht12 kann eine Dicke von ungefähr 85 nm aufweisen, und ihre Dotiermittelkonzentration wird beispielsweise weniger als 1/100 der Spitzen-Konzentration des vergrabenen Dotiermittels des Substrats betragen. - Anschließend an die Ausbildung der Schicht
12 wird eine Isolierschicht13 auf der Schicht10 ausgebildet. Die Schicht13 kann aus einer dünnen, thermisch gewachsenen Oxidschicht oder einer abgelagerten Siliziumdioxidschicht bestehen. Daraufhin wird eine Polysiliziumschicht14 auf der Isolierschicht13 abgelagert. Wie man sehen wird, sind die Gates, die aus der Schicht14 gebildet werden, Opfergates. Sie werden nachfolgend entfernt, und Metall wird für die Bereiche, die von diesen Polysiliziumgates besetzt waren, substituiert. Eine Hartmaske15 wird auf der Polysiliziumschicht14 ausgebildet. - Weiter wird, wie in
4 gezeigt ist, eine Gate-Opferstruktur gefertigt, indem die Hartmaskenschicht15 zuerst mittels gewöhnlicher photolithographischer Verfahren maskiert und geätzt wird, um Maskenelemente für die Gates zu definieren. Nun werden die Polysiliziumschicht14 und die Isolierschicht13 mittels gewöhnlicher Ätzmittel in Abgleich mit der Hartmaske15 geätzt. Die resultierende Struktur ist in4 abgebildet. - Wie in
5 gezeigt ist, werden dann Seitenwände16 auf dem Gate von4 ausgebildet. Relativ dünne Siliziumnitrid-Seitenwandelemente16 können mittels gewöhnlicher Seitenwandverarbeitung ausgebildet werden. Der Zweck dieser Seitenwand-Abstandhalter liegt darin, das Polysilizium während der nachfolgenden Verarbeitung zu schützen. Daher werden alle Seiten des Polysiliziumgates14 bedeckt. Da die Seitenwand-Abstandhalter zum Schutz des Polysiliziums verwendet werden, können sie relativ dünn sein. - Nun wird die Schicht
12 geätzt, um einen Kanalkörper12a auszubilden. Das Ätzen unterschneidet die Gatestruktur, wie in6 durch die Unterschneidung20 gezeigt ist. - Die Schicht
12 kann mit einer Vielzahl von auf hydroxidbasierten Lösungen geätzt werden. Zum Zweck einer hohen Selektivität für das stark dotierte Substrat werden jedoch relativ milde Verarbeitungsbedingungen und ein Naßätzmittel verwendet. Ein Verfahren ist eine Behandlung mit einer wäßrigen Ammoniumhydroxidlösung im Konzentrationsbereich von 2–10% im Volumen bei 25 Grad Celsius mit einem Ultraschallwandler, der Ultra- oder Megaschall-Energie bei einer Leistung von 0,5 bis 5 W/cm2 abstrahlt. - Eine Source- und eine Drainregion werden dann aufgewachsen, um eine flache, stark dotierte Source-/Drainspitze (Erweiterung) herzustellen, die sich über die Entfernung von unter dem Gaterand zum Kanalkörper
12a erstreckt. Eine getrennte Verarbeitung wird für die p-Kanal- und die n-Kanal-Transistoren verwendet, wobei jeweils die Source- und die Drainregionen in unterschiedlichen Verarbeitungsschritten gewachsen werden, beide mit Vor-Ort-Dotierung. Dies führt dazu, daß die Source- und die Drainregionen stark dotiert sind, in einem Fall mit einem Dotiermittel vom p-Typ, im anderen Fall mit einem Dotiermittel vom n-Typ. - Beim Ausbilden eines PMOS-Transistors sind die Source- bzw. die Drainerweiterung (Spitze) erhöhte Source-/Drainregionen, die durch selektives Ablagern von epitaktischem Bor(B)-dotierten Silizium oder von SiGe mit Germanium-Konzentrationen von bis zu 30% ausgebildet werden. Unter den Verarbeitungsbedingungen von 100 sccm von Dichlorsilan (DCS), 20 slm H2, 750–800°C, 20 Torr, 150–200 sccm HCl, einem Diboran-Fluß (B2H6) von 150–200 sccm und einem GeH4-Fluß von 150–200 sccm wird ein stark dotierter SiGe-Film mit einer Ablagerungsrate von 20 nm/Min, einer B-Konzentration von 1E20 cm–3 und einer Germanium-Konzentration von 20% erreicht. Ein niedriger spezifischer Widerstand von 0,7–0,9 mOhm-cm, der aus der hohen B-Konzentration in dem Film herrührt, stellt den Vorteil von hoher Leitfähigkeit in den Source-/Drainspitzen-Regionen bereit und verringert dadurch Rextern. Das SiGe in den Source-/Drainregionen übt ein Stauchwirkung auf den Kanal aus, was wiederum zu verbesserter Mobilität und verbesserter Transistorleistung führt.
- Bei einem NMOS-Transistor werden die Source-/Drainregionen mittels vor Ort mit Phosphor dotiertem Silizium ausgebildet, das selektiv unter Verarbeitungsbedingungen von 100 sccm von DCS, 25–50 sccm HCl, 200–300 sccm von 1%-Ph3 mit einer H2-Trägergasströmung von 20 slm bei 750°C und 20 Torr abgelagert wird. Eine Phosphorkonzentration von 2E20 cm–3 mit einem spezifischen Widerstand von 0,4–0,6 mOhm-cm wird in dem abgelagerten Film erreicht.
- Nachdem die Source-/Drainregionen wie in
7 gezeigt ausgebildet sind, werden mittels gewöhnlicher Verarbeitung zusätzliche Abstandhalter24 ausgebildet. Als Beispiel können die Abstandhalter ein Siliziumnitrid- oder Siliziumdioxid-Abstandhalter sein. Die Abstandhalter24 sind relativ dick verglichen mit der Dicke der Abstandhalter16 , wie in8 gezeigt ist. - Nun erfolgt eine Ionenimplantation, um die Source/Drainregionen
26 in dem Substrat10 auszubilden. Wieder werden getrennte Ionenimplantationsverfahren für das Dotiermittel vom p-Typ und das Dotiermittel vom n-Typ verwendet. Die Regionen26 können auf einen Pegel von 1020 Atomen/cm3 implantiert werden. - Wie in
9 gezeigt ist, wird ein gewöhnliches Silizid- oder Salicide-Verfahren („self-aligned silicide", Salicide) verwendet, um die Salicide-Schicht28 auszubilden, und dadurch die Deckfläche der Source-/Drainregionen leitfähiger zu machen. - In der
10 wird ein n-Kanal-Transistor neben einem p-Kanal-Transistor abgebildet. Die Kanalregionen werden unter12b für den n-Kanal-Transistor und unter12c für den p-Kanal-Transistor gezeigt. Der Buchstabe „b" wird unten verwendet, um die Schichten und Bereiche für den n-Kanal-Transistor zu bezeichnen, und analog wird der Buchstabe „c" verwendet, um die Schichten und Bereiche für den p-Kanal-Transistor zu bezeichnen. Die in10 gezeigte Struktur ist identisch mit der in9 gezeigten, außer daß ein ILD30 über dem Wafer ausgebildet ist. Jedes einer Mehrzahl von Dielektrika kann für das ILD verwendet werden, wie etwa Siliziumdioxid, kohlenstoffdotiertes Siliziumdioxid oder andere Low-k-Dielektrika. - Nun wird CMP verwendet, um eine planarisierte Oberfläche bereitzustellen, und um das Salicide von der Oberseite der Gates
14b und14c zu entfernen. Die resultierende Struktur ist in11 dargestellt. - Weiter wird eine Photoresistschicht
32 über den p-Kanal-Transistoren ausgebildet, und ein Naßätzmittel wird verwendet, um das Polysilizium von den n-Kanal-Transistoren zu entfernen. Die darunter liegende Isolierschicht wird ebenfalls entfernt, was die in12 dargestellte Öffnung34 ausbildet. - Nun wird, wie in
13 gezeigt ist, eine Isolierschicht37b zusammen mit einer Metallschicht38 ausgebildet, die als „n-Metall" bezeichnet wird, da sie das Metall ist, das die geeignete Austrittsarbeit für die n-Kanal-Transistoren aufweist. Das Gatedielektrikum weist im Idealfall eine hohe Dielektrizitätskonstante auf, wie etwa ein Metalloxid-Dielektrikum, zum Beispiel HfO2, ZrO2 oder andere High-k-Dielektrika, wie etwa PZT oder BST. Ein Film aus einem High-k-Dielektrikum kann durch irgendeine bekannte Technik, wie etwa durch chemische Gasphasenabscheidung (CVD), ausgebildet werden. Die Gateelektrodenschicht38 kann durch unstrukturiertes Ablagern eines geeigneten Gateelektrodenmaterials ausgebildet werden. In einer Ausführung umfaßt ein Gateelektrodenmaterial einen Metallfilm, wie etwa Wolfram, Tantal und/oder Nitride und Legierungen daraus. Für die n-Kanal-Transistoren kann eine Austrittsarbeit im Bereich von 4,0 bis 4,6 eV verwendet werden. - Daraufhin wird CMP verwendet, um die Oberfläche zu planarisieren, wobei die Metallschicht
38 , außerhalb des Bereichs, der vorher vom Polysiliziumgate ausgefüllt war, entfernt wird. Das resultierende Gate38b und die darunter liegende Isolierschicht37b sind in14 dargestellt. - Ein Naßätzmittel wird verwendet, um das Polysiliziumgate, das zum p-Kanal-Transistor gehört, zu entfernen. Wieder wird die darunter liegende Isolierschicht ebenfalls entfernt, so daß eine geeignetere Isolierschicht ausgebildet werden kann. Die Öffnungen
42 der15 entsteht, nachdem das Polysiliziumgate und die darunter liegende Isolierschicht entfernt worden sind. Ein Gatedielektrikum37c wird auf dem freigelegten Silizium ausgebildet. Das Dielektrikum kann das selbe sein, wie das Dielektrikum37b . - Eine Metallschicht
44 wird über der Struktur von15 und dem Gatedielektrikum37b ausgebildet. Dies wird als ein „p-Metall" in16 gezeigt, da die Austrittsarbeit dieses Metalls für p-Kanal-Transistoren geeignet ist. Das p-Metall kann aus der gleichen Zusammensetzung sein wie das n-Metall, außer daß die Austrittsarbeit vorzugsweise zwischen 4,6 und 5,2 eV liegt. - Nach dem Ablagern des p-Metalls wird CMP verwendet, um die Struktur zu planarisieren, wobei die resultierende Struktur in
17 gezeigt ist. Es entsteht ein n-Kanal-Transistor mit einem Gate37b und einer Kanalregion12b , und analog entsteht ein p-Kanal-Transistor mit einem Gate44c und einer Kanalregion12c . - Es gibt mehrere Vorteile der Transistoren von
17 und ihrer Herstellung, verglichen mit Transistoren vom Stand der Technik. Erstens sind flache Tiefen der Spitzen-(Erweiterungs-)Übergänge erstrebenswert, um kleinere Transistorabmessungen unterstützen zu helfen. Wenn herkömmliche Techniken mit implantierten Spitzen verwendet werden, sind die minimalen Tiefen der Spitzen-Übergänge durch die notwendige Gateüberlappung beschränkt. Mit der Struktur von17 und der beschriebenen Verarbeitungsverfahren können die Abmessung der Gateüberlappung und die Übergangstiefe besser gesteuert werden. Die Naßätzung kann beispielsweise zeitlich gesteuert werden, um das Ausmaß des Unterschneidens unter der Gatestruktur zu bestimmen. - Flache Tiefen der Spitzen-Übergänge ermöglichen eine Herstellung von kürzeren Gatelängen ohne den Sperrstrom zu erhöhen. Dotierung der Spitzen unter dem Gaterand ist notwendig, um einen niederohmigen Pfad zwischen der Inversionsschicht unter dem Gate und der stark dotierten Source/Drain-Spitzenregion sicherzustellen. Der niedrige Widerstand erlaubt höhere Treiberströme, die für die Schaltgeschwindigkeit der Schaltung entscheidend sind.
- Ein Vorteil des Metallgates liegt darin, daß die Verarbeitung bei niedrigeren Temperaturen erfolgen kann. Dies gilt zusätzlich zu der besseren Leistung, die mit dem Metallgate erzielt wird, verglichen mit einem Polysiliziumgate. In dem oben beschriebenen Verarbeitungsverfahren werden niedrigere Temperaturoptionen verwendet, um die thermische Gesamtbelastung zu verringern. Dies verhindert, wie vorher erwähnt, daß das Dotiermittel aus dem Substrat in die Kanalregion diffundiert.
- Somit wurden ein Delta-dotierter Transistor mit einem Metallgate und ein Herstellungsverfahren beschrieben.
Claims (20)
- Verfahren zur Fertigung von Halbleitertransistoren, welches folgendes umfaßt: Wachsen einer undotierten oder leicht dotierten Siliziumschicht auf einem stark dotierten Substrat; Ausbilden von Polysilizium-Opfergates auf der Siliziumschicht; Ätzen der Siliziumschicht und Unterschneiden der Gatestrukturen, um Siliziumkörper unter den Gatestrukturen auszubilden; Wachsen von Source- und Drainregionen, die sich in die Unterschneidungen angrenzend an die Siliziumkörper erstrecken; Entfernen der Polysiliziumgates; und Ausbilden von Metallgates an Stelle der Polysiliziumgates.
- Verfahren nach Anspruch 1, wobei die Verarbeitung bei ausreichend niedrigen Temperaturen ausgeführt wird, um zu verhindern, daß Dotierungsmittel aus dem Substrat die Siliziumschicht oder die Siliziumkörper wesentlich dotieren.
- Verfahren nach Anspruch 1, wobei das Ätzen der Siliziumschicht mit einem Naßätzmittel durchgeführt wird, welches zwischen der Siliziumschicht und dem Siliziumsubstrat diskriminiert.
- Verfahren nach Anspruch 2, wobei die Source- und Drainregionen selektiv gewachsene Regionen aus Silizium oder Silizium-Germanium sind.
- Verfahren nach Anspruch 4, wobei die Source- und Drainregionen stark dotierte Regionen sind.
- Verfahren nach Anspruch 1, wobei: erste Source- und Drainregionen selektiv gewachsen und stark mit einem n-Typ-Dotiermittel dotiert werden, und zweite Source- und Drainregionen selektiv gewachsen und stark mit einem p-Typ-Dotiermittel dotiert werden.
- Verfahren nach Anspruch 6, wobei: erste Metallgates über den ersten Source- und Drainregionen ausgebildet werden, welche eine Austrittsarbeit zwischen 4,0 und 4,6 eV aufweisen; und zweite Metallgates über den zweiten Source- und Drainregionen ausgebildet werden, welche eine Austrittsarbeit zwischen 4,6 und 5,2 eV aufweisen.
- Verfahren nach Anspruch 6, wobei das Ausbilden der Metallgates folgendes umfaßt: Entfernen der Polysiliziumgates über den ersten Source- und Drainregionen; Ablagern eines ersten Metalls; Abpolieren des ersten Metalls über den zweiten Source- und Drainregionen; Entfernen der Polysiliziumgates über den zweiten Source- und Drainregionen; Ablagern eines zweiten Metalls; Abpolieren des zweiten Metalls über den ersten Source- und Drainregionen.
- Verfahren nach Anspruch 8, wobei das erste Metall eine Austrittsarbeit zwischen 4,0 und 4,6 eV aufweist, und das zweite Metall eine Austrittsarbeit zwischen 4,6 und 5,2 eV aufweist.
- Verfahren nach Anspruch 1, wobei die Halbleitertransistoren komplementäre MOS-Transistoren, die Siliziumschicht eine monokristalline Schicht und das Substrat ein monokristallines Substrat ist, wobei das Ätzen der Siliziumschicht und Unterschneiden der Gatestrukturen Kanalregionen für die Transistoren ausbildet; das Wachsen von Source- und Drainregionen ein Wachsen von ersten und zweiten monokristallinen Source- und Drainregionen, die mit einem n-Typ- und einem p-Typ-Dotiermittel dotiert sind, welche sich jeweils auf gegenüberliegenden Seiten der Kanalregionen von unterhalb der Gatestrukturen erstrecken, umfaßt; und das Entfernen der Polysiliziumgates und Ausbilden von Metallgates ein Ersetzen der Gatestrukturen mit einem ersten Metall und einem zweiten Metall für die ersten bzw. zweiten Source- und Drainregionen umfaßt.
- Verfahren nach Anspruch 10, wobei erste Seiten-Abstandhalter auf den Gatestrukturen ausgebildet werden, bevor die Schicht geätzt wird.
- Verfahren nach Anspruch 11, wobei zweite Seiten-Abstandhalter auf den ersten Abstandhaltern ausgebildet werden, nachdem die ersten und zweiten Source- und Drainregionen ausgebildet sind.
- Verfahren nach Anspruch 12, welches das Dotieren der ersten und zweiten Source- und Drainregionen und des Substrats in Ausrichtung zu den zweiten Abstandhaltern umfaßt.
- Verfahren nach Anspruch 10, wobei das erste Metall eine Austrittsarbeit zwischen 4,0 und 4,6 eV aufweist, und das zweite Metall eine Austrittsarbeit zwischen 4,6 und 5,2 eV aufweist.
- MOS-Transistor, welcher folgendes umfaßt: ein stark dotiertes Substrat; eine undotierte oder leicht dotierte Kanalregion, die auf dem Substrat angeordnet ist; erhöhte, monokristalline Source- und Drainregionen, welche auf dem Substrat angeordnet sind, die sich auf gegenüberliegenden Seiten der Kanalregion erstrecken, und ein Metallgate, das über der Kanalregion und über zumindest einem Teil der Source- und der Drainregion angeordnet und von diesen isoliert ist.
- Transistor nach Anspruch 15, welcher erste Seitenwand-Abstandhalter umfaßt, die um das Metallgate herum angeordnet sind.
- Transistor nach Anspruch 15, welcher eine Silizidschicht auf Teilen der Source- und der Drainregion, die sich bis jenseits des Metallgates und der ersten Seitenwand-Abstandhalter erstrecken, umfaßt.
- Transistor nach Anspruch 15, welcher Source- und Drain-Diffusionen umfaßt, die sich in das Substrat erstrecken.
- Transistor nach Anspruch 15, wobei die Source- und die Drainregion Silizium oder Silizium-Germanium umfassen.
- Transistor nach Anspruch 15, wobei das Substrat eine Spitzen-Dotierungskonzentration von 1019 Atome/cm3 oder mehr aufweist.
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US10/955,669 US7332439B2 (en) | 2004-09-29 | 2004-09-29 | Metal gate transistors with epitaxial source and drain regions |
US10/955,669 | 2004-09-29 | ||
PCT/US2005/035377 WO2006039597A2 (en) | 2004-09-29 | 2005-09-29 | Metal gate transistors with epitaxial source and drain regions |
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DE112005002302T Active DE112005002302B4 (de) | 2004-09-29 | 2005-09-29 | Verfahren zur Herstellung von Metallgate-Transistoren mit epitaktischen Source- und Drainregionen und MOS-Transistor |
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US (5) | US7332439B2 (de) |
KR (1) | KR100867781B1 (de) |
CN (2) | CN101027763A (de) |
DE (1) | DE112005002302B4 (de) |
TW (1) | TWI272681B (de) |
WO (1) | WO2006039597A2 (de) |
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2004
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- 2005-09-29 TW TW094133997A patent/TWI272681B/zh not_active IP Right Cessation
- 2005-09-29 WO PCT/US2005/035377 patent/WO2006039597A2/en active Application Filing
- 2005-09-29 CN CNA2005800324531A patent/CN101027763A/zh active Pending
- 2005-09-29 CN CN201310419494.2A patent/CN103560150B/zh not_active Expired - Fee Related
- 2005-09-29 KR KR1020077007071A patent/KR100867781B1/ko active IP Right Grant
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US7332439B2 (en) | 2008-02-19 |
US20060068590A1 (en) | 2006-03-30 |
US20080142840A1 (en) | 2008-06-19 |
CN103560150A (zh) | 2014-02-05 |
TW200618125A (en) | 2006-06-01 |
WO2006039597A3 (en) | 2006-07-13 |
DE112005002302T5 (de) | 2007-09-27 |
KR20070052329A (ko) | 2007-05-21 |
US20160308014A1 (en) | 2016-10-20 |
CN101027763A (zh) | 2007-08-29 |
US20110156145A1 (en) | 2011-06-30 |
TWI272681B (en) | 2007-02-01 |
KR100867781B1 (ko) | 2008-11-10 |
US20060068591A1 (en) | 2006-03-30 |
WO2006039597A2 (en) | 2006-04-13 |
CN103560150B (zh) | 2017-01-11 |
US8344452B2 (en) | 2013-01-01 |
US7915167B2 (en) | 2011-03-29 |
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