CN103578987B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103578987B
CN103578987B CN201210250438.6A CN201210250438A CN103578987B CN 103578987 B CN103578987 B CN 103578987B CN 201210250438 A CN201210250438 A CN 201210250438A CN 103578987 B CN103578987 B CN 103578987B
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epitaxial layer
layer
sacrificial gate
semiconductor device
stacking
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CN103578987A (zh
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尹海洲
蒋葳
朱慧珑
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Institute of Microelectronics of CAS
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Priority to US14/354,648 priority patent/US9147762B2/en
Priority to PCT/CN2012/079401 priority patent/WO2014012275A1/zh
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Abstract

本申请公开了一种半导体器件及其制造方法。一示例方法包括：在衬底上生长第一外延层；在第一外延层上生长第二外延层；在第二外延层上形成牺牲栅堆叠；以牺牲栅堆叠为掩模，选择性刻蚀第二外延层；在第一外延层上生长并原位掺杂第三外延层；在牺牲栅堆叠两侧形成侧墙；以侧墙为掩模，选择性刻蚀第三外延层和第一外延层；以及在衬底上生长并原位掺杂第四外延层，以形成源/漏区。

Description

半导体器件及其制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种半导体器件及其制造方法。
背景技术
随着器件尺寸日益缩小，短沟道效应越来越明显。为抑制短沟道效应，一种手段是减小源/漏延伸区的结深。为形成浅的延伸区，需要在进行延伸区注入时采用低能离子进行注入，且随后进行超快速退火来激活注入离子。这对生产设备和生产工艺提出了挑战。
另一方面，离子注入可能导致衬底损伤。从而需要额外的退火处理来消除损伤。
发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上生长第一外延层；在第一外延层上生长第二外延层；在第二外延层上形成牺牲栅堆叠；以牺牲栅堆叠为掩模，选择性刻蚀第二外延层；在第一外延层上生长并原位掺杂第三外延层；在牺牲栅堆叠两侧形成侧墙；以侧墙为掩模，选择性刻蚀第三外延层和第一外延层；以及在衬底上生长并原位掺杂第四外延层，以形成源/漏区。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底；在衬底上生长的第一外延层；在第一外延层上生长的第二外延层，其中第二外延层的横向端部相对于第一外延层的相应横向端部凹入；在第一外延层上生长且与第二外延层邻接的第三外延层，其中第三外延层被原位掺杂且因此被配置成源/漏延伸区；在第二外延层上形成的栅堆叠；以及在衬底上生长且与第一和第三外延层邻接的第四外延层，其中第四外延层被原位掺杂且因此被配置成源/漏区。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-6是示出了根据本公开实施例的制造半导体器件流程的示意图；以及
图7-14是示出了根据本公开另一实施例的制造半导体器件流程的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
以下，参照图1-6，描述根据本公开的一实施例。
如图1所示，提供衬底1000。衬底1000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1000上，例如通过外延，生长外延层1004。外延层1004例如可以包括SiGe(Ge的原子百分比例如为约10％)，厚度可以为约5-10nm。该外延层1004的厚度将大体上确定随后形成的源/漏延伸区的厚度。
随后，如图2所示，在外延层1004上，形成牺牲栅堆叠。例如，可以通过淀积依次形成氧化物层1006和氮化物层1008，且随后进行构图，以形成牺牲栅堆叠。需要指出的是，本领域技术人员知道多种方式来形成牺牲栅堆叠。图2中所示的氧化物层1006和氮化物层1008的牺牲栅堆叠结构仅仅是示例。根据本公开的实施例，为了便于后继处理，牺牲栅堆叠优选地不包括晶体半导体材料(如，多晶硅)，而是包括电介质材料例如氮化物、氧化物或其组合，这是为了在后续处理中需要进行选择性外延生长时避免在牺牲栅堆叠上进行生长。
接下来，如图3所示，可以对外延层1004进行选择性刻蚀。这种选择性刻蚀例如可以通过湿法刻蚀、干法刻蚀或其组合来进行。由于外延层1004(例如，SiGe)和衬底1000(例如，Si)之间的刻蚀选择性，刻蚀可以停止于衬底1000。由于牺牲栅堆叠的存在，外延层1004位于牺牲栅堆叠下方的部分得以保留。在图3所示的示例中，示出了外延层1004的横向边缘相对于牺牲栅堆叠的横向边缘略为凹进，凹进距离可以通过控制刻蚀工艺中的工艺条件来控制。
然后，如图4所示，在由于上述选择性刻蚀而露出的衬底1000上例如通过外延，生长外延层1010。外延层1010例如包括Si。由于牺牲栅堆叠包括电介质材料如氧化物和氮化物，因此外延生长不会在牺牲栅堆叠表面发生。在生长外延层1010的过程中，可以通过原位掺杂，将外延层1010掺杂为相应的导电类型。例如，对于n型器件，可以通过掺杂n型杂质如As或P，将外延层1010掺杂为n型；对于p型器件，可以通过掺杂p型杂质如In、BF2或B，将外延层1010掺杂为p型。这种原位掺杂的外延层1010随后用来形成最终器件的延伸区。
接下来，如图5所示，在牺牲栅堆叠两侧形成侧墙1012。侧墙1012例如可以包括氮化硅、氧化硅或其组合。本领域技术人员知道多种方式来形成侧墙，在此不再赘述。
随后，如图6所示，可以以侧墙为掩模，来形成源/漏区1014。例如，可以通过离子注入，来形成源/漏区1014。具体地，对于n型器件，可以注入n型杂质如As或P；对于p型器件，可以注入p型杂质。离子注入之后，例如可以通过退火，来激活注入的离子。
之后，可以进行替代栅工艺。具体地，可以通过选择性刻蚀，去除牺牲栅堆叠(在该示例中，去除氮化物层1008和氧化物层1006)，从而在侧墙之间形成空隙。然后，可以通过在空隙中填充栅介质和栅导体，来形成最终的栅堆叠。栅介质例如可以包括高K栅介质，栅导体例如可以包括金属栅导体。
这样，就得到了根据本公开一示例的半导体器件。如图6所示，该半导体器件包括在半导体衬底上形成的、通过原位掺杂的外延层1010。该外延层1010(更具体来说，其靠近沟道区的部分)构成该半导体器件的源/漏延伸区1016。由于外延层1010的形成工艺，其厚度主要由外延层1004的厚度决定，也就是说，外延层1004的厚度基本上确定了延伸区1016的深度。由于可以比较精确地控制在衬底上生长的外延层1004的厚度较薄，从而可以控制形成较浅的延伸区1016。另外，在形成延伸区1016的过程中，对其原位掺杂，从而避免了进行离子注入，并因此避免了需要对其进行的超快速退火。
以下，参照图7-14，描述根据本公开的另一实施例。
如图7所示，提供衬底2000。衬底2000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1000上，例如通过外延，生长外延层2002。外延层2002例如可以包括SiGe(Ge的原子百分比例如为约10％)，厚度可以为约30-50nm。该外延层2002的厚度将大体上确定随后形成的源/漏区的厚度。
另外，在外延层2002上，例如通过外延，生长另一外延层2004。外延层2004例如可以包括Si，厚度可以为约5-10nm。该外延层2004的厚度将大体上确定随后形成的源/漏延伸区的厚度。
随后，如图8所示，在外延层2004上，形成牺牲栅堆叠。例如，可以通过淀积依次形成氧化物层2006和氮化物层2008，且随后进行构图，以形成牺牲栅堆叠。关于牺牲栅堆叠，可以参见以上结合图2的说明。
接下来，如图9所示，可以对外延层2004进行选择性刻蚀。这种选择性刻蚀例如可以通过湿法刻蚀、干法刻蚀或其组合来进行。由于外延层2004(例如，Si)和外延层2002(例如，SiGe)之间的刻蚀选择性，刻蚀可以停止于外延层2002。由于牺牲栅堆叠的存在，外延层2004位于牺牲栅堆叠下方的部分得以保留。在图9所示的示例中，示出了外延层2004的横向边缘相对于牺牲栅堆叠的横向边缘略为凹进，凹进距离可以通过控制刻蚀工艺中的工艺条件来控制。
然后，如图10所示，在由于上述选择性刻蚀而露出的外延层2002上例如通过外延，生长外延层2010。外延层2010例如可以包括Si。由于牺牲栅堆叠包括电介质材料如氧化物和氮化物，因此外延生长不会在牺牲栅堆叠表面发生。在生长外延层2010的过程中，可以通过原位掺杂，将外延层2010掺杂为相应的导电类型。例如，对于n型器件，可以通过掺杂n型杂质如As或P，将外延层2010掺杂为n型；对于p型器件，可以通过掺杂p型杂质如In、BF2或B，将外延层2010掺杂为p型。这种原位掺杂的外延层2010随后用来形成最终器件的延伸区。
接下来，如图11所示，在牺牲栅堆叠两侧形成侧墙2012。侧墙2012例如可以包括氮化硅、氧化硅或其组合。本领域技术人员知道多种方式来形成侧墙，在此不再赘述。
随后，如图12所示，可以以侧墙为掩模，依次选择性刻蚀外延层2010和外延层2002。这种选择性刻蚀例如可以通过湿法刻蚀、干法刻蚀或其组合来进行。由于牺牲栅堆叠和侧墙的存在，外延层2010和外延层2002位于它们之下的部分得以保留。
然后，如图13所示，在由于上述选择性刻蚀而露出的衬底2000上例如通过外延，生长外延层2014。外延层2014例如包括Si。由于牺牲栅堆叠包括电介质材料如氧化物和氮化物，因此外延生长不会在牺牲栅堆叠表面发生。在生长外延层2014的过程中，可以通过原位掺杂，将外延层2014掺杂为相应的导电类型。例如，对于n型器件，可以通过掺杂n型杂质如As或P，将外延层2014掺杂为n型；对于p型器件，可以通过掺杂p型杂质如In、BF2或B，将外延层2014掺杂为p型。这种原位掺杂的外延层2014随后用来形成最终器件的源/漏区。此外，原位掺杂的外延层2010的剩余部分随后用来形成器件的源/漏延伸区2016。
根据本公开的一示例，为了增强器件性能，外延层2014还可以包括SiGe(对于p型器件，Ge原子百分比例如高于30％)或Si：C(对于n型器件)。这种外延层2014可以向器件的沟道区施加应力，从而增强载流子迁移率，并因此改善器件性能。
之后，可以进行替代栅工艺。具体地，可以通过选择性刻蚀，去除牺牲栅堆叠(在该示例中，去除氮化物层1008和氧化物层1006)，从而在侧墙之间形成空隙。然后，可以通过在空隙中填充栅介质2018和栅导体2020，来形成最终的栅堆叠。栅介质2018例如可以包括高K栅介质，栅导体2020例如可以包括金属栅导体。在栅介质2018和栅导体2020之间还可以形成功函数调节层(未示出)。然后，例如通过淀积，形成层间电介质层2022(例如，氧化物)，并进行CMP，得到如图14所示的半导体器件。
如图14所示，该半导体器件包括在衬底上形成的栅堆叠(栅介质层2018和栅导体层2020)。原位掺杂的外延层2010构成该半导体器件的源/漏延伸区2016。同上述实施例中一样，如此形成的延伸区2016可以控制为较浅，而且避免了离子注入工艺。
此外，该半导体器件还包括由外延层2014形成的源/漏区。同样，由于在源/漏区的形成过程中进行原位掺杂，避免了进行离子注入，并因此避免了相应的退火工艺。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (9)

1.一种制造半导体器件的方法，包括：
在衬底上生长第一外延层；
在第一外延层上生长第二外延层；
在第二外延层上形成牺牲栅堆叠；
以牺牲栅堆叠为掩模，选择性刻蚀第二外延层；
在第一外延层上生长并原位掺杂第三外延层；
在牺牲栅堆叠两侧形成侧墙；
以侧墙为掩模，选择性刻蚀第三外延层和第一外延层；以及
在衬底上生长并原位掺杂第四外延层，以形成源/漏区。
2.根据权利要求1所述的方法，其中，在形成源/漏区之后，该方法还包括：
去除牺牲栅堆叠，在侧墙之间形成空隙；以及
在空隙中依次形成栅介质层和栅导体层。
3.根据权利要求1所述的方法，其中，衬底包括Si，第一外延层SiGe，第二外延层包括Si，第三外延层包括Si，第四外延层包括Si、SiGe或Si：C。
4.根据权利要求1所述的方法，其中，牺牲栅堆叠包括电介质材料。
5.一种半导体器件，包括：
衬底；
在衬底上生长的第一外延层；
在第一外延层上生长的第二外延层，其中第二外延层的横向端部相对于第一外延层的相应横向端部凹入；
在第一外延层上生长且与第二外延层邻接的第三外延层，其中第三外延层被原位掺杂且因此被配置成源/漏延伸区；
在第二外延层上形成的栅堆叠；以及
在衬底上生长且与第一和第三外延层邻接的第四外延层，其中第四外延层被原位掺杂且因此被配置成源/漏区。
6.根据权利要求5所述的半导体器件，其中，第二外延层的厚度与第三外延层的厚度相同。
7.根据权利要求5所述的半导体器件，其中，第二外延层的横向端部相对于栅堆叠的相应横向边缘凹入，从而第三外延层延伸至栅堆叠下方。
8.根据权利要求5所述的半导体器件，其中，第三外延层远离第二外延层的横向端部与第一外延层的相应横向端部齐平。
9.根据权利要求8所述的半导体器件，还包括形成在栅堆叠两侧的侧墙，其中第一和第三外延层的横向端部由侧墙限定。
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