CN103578944B - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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CN103578944B
CN103578944B CN201210249429.5A CN201210249429A CN103578944B CN 103578944 B CN103578944 B CN 103578944B CN 201210249429 A CN201210249429 A CN 201210249429A CN 103578944 B CN103578944 B CN 103578944B
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刘云飞
尹海洲
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Abstract

本申请公开了一种制造半导体器件的方法。一示例方法可以包括：在衬底上形成栅堆叠，栅堆叠包括栅介质层和栅导体层；选择性刻蚀栅介质层的端部，从而形成空隙；以及在空隙中填充栅介质层的材料。

Description

半导体器件制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种制造半导体器件的方法。
背景技术
在半导体工艺中，经常会进行倾斜离子注入。例如，在使用离子注入工艺形成CMOS器件源漏区的过程中，为了避免隧道效应而形成浅结，通常沿一定倾斜角度进行离子注入。另外，在短沟道器件的制作中，为了控制短沟道效应，通常采用大倾斜角度进行晕圈(halo)注入。
然而，倾斜离子注入会使注入离子穿过栅介质层，从而造成栅介质层的损伤，使得器件由于栅漏电流急剧增加而失效。特别当高能量、大剂量注入大型杂质离子如P、Ge、As离子等时，这一问题更加突出。
常规解决方案是在离子注入工艺之前在栅堆叠侧壁上淀积一层电介质侧墙(例如，氧化硅或氮化硅)，以减弱注入离子对栅介质层的损伤效果。然而，这种方法并不能完全消除栅介质层的损伤，从而使器件性能在一定程度上被降低。
发明内容
本公开的目的至少部分地在于提供一种制造半导体器件的方法。
根据本公开的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上形成栅堆叠，栅堆叠包括栅介质层和栅导体层；选择性刻蚀栅介质层的端部，从而形成空隙；以及在空隙中填充栅介质层的材料。
通过选择性刻蚀栅介质层的端部然后再回填，对栅介质层进行处理，使得可以去除栅介质层端部可能存在的缺陷，例如由于倾斜离子注入而导致的缺陷。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-3是示出了根据本公开实施例的制造半导体器件流程的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
如图1所示，提供衬底100。衬底100可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底100上，可以形成栅堆叠。栅堆叠可以包括栅介质层102和栅导体层104。栅介质层102可以包括电介质层如氧化硅，或者可以包括高K栅介质。栅导体层104可以包括多晶硅，或者金属栅导体。在栅介质层102包括高K栅介质、栅导体层104包括金属栅导体的情况下，还可以存在功函数调节层(未示出)夹于栅介质层102和栅导体层104之间。然后，可以栅堆叠为掩模，例如通过离子注入，形成源/漏区106。
在进行源/漏注入之前，如图1中的箭头所示，还可以进行倾斜离子注入，以便形成例如晕圈(halo)结构108或轻掺杂漏(LDD)。在倾斜离子注入过程中，注入离子可能会穿过栅介质层102，特别是栅介质层102的端部，从而在栅介质层102中造成损伤110。
接下来，如图2所示，可以通过选择性刻蚀，去除栅介质层102的端部，特别是包含损伤110的区域。例如，这种选择性刻蚀可以通过湿法刻蚀、干法刻蚀或其组合来进行。例如，可以将图1所示的结构浸入刻蚀溶液中。刻蚀溶液例如可以包括按约100∶1稀释的HF溶液。在刻蚀过程中，可以通过控制刻蚀时间，来特别去除栅介质层102端部受倾斜离子注入影响的区域(包含损伤110)。
根据本公开的实施例，刻蚀时间例如可以根据栅介质的刻蚀速率以及栅介质需要刻蚀的量来确定。栅介质的刻蚀速率取决于多种因素，例如栅介质本身的材质、刻蚀方案以及环境温度等。栅介质需要刻蚀的量例如取决于离子注入的倾斜角度、注入能量和注入剂量等。
然后，如图3所示，可以通过在栅介质层102的端部(由于上述选择性刻蚀而存在空隙)填充栅介质层的材料(例如，氧化硅)，来获得基本上无损伤的栅介质层102′。这种填充例如可以通过在衬底100上淀积一层厚的栅介质材料层，并进行回蚀来完成。这种淀积例如可以包括低压化学气相淀积(LPCVD)或者原子层淀积(ALD)。根据本公开的一示例，在回蚀过程中，例如通过控制刻蚀工艺的参数，保留栅介质层材料位于栅堆叠侧壁上的部分，从而形成栅堆叠的第一侧墙。本领域技术人员知道这种通过回蚀形成侧墙的工艺，在此不再赘述。
这样，就获得了最终的器件。如图3所述，该器件可以包括衬底100和在衬底100上形成的栅堆叠。栅堆叠包括栅介质层102′和栅导体层104。栅介质层102′包括位于端部的回填部分。可选地，该回填部分沿栅堆叠的侧壁延伸，充当栅堆叠的第一侧墙。
这里需要指出的是，尽管在以上的说明中，针对由于倾斜离子注入而造成栅介质损伤的情况，描述了对栅介质层进行选择性刻蚀和回填的处理。但是，本公开不限于此。例如，即便不进行倾斜离子注入，也可以对栅介质层进行选择性刻蚀和回填的处理，以便去除栅介质层端部可能存在的损伤。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (7)

1.一种制造半导体器件的方法，包括：
在衬底上形成栅堆叠，栅堆叠包括栅介质层和栅导体层；
进行倾斜离子注入；
选择性刻蚀栅介质层的端部，从而形成空隙；以及
在空隙中填充栅介质层的材料。
2.根据权利要求1所述的方法，在空隙中填充栅介质层的材料包括：淀积所述材料并回蚀，其中，在回蚀过程中，保留所述材料位于栅堆叠侧壁上的部分，以用作栅堆叠的第一侧墙。
3.根据权利要求2所述的方法，其中，淀积包括低压化学气相淀积(LPCVD)或者原子层淀积(ALD)。
4.根据权利要求1所述的方法，选择性刻蚀通过湿法刻蚀、干法刻蚀或其组合来进行。
5.根据权利要求4所述的方法，其中，湿法刻蚀通过稀释HF溶液进行。
6.根据权利要求1所述的方法，其中，在选择性刻蚀栅介质层端部的操作中，控制刻蚀时间，以去除栅介质层端部受倾斜离子注入影响的区域。
7.根据权利要求1所述的方法，其中，倾斜离子注入用于形成晕圈区(halo)或者轻掺杂漏(LDD)。
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