CN107564816B - Ldmos晶体管及其形成方法 - Google Patents

Ldmos晶体管及其形成方法 Download PDF

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CN107564816B
CN107564816B CN201610504769.6A CN201610504769A CN107564816B CN 107564816 B CN107564816 B CN 107564816B CN 201610504769 A CN201610504769 A CN 201610504769A CN 107564816 B CN107564816 B CN 107564816B
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ldmos transistor
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CN107564816A (zh
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

一种LDMOS晶体管及其形成方法，其中所述形成方法，包括：提供半导体衬底，所述半导体衬底内形成有浅沟槽隔离结构；在所述半导体衬底中形成漂移区，所述漂移区包围所述浅沟槽隔离结构；在漂移区一侧的半导体衬底内形成体区；形成横跨覆盖部分所述体区、漂移区和浅沟槽隔离结构的栅极结构；在栅极结构一侧的漂移区内形成漏区；在栅极结构另一侧的体区内形成源区；在栅极结构一侧的漏区内以及栅极结构底部的漂移区内形成第一浅掺杂区，所述第一浅掺杂区的掺杂类型与漏区的掺杂类型相同，第一浅掺杂区的深度小于漏区和漂移区的深度。本发明的方法提高了LDMOS晶体管的工作电流。

Description

LDMOS晶体管及其形成方法
技术领域
本发明涉及半导体制作领域，特别涉及一种LDMOS晶体管及其形成方法。
背景技术
功率场效应管主要包括垂直双扩散场效应管(VDMOS，Vertical Double-DiffusedMOSFET)和横向双扩散场效应管(LDMOS，Lateral Double-Diffused MOSFET)两种类型。其中，相较于垂直双扩散场效应管(VDMOS)，横向双扩散场效应管(LDMOS)具有诸多优点，例如，后者具有更好的热稳定性和频率稳定性、更高的增益和耐久性、更低的反馈电容和热阻，以及恒定的输入阻抗和更简单的偏流电路。
现有技术中，一种常规的N型横向双扩散场效应管(LDMOS晶体管)结构如图1所示，包括：半导体衬底(图中未示出)，位于半导体衬底中的P阱100；位于P阱100内的N型漂移区101；位于N型漂移区101中的浅沟槽隔离结构104，所述浅沟槽隔离结构104用于增长横向双扩散场效应管导通的路径，以增大横向双扩散场效应管的击穿电压；位于N型漂移区101一侧的P阱100内的P型体区106；位于半导体衬底上的栅极结构105，所述栅极结构105横跨所述P型体区106和N型漂移区101，并部分位于浅沟槽隔离结构104上，所述栅极结构105包括位于半导体衬底上的栅介质层、位于栅介质层上的栅电极、位于栅介质层和栅电极两侧侧壁上的侧墙；位于栅极结构105一侧的P型体区106内的源区102，和位于栅极机构105的另一侧的N型漂移区101内的漏区103，源区102和漏区103的掺杂类型为N型。
但是现有的横向双扩散场效应管(LDMOS晶体管)的性能仍有待提高。
发明内容
本发明解决的问题是怎样提高LDMOS晶体管的工作电流。
为解决上述问题，本发明提供一种LDMOS晶体管的形成方法，包括：
提供半导体衬底，所述半导体衬底内形成有浅沟槽隔离结构；在所述半导体衬底中形成漂移区，所述漂移区包围所述浅沟槽隔离结构；在漂移区一侧的半导体衬底内形成体区；形成横跨覆盖部分所述体区、漂移区和浅沟槽隔离结构的栅极结构；在栅极结构一侧的漂移区内形成漏区；在栅极结构另一侧的体区内形成源区；在栅极结构一侧的漏区内以及栅极结构底部的漂移区内形成第一浅掺杂区，所述第一浅掺杂区的掺杂类型与漏区的掺杂类型相同，第一浅掺杂区的深度小于漏区和漂移区的深度。
可选的，形成所述第一浅掺杂区采用单角度离子注入，单角度离子注入时，注入离子从漏区指向源区的方向入射，注入离子入射方向与半导体衬底的法线的具有第一夹角，半导体衬底在单角度离子注入过程中不旋转。
可选的，所述第一浅掺杂区的深度为10nm～50nm，第一浅掺杂区掺杂离子的浓度为1e18～1e19atom/cm3。
可选的，所述LDMOS晶体管为P型的LDMOS晶体管，所述体区的掺杂类型为N型，漂移区的掺杂类型为P型，所述漏区的掺杂类型为P型，第一浅掺杂区的掺杂类型为P型，所述源区的掺杂类型为P型。
可选的，所述单角度离子注入注入的离子为BF2离子或B离子。
可选的，注入BF2离子或B离子时的注入角度为15～40度，注入剂量为1E13atom/cm2～1E14atom/cm2，注入能量为5Kev～40Kev。
可选的，所述单角度离子注入的离子还包括C离子或N离子。
可选的，注入C离子或N离子时的注入角度为15～40度，注入剂量为5E12atom/cm2～5E15atom/cm2，注入能量为0.5Kev～20Kev。
可选的，形成所述源区和漏区采用源漏离子注入，源漏离子注入注入的杂质离子为B离子、BF2离子、Ga离子或In离子中的一种或几种，源漏离子注入的注入角度为0～5度，注入剂量为5E13atom/cm2～5E15atom/cm2，注入能量为6Kev～50Kev。
可选的，所述LDMOS晶体管为N型的LDMOS晶体管，所述体区的掺杂类型为P型，漂移区的掺杂类型为N型，所述漏区的掺杂类型为N型，第一浅掺杂区的掺杂类型为N型，所述源区的掺杂类型为N型。
可选的，所述单角度离子注入注入的离子为P离子或As离子。
可选的，注入P离子或As离子时的注入角度为15～40度，注入剂量为1E13atom/cm2～1E14atom/cm2，注入能量为8Kev～45Kev。
可选的，所述单角度离子注入的离子还包括C离子或N离子。
可选的，注入C离子或N离子时的注入角度为15～40度，注入剂量为5E12atom/cm2～5E15atom/cm2，注入能量为0.5Kev～20Kev。
可选的，形成所述源区和漏区采用源漏离子注入，源漏离子注入注入的杂质离子为P离子、As离子或Sb离子中的一种或几种，源漏离子注入的注入角度为0～5度，注入剂量为5E13atom/cm2～5E15atom/cm2，注入能量为12Kev～50Kev。
可选的，采用单角度离子注入形成第一浅掺杂区时，同时在源区内形成第二掺杂区，所述第二掺杂区的掺杂类型与源区的掺杂类型相同，第二掺杂区的深度小于源区的深度，且第二掺杂区与栅极结构的侧壁具有第一距离。
本发明还提供了一种LDMOS晶体管，包括：
半导体衬底，位于半导体衬底内的浅沟槽隔离结构；位于所述半导体衬底中的漂移区，所述漂移区包围所述浅沟槽隔离结构；位于漂移区一侧的半导体衬底的体区；横跨覆盖部分所述体区、漂移区和浅沟槽隔离结构的栅极结构；位于栅极结构一侧的漂移区内的漏区；位于栅极结构另一侧的体区内的源区；位于栅极结构一侧的漏区内以及栅极结构底部的漂移区内的第一浅掺杂区，所述第一浅掺杂区的掺杂类型与漏区的掺杂类型相同，第一浅掺杂区的深度小于漏区和漂移区的深度。
可选的，所述第一浅掺杂区的深度为10nm～50nm，第一浅掺杂区掺杂离子的浓度为1e18～1e19atom/cm3。
可选的，所述LDMOS晶体管为P型的LDMOS晶体管，所述体区的掺杂类型为N型，漂移区的掺杂类型为P型，所述漏区的掺杂类型为P型，第一浅掺杂区的掺杂类型为P型，所述源区的掺杂类型为P型。
可选的，所述LDMOS晶体管为N型的LDMOS晶体管，所述体区的掺杂类型为P型，漂移区的掺杂类型为N型，所述漏区的掺杂类型为N型，第一浅掺杂区的掺杂类型为N型，所述源区的掺杂类型为N型。
与现有技术相比，本发明的技术方案具有以下优点：
本发明的LDMOS晶体管的形成方法，在栅极结构一侧的漏区内以及栅极结构底部的漂移区内形成第一浅掺杂区，所述第一浅掺杂区的掺杂类型与漏区的掺杂类型相同，第一浅掺杂区的深度小于漏区和漂移区的深度，第一浅掺杂区的存在改善了漂移区和漏区中浅沟槽隔离结构(STI)的存在导致的杂质离子在该区域的堆积分布，提高浅沟槽隔离结构周围的漏区和漂移区内杂质离子分布的均匀性，减小漏区和漂移区表面区域的电阻的同时防止局部高电阻区对阈值电压的影响，当LDMOS晶体管工作时，从而使得漏区到源区之间的导通路径上的导通电阻减小，因而在漏区施加与现有技术相同大小的工作电压时，增大了LDMOS晶体管的工作电流。同时本发明的方法，通过形成第一掺杂区，在通过杂质补充原理而改善沟道掺杂均匀性的同时，可以有效防止局部高电阻区对整个有效沟道的影响，并尽可能的防止了了短沟道效应的产生。
本发明的LDMOS晶体管，在栅极结构一侧的漏区内以及栅极结构底部的漂移区内具有第一浅掺杂区，所述第一浅掺杂区的掺杂类型与漏区的掺杂类型相同，第一浅掺杂区的深度小于漏区和漂移区的深度，第一浅掺杂区的存在改善了漂移区和漏区中浅沟槽隔离结构(STI)的存在导致的杂质离子在该区域的堆积分布，提高浅沟槽隔离结构周围的漏区和漂移区内杂质离子分布的均匀性，减小漏区和漂移区表面区域的电阻的同时防止局部高电阻区对阈值电压的影响，当LDMOS晶体管工作时，从而使得漏区到源区之间的导通路径上的导通电阻减小，因而在漏区施加与现有技术相同大小的工作电压时，增大了LDMOS晶体管的工作电流。同时本发明的LDMOS晶体管，第一掺杂区的存在，在改善沟道掺杂均匀性的同时，可以有效防止局部高电阻区对整个有效沟道的影响，并尽可能的防止了了短沟道效应的产生。
附图说明
图1是现有技术的LDMOS晶体管的结构示意图；
图2～图7为本发明实施例LDMOS晶体管形成过程的剖面结构示意图。
具体实施方式
如背景所言，现有的横向双扩散场效应管(LDMOS晶体管)的性能仍有待提高，比如现有的LDMOS晶体管的工作电流值的大小仍有待提升。
研究发现，现有技术LDMOS晶体管工作电流受制于源区和漏区之间的导通电阻难以在继续增加，虽然可以通过减小源区和漏区之间沟道的宽度(或尺寸)或者增加源区和漏区的掺杂剂量以提高工作电流值，但是相应的使得LDMOS晶体管击穿电压会降低以及引起短沟道效应或者其他电学性能的改变。
进一步研究发现，现有的工艺通过离子注入工艺形成源区和漏区时，通常采用统一的沟道表面区离子注入来调节阈值电压，这种离子注入有时会导致沟道区阻值过大，抑制工作电流的大小。同时，由于现有工艺中漂移区和漏区中浅沟槽隔离结构(STI)的存在会导致杂质离子在该区域的堆积分布(杂质离子分布不均匀)，造成漂移区和漏区局部高电阻区而影响沟道阈值电压和工作电流，而单一调节沟道离子注入虽可以降低阈值电压以提高工作电流，但难以使得工作电压和工作电流同时满足要求以及改善由于以上所述原因而导致的杂质不均匀性的难题。
为此，本发明提供了一种LDMOS晶体管及其形成方法，其中，LDMOS晶体管的形成方法，在栅极结构一侧的漏区内以及栅极结构底部的漂移区内形成第一浅掺杂区，所述第一浅掺杂区的掺杂类型与漏区的掺杂类型相同，第一浅掺杂区的深度小于漏区和漂移区的深度，第一浅掺杂区的存在改善了漂移区和漏区中浅沟槽隔离结构(STI)的存在导致的杂质离子在该区域的堆积分布，提高浅沟槽隔离结构周围的漏区和漂移区内杂质离子分布的均匀性，减小漏区和漂移区表面区域的电阻的同时防止局部高电阻区对阈值电压的影响，当LDMOS晶体管工作时，从而使得漏区到源区之间的导通路径上的导通电阻减小，因而在漏区施加与现有技术相同大小的工作电压时，增大了LDMOS晶体管的工作电流。同时本发明的方法，通过形成第一掺杂区，在通过杂质补充原理而改善沟道掺杂均匀性的同时，可以有效防止局部高电阻区对整个有效沟道的影响，并尽可能的防止了短沟道效应的产生。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。在详述本发明实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图2～图7为本发明实施例LDMOS晶体管形成过程的剖面结构示意图。
参考图2，提供半导体衬底200，所述半导体衬底200内形成有浅沟槽隔离结构201。
所述半导体衬底200的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施中，所述半导体衬底200的材料为硅。
所述浅沟槽隔离结构201用于增长LDMOS晶体管导通的路径，以增大LDMOS晶体管的击穿电压。
在一实施例中，所述浅沟槽隔离结构201的形成过程为：在所述半导体衬底200上形成掩膜层(图中未示出)，所述掩膜层中具有暴露出半导体衬底表面的开口；沿开口刻蚀所述半导体衬底200，在半导体衬底200中形成凹槽；形成覆盖所述掩膜层并填充满凹槽的隔离材料层；平坦化所述隔离材料层，直至暴露出半导体衬底表面，在所述凹槽中形成浅沟槽隔离结构。
所述浅沟槽隔离结构201可以为单层或多层(≥2层)堆叠结构。在一实施例中，所述多层堆叠结构为双层堆叠结构，包括位于凹槽的侧壁和底部表面的衬垫层和位于衬底垫层上填充满凹槽的填充层，所述衬垫层的材料可以为氧化硅，所述填充层的材料可以为氮化硅。
参考图3，在所述半导体衬底200中形成漂移区203，所述漂移区203包围所述浅沟槽隔离结构201。
在形成漂移区203之前，还可以在所述半导体衬底200内形成阱区202，形成的漂移区203位于阱区202内，漂移区203的深度小于阱区202的深度，所述阱区202可以在形成浅沟槽隔离结构201之前形成，也可以在形成浅沟槽隔离结构201之后形成。
本实施例中，所述阱区202和漂移区203通过离子注入工艺形成，形成漂移区之前在半导体衬底上形成掩膜层，所述掩膜层暴露出待注入的区域。在一实施例中，当形成的LDMOS为P型的LDMOS时，所述阱区202中掺杂N型的杂质离子，所述漂移区203中掺杂P型的杂质离子；在另一实施例中，当形成的LDMOS为N型的LDMOS时，所述阱区202中掺杂P型的杂质离子，所述漂移区203中掺杂N型的杂质离子。所述N型杂质离子为磷离子、砷离子、锑离子中的一种或几种；P型杂质离子为硼离子、铟离子、镓离子中的一种或几种。
参考图4，在漂移区203一侧的半导体衬底200内形成体区208。
所述体区208的形成工艺为离子注入，在一实施例中，当形成的LDMOS为P型的LDMOS时，所述体区208中掺杂N型的杂质离子；在另一实施例中，当形成的LDMOS为N型的LDMOS时，所述体区208中掺杂P型的杂质离子。所述N型杂质离子为磷离子、砷离子、锑离子中的一种或几种；P型杂质离子为硼离子、铟离子、镓离子中的一种或几种。
本实施例中，所述体区208在漂移区203形成之后形成；在其他实施例中，所述体区208可以在漂移区203形成之前形成。
参考图5，形成横跨覆盖部分所述体区208、漂移区203和浅沟槽隔离结构201的栅极结构207。
在一实施例中，所述栅极结构207包括栅介质层204、位于栅介质层204上的栅电极206。
本实施例中，所述栅介质层204的材料为氧化硅、所述栅电极206的材料为多晶硅。栅极结构的形成过程为：形成覆盖所述半导体衬底200表面的栅介质层材料层；在所述栅介质材料层上形成栅电极材料层；刻蚀所述栅电极材料层和栅介质材料层，在部分所述体区208、(部分)漂移区203、(部分)浅沟槽隔离结构201、以及漂移区203和体区208之间的半导体衬底表面上形成栅介质层204，在栅介质层204上形成栅电极206。
在本发明的其他实施例中，所述栅介质层204的材料还可以为高K介电材料，比如HfO2、TiO2、HfZrO、HfSiNO等，所述栅电极206的材料为金属，比如W、Cu、Al等。可以通过后栅工艺形成所述栅极结构。
在一实施例中，栅介质层204和的栅电极206两侧侧壁上还形成有侧墙205。所述侧墙205在后续第一浅掺杂区时保护栅电极206的侧壁不会被注入损伤，并且所述侧墙205控制后续在体区208中形成的源区的位置。
所述侧墙212可以为单层或多层(≥2层)结构，所述侧墙212的材料为氧化硅、氮化硅或其他合适的材料。
参考图6，在栅极结构207一侧的漂移区203内形成漏区209；在栅极结构207另一侧的体区210内形成源区210。
形成所述源区209和漏区210采用源漏离子注入。在一实施例中，当形成的LDMOS为P型的LDMOS时，所述漏区209和源区210中掺杂P型的杂质离子；在另一实施例中，当形成的LDMOS为N型的LDMOS时，所述漏区209和源区210中掺杂N型的杂质离子。所述N型杂质离子为磷(P)离子、砷(As)离子、锑(Te)离子中的一种或几种；P型杂质离子为硼(B)离子、氟化硼(BF2)离子、铟(In)离子、镓(Ga)离子中的一种或几种。
在一实施例中，源漏离子注入注入的杂质离子为B离子、BF2离子、Ga离子或In离子中的一种或几种时，源漏离子注入的注入角度为0～5度，注入剂量为5E13atom/cm2～5E15atom/cm2，注入能量为6Kev～50Kev。
在另一实施例中，源漏离子注入注入的杂质离子为P离子、As离子或Sb离子中的一种或几种时，源漏离子注入的注入角度为0～5度，注入剂量为5E13atom/cm2～5E15atom/cm2，注入能量为12Kev～50Kev。
参考图7，在栅极结构207一侧的漏区209内以及栅极结构207底部的漂移区203内形成第一浅掺杂区211，所述第一浅掺杂区211的掺杂类型与漏区209的掺杂类型相同，第一浅掺杂区211的深度小于漏区209和漂移区203的深度。
第一浅掺杂区211包括两部分，一部分位于栅极结构207一侧的漏区209内，一部分位于栅极结构207底部的漂移区203内，第一浅掺杂区211的存在改善了漂移区203和漏区209中浅沟槽隔离结构(STI)的存在导致的杂质离子在该区域的堆积分布，提高浅沟槽隔离结构周围的漏区209和漂移区203内杂质离子分布的均匀性，并减小漏区209和漂移区203表面区域的电阻的同时防止局部高电阻区对阈值电压的影响，当LDMOS晶体管工作时，从而使得漏区209到源区210之间的导通路径上的导通电阻减小，因而在漏区209施加与现有技术相同大小的工作电压时，增大了LDMOS晶体管的工作电流。
在一实施例中，所述第一浅掺杂区211的深度为10nm～50nm，1e18～1e19atom/cm3，使得第一浅掺杂区211对改善了漂移区203和漏区209中浅沟槽隔离结构(STI)的存在导致的杂质离子在该区域的堆积分布，提高浅沟槽隔离结构周围的漏区209和漂移区203内杂质离子分布的均匀性，以及减小漏区209和漂移区203表面区域的电阻的同时防止局部高电阻区对阈值电压的效果更佳。需要说明的是，第一浅掺杂区211的深度是指半导体衬底表面到第一掺杂区211底部边界的垂直距离。
形成所述第一浅掺杂区211采用单角度离子注入21，单角度离子注入时，注入离子从漏区209指向源区210的方向入射，注入离子入射方向与半导体衬底200的法线的具有第一夹角，半导体衬底200在单角度离子注入过程中不旋转，通过单角度离子注入，同时在栅极结构207一侧的漏区203的表面附近以及栅极结构207底部的漂移区表面附近第一浅掺杂区211，从而简化了第一浅掺杂区211的形成工艺难度。
在一实施例中，在进行单角度离子注入之前，可以在半导体衬底200和栅极结构上形成掩膜层，所述掩膜层中具有暴露出漏区209的表面以及浅沟槽隔离结构201上方的侧墙205的开口，所述掩膜层作为单角度离子注入时的掩膜。
当形成的所述LDMOS晶体管为P型的LDMOS晶体管时，第一浅掺杂区211的掺杂类型为P型，在一实施例中，所述单角度离子注入注入的离子为BF2离子或B离子，注入BF2离子时的注入角度为15～40度，可以为15度、20度、30度、35度，注入剂量为1E13atom/cm2～1E14atom/cm2，可以为2E13atom/cm2、3E13atom/cm2、4E13atom/cm2、5E13atom/cm2、6E13atom/cm2、7E13atom/cm2、8E13atom/cm2、9E13atom/cm2，注入能量为5Kev～40Kev，可以为10Kev、15Kev、20Kev、25Kev、30Kev、35Kev，使得形成的第一浅掺杂区211的位置精度较高，并且能有效提高浅沟槽隔离结构周围的漏区209和漂移区203内杂质离子分布的均匀性以及减小漏区209和漂移区203表面附近的电阻，并且注入的离子为BF2离子时，F能防止B向向漂移区203和体区208之间的半导体衬底中扩散，防止短沟道效应。
在一实施例中，单角度离子注入注入的离子为BF2离子或B离子，所述单角度离子注入的离子还包括C离子或N离子，C离子或N离子能防止B离子向漂移区203和体区208之间的半导体衬底中扩散，从而防止短沟道效。在一实施例中，注入C离子或N离子时的注入角度为15～40度，可以为10度、20度、30度、35度，注入剂量为5E12atom/cm2～5E14atom/cm2，6E12atom/cm2、9E12atom/cm2、2E13atom/cm2、5E13atom/cm2、8E13atom/cm2、9E13atom/cm2E15atom/cm2、4E15atom/cm2，注入能量为0.5Kev～20Kev，1Kev、2Kev、5Kev、10Kev、12Kev、14Kev、15Kev、17Kev、18Kev、19Kev，使得注入的C离子或N离子的位置与第一浅掺杂区211的位置相应，并且不会影响第一浅掺杂区211的电学性能，并能有效的防止第一浅掺杂区211中B离子的扩散。
当所述LDMOS晶体管为N型的LDMOS晶体管，所述第一浅掺杂区211的掺杂类型为N型，在一实施例中，所述单角度离子注入注入的离子为P离子或As离子，注入P离子或As离子时的15～40度，注入剂量为1E13atom/cm2～1E14atom/cm2，注入能量为8Kev～45Kev，使得形成的第一浅掺杂区211的位置精度较高，并且能有效提高浅沟槽隔离结构周围的漏区209和漂移区203内杂质离子分布的均匀性以及减小漏区209和漂移区203表面附近的电阻。
单角度离子注入注入的离子为P离子或As离子，所述单角度离子注入的离子还包括C离子或N离子，C离子或N离子能防止第一浅掺杂区211中的P离子或As离子向漂移区203和体区208之间的半导体衬底中扩散，从而防止短沟道效应。
在一实施例中，注入C离子或N离子时的注入角度为15～40度，注入剂量为5E12atom/cm2～5E15atom/cm2，注入能量为0.5Kev～20Kev，使得注入的C离子或N离子的位置与第一浅掺杂区211的位置相应，并且不会影响第一浅掺杂区211的电学性能，并能有效的防止第一浅掺杂区211中P离子或As离子的扩散。
在其他实施例中，采用单角度离子注入形成第一浅掺杂区211时，可以同时在源区210内形成第二掺杂区212，所述第二掺杂区212的掺杂类型与源区210的掺杂类型相同，第二掺杂区212的深度小于源区210的深度，且第二掺杂区212与栅极结构207的侧壁具有第一距离(由于第二掺杂区212是与第一掺杂区同时形成，单角度离子注入时，半导体衬底200是不旋转的，因而注入过程中，栅极结构207挡住了射向源区方向的部分杂质离子，使得形成第二掺杂区212时远离栅极结构207和侧墙205的侧壁，即靠近源区210的栅极结构底部的体区208内不会注入反型的杂质离子，从而在减小源区210表面附近的电阻的同时，防止短沟道效应的产生。
在进行单角度离子注入后，进行退火工艺，以激活掺杂离子，在一实施例中，所述退火工艺的温度为900～1100C，退火的时间为10s～30s。
前述实施例中，在形成栅极结构后，再在在栅极结构一侧的漏区内以及栅极结构底部的漂移区内形成第一浅掺杂区。
在另一实施例中，所述第一浅掺杂区可以在形成第一栅极结构之前形成，具体过程为：在所述半导体衬底中形成漂移区，所述漂移区包围所述浅沟槽隔离结构；在漂移区内形成第一浅掺杂区，第一浅掺杂区包围所述浅沟槽隔离结构，第一浅掺杂区的掺杂类型与漏区的掺杂类型相同，第一浅掺杂区的深度小于漂移区的深度；在漂移区一侧的半导体衬底内形成体区；形成横跨覆盖部分所述体区、漂移区、第一浅掺杂区和浅沟槽隔离结构的栅极结构；在栅极结构一侧的漂移区内形成漏区，漏区的深度大于第一浅掺杂区的深度小于漂移区的深度；在栅极结构另一侧的体区内形成源区。本实施例中，由于第一浅掺杂区在栅极结构形成之前形成，因而防止了栅极结构对第一掺杂区位置和杂质离子的浓度以及杂质离子的分布的均匀性的影响，提高了形成的第一浅掺杂区位置的精度和杂质离子分布的均匀性。
形成第一浅掺杂区采用离子注入工艺，形成第一浅掺杂区与形成漂移区可以采用同一掩膜层，相比于前述实施例中第一掺杂区的形成工艺，此实施例中第一掺杂区的形成工艺采用无角度(注入方向与半导体衬底法线方向平行)的离子注入，形成工艺的其他限定与前述实施例中第一掺杂区的形成工艺的限定相同。需要说明的是，此实施例中，各结构的其他限定也请参考前述实施例中相应的结构的限定，在此不再赘述。
本发明还提供了一种LDMOS晶体管，请参考图7，包括：
半导体衬底200，位于半导体衬底200内的浅沟槽隔离结构201；
位于所述半导体衬底200中的漂移区203，所述漂移区203包围所述浅沟槽隔离结构201；
位于漂移区203一侧的半导体衬底200的体区208；
横跨覆盖部分所述体区208、漂移区203和浅沟槽隔离结构201的栅极结构207；
位于栅极结构207一侧的漂移区203内的漏区209；
位于栅极结构207另一侧的体区208内的源区210；
位于栅极结构207一侧的漏区209内以及栅极结构207底部的漂移区203内的第一浅掺杂区211，所述第一浅掺杂区211的掺杂类型与漏区209的掺杂类型相同，第一浅掺杂区211的深度小于漏区209和漂移区203的深度。
所述第一浅掺杂区211的深度为10nm～50nm，第一浅掺杂区211掺杂离子的浓度为1e18～1e19atom/cm3。
所述LDMOS晶体管为P型的LDMOS晶体管，所述体区208的掺杂类型为N型，漂移区203的掺杂类型为P型，所述漏区209的掺杂类型为P型，第一浅掺杂区211的掺杂类型为P型，所述源区210的掺杂类型为P型。
所述LDMOS晶体管为N型的LDMOS晶体管，所述体区208的掺杂类型为P型，漂移区203的掺杂类型为N型，所述漏区209的掺杂类型为N型，第一浅掺杂区211的掺杂类型为N型，所述源区210的掺杂类型为N型。
需要说明的是本实施中，关于晶体管的其他限定和描述请参考前述实施例中晶体管形成过程部分的相应的限定和描述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

1.一种LDMOS晶体管的形成方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底内形成有浅沟槽隔离结构；
在所述半导体衬底中形成漂移区，所述漂移区包围所述浅沟槽隔离结构；
在漂移区一侧的半导体衬底内形成体区；
形成横跨覆盖部分所述体区、漂移区和浅沟槽隔离结构的栅极结构；
在栅极结构一侧的漂移区内形成漏区；
在栅极结构另一侧的体区内形成源区；
在栅极结构一侧的漏区内以及栅极结构底部的漂移区内形成第一浅掺杂区，所述第一浅掺杂区的掺杂类型与漏区的掺杂类型相同，第一浅掺杂区的深度小于漏区和漂移区的深度；
形成所述第一浅掺杂区采用单角度离子注入，单角度离子注入时，注入离子从漏区指向源区的方向入射，注入离子入射方向与半导体衬底的法线的具有第一夹角，半导体衬底在单角度离子注入过程中不旋转；
采用单角度离子注入形成第一浅掺杂区时，同时在源区内形成第二掺杂区，所述第二掺杂区的掺杂类型与源区的掺杂类型相同，第二掺杂区的深度小于源区的深度，且第二掺杂区与栅极结构的侧壁具有第一距离。
2.如权利要求1所述的LDMOS晶体管的形成方法，其特征在于，所述第一浅掺杂区的深度为10nm～50nm，第一浅掺杂区掺杂离子的浓度为1e18～1e19atom/cm3。
3.如权利要求2所述的LDMOS晶体管的形成方法，其特征在于，所述LDMOS晶体管为P型的LDMOS晶体管，所述体区的掺杂类型为N型，漂移区的掺杂类型为P型，所述漏区的掺杂类型为P型，第一浅掺杂区的掺杂类型为P型，所述源区的掺杂类型为P型。
4.如权利要求3所述的LDMOS晶体管的形成方法，其特征在于，所述单角度离子注入注入的离子为BF2离子或B离子。
5.如权利要求4所述的LDMOS晶体管的形成方法，其特征在于，注入BF2离子或B离子时的注入角度为15～40度，注入剂量为1E13atom/cm2～1E14atom/cm2，注入能量为5KeV～40KeV。
6.如权利要求4所述的LDMOS晶体管的形成方法，其特征在于，所述单角度离子注入的离子还包括C离子或N离子。
7.如权利要求6所述的LDMOS晶体管的形成方法，其特征在于，注入C离子或N离子时的注入角度为15～40度，注入剂量为5E12atom/cm2～5E15atom/cm2，注入能量为0.5KeV～20KeV。
8.如权利要求2所述的LDMOS晶体管的形成方法，其特征在于，形成所述源区和漏区采用源漏离子注入，源漏离子注入注入的杂质离子为B离子、BF2离子、Ga离子或In离子中的一种或几种，源漏离子注入的注入角度为0～5度，注入剂量为5E13atom/cm2～5E15atom/cm2，注入能量为6KeV～50KeV。
9.如权利要求2所述的LDMOS晶体管的形成方法，其特征在于，所述LDMOS晶体管为N型的LDMOS晶体管，所述体区的掺杂类型为P型，漂移区的掺杂类型为N型，所述漏区的掺杂类型为N型，第一浅掺杂区的掺杂类型为N型，所述源区的掺杂类型为N型。
10.如权利要求9所述的LDMOS晶体管的形成方法，其特征在于，所述单角度离子注入注入的离子为P离子或As离子。
11.如权利要求10所述的LDMOS晶体管的形成方法，其特征在于，注入P离子或As离子时的注入角度为15～40度，注入剂量为1E13atom/cm2～1E14atom/cm2，注入能量为8KeV～45KeV。
12.如权利要求10所述的LDMOS晶体管的形成方法，其特征在于，所述单角度离子注入的离子还包括C离子或N离子。
13.如权利要求12所述的LDMOS晶体管的形成方法，其特征在于，注入C离子或N离子时的注入角度为15～40度，注入剂量为5E12atom/cm2～5E15atom/cm2，注入能量为0.5KeV～20KeV。
14.如权利要求9所述的LDMOS晶体管的形成方法，其特征在于，形成所述源区和漏区采用源漏离子注入，源漏离子注入注入的杂质离子为P离子、As离子或Sb离子中的一种或几种，源漏离子注入的注入角度为0～5度，注入剂量为5E13atom/cm2～5E15atom/cm2，注入能量为12KeV～50KeV。
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