CN103560150A - 具有外延源区和漏区的金属栅晶体管 - Google Patents
具有外延源区和漏区的金属栅晶体管 Download PDFInfo
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- CN103560150A CN103560150A CN201310419494.2A CN201310419494A CN103560150A CN 103560150 A CN103560150 A CN 103560150A CN 201310419494 A CN201310419494 A CN 201310419494A CN 103560150 A CN103560150 A CN 103560150A
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- doping
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- metal gate
- crystal silicon
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Abstract
本发明公开一种具有外延源区和漏区的金属栅晶体管。描述了形成于重掺杂的衬底上的MOS晶体管。在低温处理中使用金属栅以防止衬底的掺杂扩散到晶体管的沟道区。
Description
本申请是国际申请日为2005年9月29日、中国国家阶段申请号为200580032453.1、题为“具有外延源区和漏区的金属栅晶体管”的发明专利申请的分案申请。
发明领域
本发明涉及MOS晶体管的领域,尤其涉及以外延源区和漏区制造的MOS晶体管。
现有技术和相关技术
在Noda等人的“0.1μm Delta-Doped MOSFET Using Post Low EnergyImplanting Selective Epitaxy”,VLSI Technology1994,技术论文的摘要中描述了δ掺杂晶体管。δ掺杂晶体管的动机是用未掺杂或轻掺杂的沟道来实现较高的迁移率(较低的杂质分散)。在2003年10月24日提交的题为“Epitaxially DepositedSource/Drain”的专利申请序列号10/692,696中也描述了这种器件,该专利转让给本申请的受让人。
这些晶体管的制造大部分依靠重掺杂衬底和衬底的轻掺杂或未掺杂外延形成的表面之间的掺杂水平的差别。由于这一掺杂水平的差别,蚀刻剂能够在衬底的表面区和主体之间进行区分。然而,出现了一个问题,即在形成栅结构时,需要相对较高温度的处理以便例如激活多晶硅栅中的掺杂。这导致掺杂剂从衬底扩散到沟道区中,由此使晶体管的性能劣化。
附图简述
图1是硅衬底的上部区域的横截面正视图,用于示出在衬底的上部区域中的掺杂曲线。
图2示出当在衬底上生长未掺杂或轻掺杂半导体层后图1的衬底。
图3是除用于形成栅的其它层以外的图2的衬底和半导体层的横截面俯视图。
图4示出在形成栅后图3的衬底。
图5示出在栅上形成侧壁隔片后图4的衬底。
图6示出在用于蚀刻半导体层的蚀刻步骤后图5的衬底。该图示出栅的底切。
图7示出在源区和漏区的外延生长后图6的衬底。
图8示出在形成另外的隔片和掺杂了源区和漏区的暴露部分后图7的结构。
图9示出在形成硅化物层后图8的结构。
图10示出其中两个晶体管并排示出的图9的结构,尤其描述了n沟道晶体管和p沟道晶体管。
图11示出在层间电介质(ILD)的化学机械抛光(CMP)后图10的结构。
图12示出当在p沟道晶体管区上形成光刻胶层并将多晶硅栅和其下面的绝缘层从n沟道栅中去除之后图11的结构。
图13示出在形成n金属层后图12的结构。
图14示出在CMP处理后图13的结构。
图15示出在从p沟道栅中去除多晶硅栅和其下面的绝缘层后图14的结构。
图16示出在沉积p金属后图15的结构。
图17示出CMP处理后图16的结构。
详细描述
描述了互补金属氧化物半导体(MOS)场效应晶体管的制造工艺和所得的晶体管。在以下描述中,陈述了诸如特定的掺杂剂浓度水平、特定的化学药品等的众多特定的细节,以提供对本发明的全面理解。本领域的技术人员将明白,不需要这些特定细节也能实施本发明。在其他情况下,没有详细描述诸如清洗步骤之类的公知的处理步骤,以免不必要地使以下的公开内容晦涩。
在图1中,示出了单晶硅衬底10的约200纳米(nm)的上部。如图所示,用诸如硼之类的掺杂剂重掺杂该衬底的上部区域。掺杂曲线示出掺杂水平在超过1019原子/立方厘米或更高的表面下具有峰值。该掺杂曲线可利用离子注入来获得。
在衬底的掺杂后,在衬底10的上表面上形成示为单晶硅层12的外延层。例如,外延硅层12的沉积利用基于二氯硅烷的化学品在诸如ASM E3000反应器之类的单晶片CVD反应器中实现。该膜以气体流量为140-250sccm的二氯硅烷(SiH2Cl2)、100-150sccm的HCl、20slm的H2在825℃和20Torr的处理压力下来沉积。在这些处理条件下,对于暴露的衬底上的硅实现了10-15nm/min的沉积速度,同时实现了对于隔片和氧化物区的极好的选择性。层12可具有约85nm的厚度,且其掺杂浓度将例如小于衬底的埋置峰值掺杂浓度的1/100。
在形成层12后,在层10上形成绝缘层13。层13可以是薄的、热生长氧化物层或沉积的二氧化硅层。接着,在绝缘层13上沉积多晶硅层14。正如将要看到的,由层14形成的栅是牺牲的。它们随后将被去除,并由金属代替由这些多晶硅栅占据的区域。在多晶硅层14上形成硬掩模。
接着,如图4所示,通过首先利用普通的光刻处理掩模并蚀刻硬掩模15以限定用于栅的掩模构件来制造牺牲栅结构。现在,利用普通的蚀刻剂与硬掩模15对准地蚀刻多晶硅层14和绝缘层13。在图4中描述了所得的结构。
如图5所示,然后在图4的栅上形成侧壁16。可利用普通的侧壁处理来形成相对薄的氮化硅侧壁构件16。这些侧壁隔片的目的是在随后的处理期间保护多晶硅。因此,多晶硅栅14的所有侧面都被覆盖。因为侧壁隔片用于保护多晶硅,所以它们可相对薄。
现在,蚀刻层12以形成沟道体12a。该蚀刻底切栅结构,如由图6中的底切20所示。
层12可用各种基于氢氧化物的溶液来蚀刻。然而,为了对重掺杂结构的高选择性,采用相对温和的处理条件和湿法蚀刻。一种方法是用2-10%范围的体积浓度的氢氧化铵水溶液,在25摄氏度下用以0.5到5W/cm2的功率耗散超声能或兆声能的超声波传感器来处理。
然后生长源区和漏区,以建立在栅边缘下横向延伸一定的距离到沟道体12a的浅、高掺杂的源/漏尖端(延伸)。对p沟道和n沟道晶体管使用分离处理,且源区和漏区中的每一个都在不同的处理步骤中生长,两者都利用了原位掺杂。这得到了高掺杂的源区和漏区,在一种情况下用p型掺杂剂,而在另一种情况下用n型掺杂剂。
在形成PMOS晶体管时,源/漏延伸(尖端)是通过选择性地沉积外延硼(B)掺杂的硅或具有高达30%的锗浓度的SiGe来形成的凸起的源/漏区。在100sccm的二氯甲硅烷(DCS)、20slm的H2、750-800℃、20Torr、150-200sccm的HCl、150-200sccm流量的乙硼烷(B2H6)以及150-200sccm流量的CeH4的处理条件下,获得了具有20nm/min的沉积速率、1E20cm-3的B浓度以及20%的锗浓度的高掺杂SiGe膜。由膜中的高B浓度得到的0.7-0.9mOhm-cm的低电阻率提供在尖端源/漏区中的高电导率以及由此减小的R外部的优点。在源/漏区中的SiGe在沟道上施加压缩应力,这进而得到增强的迁移率和提高的晶体管性能。
对于NMOS晶体管,在100sccm的DCS、25-50sccm的HCl、具有20slm的载体H2气体流量的200-300sccm的1%Ph3在750℃和20Torr的处理条件下利用选择性沉积的原位磷掺杂硅来形成源/漏区。在沉积膜中获得了具有0.4-0.6mOhm-cm的电阻率的2E20cm-3的磷浓度。
在如图7所示形成源/漏区后,利用普通的处理来形成另外的隔片24。作为一个示例,隔片可以是氮化硅或二氧化硅隔片。隔片24与如图8所示的隔片16的厚度相比相对较厚。
现在进行离子注入以在衬底10中形成源/漏区26。此外,对p型掺杂剂和n型掺杂剂使用分隔离子注入工艺。可将区域26注入成1020原子/立方厘米的水平。
如图9所示,可使用普通的硅化物工艺或自对准多晶硅化物(salicide)处理来形成自对准多晶硅化物层28,从而使源/漏区的上表面更导电。
在图10中,连同p沟道晶体管一起描述了n沟道晶体管。对于n沟道晶体管沟道区示为12b,而对于p沟道晶体管为12c。以下使用字母“b”来表示用于n沟道晶体管的层和区域,类似地,用字母“c”来表示用于p沟道晶体管的层和区域。图10中所示的结构除在晶片上形成ILD30外与图9所示的一样。诸如二氧化硅、碳掺杂二氧化硅或其他低k电介质等多种电介质中的任何一种可用于ILD。
现在,使用CMP来提供平坦化表面并从栅14b和14c的顶部去除自对准多晶硅化物。所得的结构在图11中示出。
接着,在p沟道晶体管上形成光刻胶层32,并利用湿法蚀刻剂来从n沟道晶体管去除多晶硅。同样去除下面的绝缘层,从而形成图12中所描述的开口。
现在,如图13所示,连同称为“n金属”的金属层38一起形成绝缘层37b,金属层38被称为“n金属”是因为它是具有用于n沟道晶体管的适当功函数的金属。栅电介质理想地具有高介电常数,诸如如HfO2、ZrO2等的金属氧化物电介质或如PZT或BST等的其它高k电介质。高k介电膜可通过诸如化学气相沉积(CVD)之类的任何公知的技术来形成。栅电极层38可通过适当的栅电极材料的毯式沉积(blanket deposition)来形成。在一个实施例中,栅电极材料包括诸如钨、钽和/或其氮化物和合金等金属膜。对于n沟道晶体管,可采用4.0到4.6eV范围的功函数。
接着使用CMP来使表面平坦化,从而去除除以前由多晶硅栅占据的区域内以外的金属层38。所得的栅38b和下面的绝缘层37b在图14中示出。
使用湿法蚀刻剂来去除与p沟道晶体管相关联的多晶硅栅。此外,同样去除下面的绝缘层,以形成更适当的绝缘层。在去除多晶硅栅和下面的绝缘层后得到图15的开口42。在暴露的硅上形成栅电介质37c。该电介质可与电介质37b相同。
在图15的结构和栅电介质37b上形成金属层44。这示为图16中的“p金属”,因为该金属的功函数适合于p沟道晶体管。p金属除功函数较佳地在4.6到5.2eV之间外可与n金属的成分相同。
在沉积p金属后,利用CMP来使结构平坦化,且所得的结构在图17中示出。得到了具有栅37b和沟道区12b的n沟道晶体管,且类似地,得到了具有栅44c和沟道区12c的p沟道晶体管。
图17的晶体管及其制造在与现有技术晶体管相比时有几个优点。首先,浅的尖端(延伸)结深度对于帮助支持较小的晶体管尺寸是理想的。当利用传统的注入尖端技术时,最小的尖端结深度受到必要的栅重叠的限制。采用图17的结构和所述的处理,可更好地控制栅重叠尺寸和结深度。例如,可定时湿法蚀刻以确定栅结构下的底切的程度。
浅的尖端结深度允许制造较短的栅长度,而不增大截止状态的漏电流。需要在栅边缘下进行尖端掺杂以保证栅下的反型层和高掺杂的源/漏尖端区之间的低电阻路径。低电阻允许较高的驱动电流,这对于电路切换速度是关键的。
金属栅的一个优点是处理可在较低的温度下进行。这在与多晶硅栅相比时增加了以金属栅获得的较好的性能。在以上所述的处理中,较低温度的选择用于减小总的热暴露。正如先前所提及的,这防止掺杂剂从衬底扩散到沟道区。
因此,描述了具有金属栅的δ掺杂晶体管以及制造方法。
Claims (8)
1.一种PMOS晶体管,包括:
单晶硅衬底,包括重掺杂的上区域;
未掺杂或轻掺杂的单晶硅沟道区,直接设置在所述单晶硅衬底的最上表面上并具有顶表面;
源区和漏区对,每个源区和漏区包括直接设置在所述单晶硅衬底的最上表面上、与所述未掺杂或轻掺杂的单晶硅沟道区直接相邻且从所述单晶硅衬底的最上表面直接向上延伸超出所述未掺杂或轻掺杂的单晶硅沟道区的顶表面的外延硅锗第一部分,并且每个源区和漏区还包括仅部分地延伸到所述单晶硅衬底中的第二部分,所述第二部分直接在所述第一部分下方;以及
金属栅,与所述未掺杂或轻掺杂的单晶硅沟道区绝缘、被设置超过所述未掺杂或轻掺杂的单晶硅沟道区并位于其上方、且被设置超过所述源区和漏区中每一个的所述第一部分的至少部分并位于其上方,其中所述源区和漏区中每一个的所述第一部分包括在所述金属栅之下的所述外延硅锗和所述未掺杂或轻掺杂的单晶硅沟道区之间的成角度面轮廓,并且其中所述源区和漏区中每一个的所述第二部分仅包括一个圆化扩散角轮廓,所述一个圆化扩散角轮廓低于所述金属栅但并不在所述金属栅下方。
2.如权利要求1所述的晶体管,其特征在于,还包括设置在所述金属栅附近的第一侧壁隔片。
3.如权利要求2所述的晶体管,其特征在于,还包括在所述源区和漏区中每一个的所述第一部分的至少部分上的硅化物层。
4.如权利要求1所述的晶体管,其特征在于,所述单晶硅衬底的重掺杂的上区域具有1019原子/立方厘米或更高的峰值掺杂浓度
5.一种PMOS晶体管,包括:
单晶硅衬底,包括重掺杂的上区域;
未掺杂或轻掺杂的单晶硅沟道区,直接设置在所述单晶硅衬底的最上表面上并具有顶表面;
源区和漏区对,每个源区和漏区包括直接设置在单晶硅衬底的最上表面上、与所述未掺杂或轻掺杂的单晶硅沟道区直接相邻且从所述单晶硅衬底的最上表面直接向上延伸超出所述未掺杂或轻掺杂的单晶硅沟道区的顶表面的外延硅锗第一部分,并且每个源区和漏区还包括仅部分地延伸到所述单晶硅衬底中的第二部分,所述第二部分直接在所述第一部分下方;以及
非硅金属栅,与所述未掺杂或轻掺杂的单晶硅沟道区绝缘、被设置在所述未掺杂或轻掺杂的单晶硅沟道区上方、且被设置在所述源区和漏区中每一个的所述第一部分的至少部分的上方,其中所述源区和漏区中每一个的所述第一部分包括在所述非硅金属栅之下的所述外延硅锗和所述未掺杂或轻掺杂的单晶硅沟道区之间的成角度面轮廓,并且其中所述源区和漏区中每一个的所述第二部分仅包括一个圆化扩散角轮廓,所述一个圆化扩散角轮廓低于所述非硅金属栅但并不在所述非硅金属栅下方。
6.如权利要求5所述的晶体管,其特征在于,还包括设置在所述金属栅附近的第一侧壁隔片。
7.如权利要求6所述的晶体管,其特征在于,还包括在所述源区和漏区中每一个的所述第一部分的至少部分上的硅化物层。
8.如权利要求5所述的晶体管,其特征在于,所述单晶硅衬底的重掺杂的上区域具有1019原子/立方厘米或更高的峰值掺杂浓度
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US10/955,669 US7332439B2 (en) | 2004-09-29 | 2004-09-29 | Metal gate transistors with epitaxial source and drain regions |
CNA2005800324531A CN101027763A (zh) | 2004-09-29 | 2005-09-29 | 具有外延源区和漏区的金属栅晶体管 |
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Families Citing this family (134)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4866534B2 (ja) * | 2001-02-12 | 2012-02-01 | エーエスエム アメリカ インコーポレイテッド | 半導体膜の改良された堆積方法 |
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7268058B2 (en) * | 2004-01-16 | 2007-09-11 | Intel Corporation | Tri-gate transistors and methods to fabricate same |
US7154118B2 (en) * | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
EP1738001A2 (en) * | 2004-04-23 | 2007-01-03 | ASM America, Inc. | In situ doped epitaxial films |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US7611943B2 (en) * | 2004-10-20 | 2009-11-03 | Texas Instruments Incorporated | Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
JP4369359B2 (ja) | 2004-12-28 | 2009-11-18 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
US7816236B2 (en) * | 2005-02-04 | 2010-10-19 | Asm America Inc. | Selective deposition of silicon-containing films |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) * | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7402875B2 (en) * | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US20070090408A1 (en) * | 2005-09-29 | 2007-04-26 | Amlan Majumdar | Narrow-body multiple-gate FET with dominant body transistor for high performance |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US8101485B2 (en) | 2005-12-16 | 2012-01-24 | Intel Corporation | Replacement gates to enhance transistor strain |
KR20080089403A (ko) * | 2005-12-22 | 2008-10-06 | 에이에스엠 아메리카, 인코포레이티드 | 도핑된 반도체 물질들의 에피택시 증착 |
US20070152266A1 (en) * | 2005-12-29 | 2007-07-05 | Intel Corporation | Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers |
US7449373B2 (en) * | 2006-03-31 | 2008-11-11 | Intel Corporation | Method of ion implanting for tri-gate devices |
US7425500B2 (en) * | 2006-03-31 | 2008-09-16 | Intel Corporation | Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors |
US7422960B2 (en) | 2006-05-17 | 2008-09-09 | Micron Technology, Inc. | Method of forming gate arrays on a partial SOI substrate |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US7537994B2 (en) | 2006-08-28 | 2009-05-26 | Micron Technology, Inc. | Methods of forming semiconductor devices, assemblies and constructions |
US20080054361A1 (en) * | 2006-08-30 | 2008-03-06 | Infineon Technologies Ag | Method and apparatus for reducing flicker noise in a semiconductor device |
US7999251B2 (en) * | 2006-09-11 | 2011-08-16 | International Business Machines Corporation | Nanowire MOSFET with doped epitaxial contacts for source and drain |
JP5380827B2 (ja) | 2006-12-11 | 2014-01-08 | ソニー株式会社 | 半導体装置の製造方法 |
US20090170270A1 (en) * | 2007-12-27 | 2009-07-02 | Texas Instruments Incorporated | Integration schemes to avoid faceted sige |
US7786518B2 (en) * | 2007-12-27 | 2010-08-31 | Texas Instruments Incorporated | Growth of unfaceted SiGe in MOS transistor fabrication |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US20100078728A1 (en) * | 2008-08-28 | 2010-04-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Raise s/d for gate-last ild0 gap filling |
US20110079861A1 (en) * | 2009-09-30 | 2011-04-07 | Lucian Shifren | Advanced Transistors with Threshold Voltage Set Dopant Structures |
US8421162B2 (en) * | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
US8367528B2 (en) * | 2009-11-17 | 2013-02-05 | Asm America, Inc. | Cyclical epitaxial deposition and etch |
KR101634748B1 (ko) | 2009-12-08 | 2016-07-11 | 삼성전자주식회사 | 트랜지스터의 제조방법 및 그를 이용한 집적 회로의 형성방법 |
US8399314B2 (en) * | 2010-03-25 | 2013-03-19 | International Business Machines Corporation | p-FET with a strained nanowire channel and embedded SiGe source and drain stressors |
US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
CN102222692B (zh) * | 2010-04-14 | 2013-06-12 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
CN102376572A (zh) * | 2010-08-10 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | 制作半导体器件的方法 |
US8377783B2 (en) | 2010-09-30 | 2013-02-19 | Suvolta, Inc. | Method for reducing punch-through in a transistor device |
US11469271B2 (en) * | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US8778767B2 (en) * | 2010-11-18 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and fabrication methods thereof |
US11508605B2 (en) * | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
DE102011004322B4 (de) * | 2011-02-17 | 2012-12-06 | Globalfoundries Dresden Module One Llc & Co. Kg | Verfahren zur Herstellung eines Halbleiterbauelements mit selbstjustierten Kontaktelementen und einer Austauschgateelektrodenstruktur |
US8461875B1 (en) | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
US8574990B2 (en) | 2011-02-24 | 2013-11-05 | United Microelectronics Corp. | Method of manufacturing semiconductor device having metal gate |
US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
US8802524B2 (en) | 2011-03-22 | 2014-08-12 | United Microelectronics Corp. | Method of manufacturing semiconductor device having metal gates |
US8400219B2 (en) | 2011-03-24 | 2013-03-19 | Suvolta, Inc. | Analog circuits having improved transistors, and methods therefor |
US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
US8835266B2 (en) | 2011-04-13 | 2014-09-16 | International Business Machines Corporation | Method and structure for compound semiconductor contact |
US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
CN102891175B (zh) * | 2011-07-19 | 2016-03-16 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件及其制造方法 |
CN102891177B (zh) * | 2011-07-19 | 2016-03-02 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件及其制造方法 |
US9263566B2 (en) | 2011-07-19 | 2016-02-16 | Semiconductor Manufacturing International (Beijing) Corporation | Semiconductor device and manufacturing method thereof |
CN102891178A (zh) * | 2011-07-19 | 2013-01-23 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件及其制造方法 |
US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
US20130032876A1 (en) | 2011-08-01 | 2013-02-07 | International Business Machines Corporation | Replacement Gate ETSOI with Sharp Junction |
KR101891373B1 (ko) | 2011-08-05 | 2018-08-24 | 엠아이이 후지쯔 세미컨덕터 리미티드 | 핀 구조물을 갖는 반도체 디바이스 및 그 제조 방법 |
US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
US9847225B2 (en) * | 2011-11-15 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing the same |
US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
CN104011841B (zh) | 2011-12-21 | 2018-01-26 | 英特尔公司 | 用于形成金属氧化物半导体器件结构的鳍的方法 |
US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
JP2013138201A (ja) * | 2011-12-23 | 2013-07-11 | Imec | 置換ゲートプロセスに従って電界効果半導体デバイスを製造する方法 |
US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
CN103187290B (zh) * | 2011-12-31 | 2015-10-21 | 中芯国际集成电路制造(北京)有限公司 | 鳍片式场效应晶体管及其制造方法 |
US8735258B2 (en) * | 2012-01-05 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit resistor fabrication with dummy gate removal |
US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
US20140004677A1 (en) * | 2012-06-29 | 2014-01-02 | GlobalFoundries, Inc. | High-k Seal for Protection of Replacement Gates |
CN103578987B (zh) | 2012-07-19 | 2016-08-24 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
WO2014071049A2 (en) | 2012-10-31 | 2014-05-08 | Suvolta, Inc. | Dram-type device with low variation transistor peripheral circuits, and related methods |
US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
US8994415B1 (en) | 2013-03-01 | 2015-03-31 | Suvolta, Inc. | Multiple VDD clock buffer |
US8988153B1 (en) | 2013-03-09 | 2015-03-24 | Suvolta, Inc. | Ring oscillator with NMOS or PMOS variation insensitivity |
US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
US9112495B1 (en) | 2013-03-15 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit device body bias circuits and methods |
US9449967B1 (en) | 2013-03-15 | 2016-09-20 | Fujitsu Semiconductor Limited | Transistor array structure |
US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
US9412842B2 (en) | 2013-07-03 | 2016-08-09 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device |
US9263455B2 (en) | 2013-07-23 | 2016-02-16 | Micron Technology, Inc. | Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines |
US8976575B1 (en) | 2013-08-29 | 2015-03-10 | Suvolta, Inc. | SRAM performance monitor |
US9543410B2 (en) * | 2014-02-14 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and formation thereof |
US9112032B1 (en) * | 2014-06-16 | 2015-08-18 | Globalfoundries Inc. | Methods of forming replacement gate structures on semiconductor devices |
US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
JP6631950B2 (ja) * | 2014-12-11 | 2020-01-15 | パナソニックIpマネジメント株式会社 | 窒化物半導体装置および窒化物半導体装置の製造方法 |
US9496338B2 (en) | 2015-03-17 | 2016-11-15 | International Business Machines Corporation | Wire-last gate-all-around nanowire FET |
TWI695513B (zh) * | 2015-03-27 | 2020-06-01 | 日商半導體能源研究所股份有限公司 | 半導體裝置及電子裝置 |
KR102290685B1 (ko) | 2015-06-04 | 2021-08-17 | 삼성전자주식회사 | 반도체 장치 |
JP6903446B2 (ja) * | 2016-03-07 | 2021-07-14 | 芝浦メカトロニクス株式会社 | 基板処理装置及び基板処理方法 |
US9972513B2 (en) * | 2016-03-07 | 2018-05-15 | Shibaura Mechatronics Corporation | Device and method for treating a substrate with hydrofluoric and nitric acid |
US9768278B1 (en) * | 2016-09-06 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of Fin loss in the formation of FinFETS |
US11127590B2 (en) * | 2016-12-05 | 2021-09-21 | The Regents Of The University Of California | Method for ALD deposition on inert surfaces via Al2O3 nanoparticles |
DE102017126544B4 (de) | 2017-06-30 | 2023-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Verfahren zur herstellung von halbleitervorrichtungen |
US10714598B2 (en) | 2017-06-30 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor device |
CN108231594B (zh) * | 2017-12-21 | 2020-10-02 | 上海集成电路研发中心有限公司 | 一种FinFET器件的制作方法 |
JP2021192396A (ja) * | 2018-09-14 | 2021-12-16 | キオクシア株式会社 | 集積回路装置及び集積回路装置の製造方法 |
US11165032B2 (en) * | 2019-09-05 | 2021-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Field effect transistor using carbon nanotubes |
CN110767804B (zh) * | 2019-11-19 | 2020-11-06 | 北京元芯碳基集成电路研究院 | 一种碳纳米管器件及其制造方法 |
WO2023140840A1 (en) | 2022-01-20 | 2023-07-27 | Applied Materials, Inc. | Methods for near surface work function engineering |
Family Cites Families (294)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4198250A (en) * | 1979-02-05 | 1980-04-15 | Intel Corporation | Shadow masking process for forming source and drain regions for field-effect transistors and like regions |
JPS58201363A (ja) * | 1982-05-20 | 1983-11-24 | Sanyo Electric Co Ltd | ゲ−ト電極形成方法 |
GB2156149A (en) | 1984-03-14 | 1985-10-02 | Philips Electronic Associated | Dielectrically-isolated integrated circuit manufacture |
US4487652A (en) | 1984-03-30 | 1984-12-11 | Motorola, Inc. | Slope etch of polyimide |
US5514885A (en) * | 1986-10-09 | 1996-05-07 | Myrick; James J. | SOI methods and apparatus |
US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
US4907048A (en) * | 1987-11-23 | 1990-03-06 | Xerox Corporation | Double implanted LDD transistor self-aligned with gate |
US4905063A (en) * | 1988-06-21 | 1990-02-27 | American Telephone And Telegraph Company, At&T Bell Laboratories | Floating gate memories |
JPH0214578A (ja) * | 1988-07-01 | 1990-01-18 | Fujitsu Ltd | 半導体装置 |
US4994873A (en) * | 1988-10-17 | 1991-02-19 | Motorola, Inc. | Local interconnect for stacked polysilicon device |
US5346834A (en) | 1988-11-21 | 1994-09-13 | Hitachi, Ltd. | Method for manufacturing a semiconductor device and a semiconductor memory device |
US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
KR930003790B1 (ko) * | 1990-07-02 | 1993-05-10 | 삼성전자 주식회사 | 반도체 장치의 캐패시터용 유전체 |
US5278102A (en) * | 1990-08-18 | 1994-01-11 | Fujitsu Limited | SOI device and a fabrication process thereof |
JP3061406B2 (ja) * | 1990-09-28 | 2000-07-10 | 株式会社東芝 | 半導体装置 |
JP3202223B2 (ja) | 1990-11-27 | 2001-08-27 | 日本電気株式会社 | トランジスタの製造方法 |
US5521859A (en) * | 1991-03-20 | 1996-05-28 | Fujitsu Limited | Semiconductor memory device having thin film transistor and method of producing the same |
JPH05152293A (ja) * | 1991-04-30 | 1993-06-18 | Sgs Thomson Microelectron Inc | 段差付き壁相互接続体及びゲートの製造方法 |
US5292670A (en) | 1991-06-10 | 1994-03-08 | Texas Instruments Incorporated | Sidewall doping technique for SOI transistors |
US5179037A (en) * | 1991-12-24 | 1993-01-12 | Texas Instruments Incorporated | Integration of lateral and vertical quantum well transistors in the same epitaxial stack |
US5391506A (en) * | 1992-01-31 | 1995-02-21 | Kawasaki Steel Corporation | Manufacturing method for semiconductor devices with source/drain formed in substrate projection. |
JPH05243572A (ja) * | 1992-02-27 | 1993-09-21 | Fujitsu Ltd | 半導体装置 |
US5405454A (en) | 1992-03-19 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Electrically insulated silicon structure and producing method therefor |
JP2572003B2 (ja) | 1992-03-30 | 1997-01-16 | 三星電子株式会社 | 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法 |
JPH0793441B2 (ja) | 1992-04-24 | 1995-10-09 | ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド | 薄膜トランジスタ及びその製造方法 |
KR960002088B1 (ko) * | 1993-02-17 | 1996-02-10 | 삼성전자주식회사 | 에스오아이(SOI : silicon on insulator) 구조의 반도체 장치 제조방법 |
JPH06310547A (ja) * | 1993-02-25 | 1994-11-04 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
EP0623963A1 (de) | 1993-05-06 | 1994-11-09 | Siemens Aktiengesellschaft | MOSFET auf SOI-Substrat |
US5739544A (en) * | 1993-05-26 | 1998-04-14 | Matsushita Electric Industrial Co., Ltd. | Quantization functional device utilizing a resonance tunneling effect and method for producing the same |
US6730549B1 (en) * | 1993-06-25 | 2004-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for its preparation |
JPH0750410A (ja) * | 1993-08-06 | 1995-02-21 | Hitachi Ltd | 半導体結晶積層体及びその形成方法並びに半導体装置 |
JP3460863B2 (ja) | 1993-09-17 | 2003-10-27 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5883564A (en) * | 1994-04-18 | 1999-03-16 | General Motors Corporation | Magnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer layer |
JP3317582B2 (ja) * | 1994-06-01 | 2002-08-26 | 菱電セミコンダクタシステムエンジニアリング株式会社 | 微細パターンの形成方法 |
JP3361922B2 (ja) | 1994-09-13 | 2003-01-07 | 株式会社東芝 | 半導体装置 |
JP3378414B2 (ja) | 1994-09-14 | 2003-02-17 | 株式会社東芝 | 半導体装置 |
US5602049A (en) | 1994-10-04 | 1997-02-11 | United Microelectronics Corporation | Method of fabricating a buried structure SRAM cell |
JPH08125152A (ja) * | 1994-10-28 | 1996-05-17 | Canon Inc | 半導体装置、それを用いた相関演算装置、ad変換器、da変換器、信号処理システム |
US5728594A (en) * | 1994-11-02 | 1998-03-17 | Texas Instruments Incorporated | Method of making a multiple transistor integrated circuit with thick copper interconnect |
GB2295488B (en) | 1994-11-24 | 1996-11-20 | Toshiba Cambridge Res Center | Semiconductor device |
US5716879A (en) * | 1994-12-15 | 1998-02-10 | Goldstar Electron Company, Ltd. | Method of making a thin film transistor |
US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
JPH08204191A (ja) | 1995-01-20 | 1996-08-09 | Sony Corp | 電界効果トランジスタ及びその製造方法 |
JP3303601B2 (ja) | 1995-05-19 | 2002-07-22 | 日産自動車株式会社 | 溝型半導体装置 |
KR0165398B1 (ko) * | 1995-05-26 | 1998-12-15 | 윤종용 | 버티칼 트랜지스터의 제조방법 |
US5627097A (en) * | 1995-07-03 | 1997-05-06 | Motorola, Inc. | Method for making CMOS device having reduced parasitic capacitance |
US5658806A (en) | 1995-10-26 | 1997-08-19 | National Science Council | Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration |
US5814895A (en) | 1995-12-22 | 1998-09-29 | Sony Corporation | Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate |
KR100205442B1 (ko) | 1995-12-26 | 1999-07-01 | 구본준 | 박막트랜지스터 및 그의 제조방법 |
US5595919A (en) * | 1996-02-20 | 1997-01-21 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned halo process for reducing junction capacitance |
JPH09293793A (ja) * | 1996-04-26 | 1997-11-11 | Mitsubishi Electric Corp | 薄膜トランジスタを有する半導体装置およびその製造方法 |
JP3710880B2 (ja) * | 1996-06-28 | 2005-10-26 | 株式会社東芝 | 不揮発性半導体記憶装置 |
TW556263B (en) * | 1996-07-11 | 2003-10-01 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing the same |
US5817560A (en) * | 1996-09-12 | 1998-10-06 | Advanced Micro Devices, Inc. | Ultra short trench transistors and process for making same |
US6399970B2 (en) * | 1996-09-17 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | FET having a Si/SiGeC heterojunction channel |
US6163053A (en) | 1996-11-06 | 2000-12-19 | Ricoh Company, Ltd. | Semiconductor device having opposite-polarity region under channel |
US5827769A (en) | 1996-11-20 | 1998-10-27 | Intel Corporation | Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode |
JPH10150185A (ja) * | 1996-11-20 | 1998-06-02 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US5908313A (en) * | 1996-12-31 | 1999-06-01 | Intel Corporation | Method of forming a transistor |
JP4086926B2 (ja) | 1997-01-29 | 2008-05-14 | 富士通株式会社 | 半導体装置及びその製造方法 |
US5929526A (en) * | 1997-06-05 | 1999-07-27 | Micron Technology, Inc. | Removal of metal cusp for improved contact fill |
JPH118390A (ja) | 1997-06-18 | 1999-01-12 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6251763B1 (en) * | 1997-06-30 | 2001-06-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
US6054355A (en) * | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
JPH1140811A (ja) * | 1997-07-22 | 1999-02-12 | Hitachi Ltd | 半導体装置およびその製造方法 |
US5952701A (en) | 1997-08-18 | 1999-09-14 | National Semiconductor Corporation | Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value |
US6232233B1 (en) * | 1997-09-30 | 2001-05-15 | Siemens Aktiengesellschaft | Methods for performing planarization and recess etches and apparatus therefor |
US6066869A (en) * | 1997-10-06 | 2000-05-23 | Micron Technology, Inc. | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor |
US5976767A (en) | 1997-10-09 | 1999-11-02 | Micron Technology, Inc. | Ammonium hydroxide etch of photoresist masked silicon |
US5856225A (en) * | 1997-11-24 | 1999-01-05 | Chartered Semiconductor Manufacturing Ltd | Creation of a self-aligned, ion implanted channel region, after source and drain formation |
US6120846A (en) | 1997-12-23 | 2000-09-19 | Advanced Technology Materials, Inc. | Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition |
US5888309A (en) * | 1997-12-29 | 1999-03-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma |
US6117741A (en) | 1998-01-09 | 2000-09-12 | Texas Instruments Incorporated | Method of forming a transistor having an improved sidewall gate structure |
US6294416B1 (en) | 1998-01-23 | 2001-09-25 | Texas Instruments-Acer Incorporated | Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts |
US6097065A (en) * | 1998-03-30 | 2000-08-01 | Micron Technology, Inc. | Circuits and methods for dual-gated transistors |
US6087208A (en) | 1998-03-31 | 2000-07-11 | Advanced Micro Devices, Inc. | Method for increasing gate capacitance by using both high and low dielectric gate material |
US6215190B1 (en) | 1998-05-12 | 2001-04-10 | International Business Machines Corporation | Borderless contact to diffusion with respect to gate conductor and methods for fabricating |
US6232641B1 (en) * | 1998-05-29 | 2001-05-15 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor |
US6317444B1 (en) | 1998-06-12 | 2001-11-13 | Agere System Optoelectronics Guardian Corp. | Optical device including carbon-doped contact layers |
US6165880A (en) | 1998-06-15 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits |
US6696366B1 (en) * | 1998-08-17 | 2004-02-24 | Lam Research Corporation | Technique for etching a low capacitance dielectric layer |
US6153485A (en) | 1998-11-09 | 2000-11-28 | Chartered Semiconductor Manufacturing Ltd. | Salicide formation on narrow poly lines by pulling back of spacer |
US6200865B1 (en) * | 1998-12-04 | 2001-03-13 | Advanced Micro Devices, Inc. | Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate |
US6362111B1 (en) * | 1998-12-09 | 2002-03-26 | Texas Instruments Incorporated | Tunable gate linewidth reduction process |
TW449919B (en) * | 1998-12-18 | 2001-08-11 | Koninkl Philips Electronics Nv | A method of manufacturing a semiconductor device |
US6380558B1 (en) | 1998-12-29 | 2002-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
US6174820B1 (en) * | 1999-02-16 | 2001-01-16 | Sandia Corporation | Use of silicon oxynitride as a sacrificial material for microelectromechanical devices |
US6093621A (en) | 1999-04-05 | 2000-07-25 | Vanguard International Semiconductor Corp. | Method of forming shallow trench isolation |
US7045468B2 (en) * | 1999-04-09 | 2006-05-16 | Intel Corporation | Isolated junction structure and method of manufacture |
US6459123B1 (en) | 1999-04-30 | 2002-10-01 | Infineon Technologies Richmond, Lp | Double gated transistor |
EP1063697B1 (en) * | 1999-06-18 | 2003-03-12 | Lucent Technologies Inc. | A process for fabricating a CMOS integrated circuit having vertical transistors |
JP2001015704A (ja) | 1999-06-29 | 2001-01-19 | Hitachi Ltd | 半導体集積回路 |
US6218309B1 (en) * | 1999-06-30 | 2001-04-17 | Lam Research Corporation | Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features |
US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
TW432594B (en) | 1999-07-31 | 2001-05-01 | Taiwan Semiconductor Mfg | Manufacturing method for shallow trench isolation |
FR2799305B1 (fr) | 1999-10-05 | 2004-06-18 | St Microelectronics Sa | Procede de fabrication d'un dispositif semi-conducteur a grille enveloppante et dispositif obtenu |
US6252284B1 (en) * | 1999-12-09 | 2001-06-26 | International Business Machines Corporation | Planarized silicon fin device |
US6303479B1 (en) * | 1999-12-16 | 2001-10-16 | Spinnaker Semiconductor, Inc. | Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts |
JP4194237B2 (ja) | 1999-12-28 | 2008-12-10 | 株式会社リコー | 電界効果トランジスタを用いた電圧発生回路及び基準電圧源回路 |
US6214679B1 (en) | 1999-12-30 | 2001-04-10 | Intel Corporation | Cobalt salicidation method on a silicon germanium film |
CN100346926C (zh) * | 2000-02-23 | 2007-11-07 | 信越半导体株式会社 | 晶片的周面倒角部分的抛光方法 |
US6483156B1 (en) | 2000-03-16 | 2002-11-19 | International Business Machines Corporation | Double planar gated SOI MOSFET structure |
FR2806832B1 (fr) | 2000-03-22 | 2002-10-25 | Commissariat Energie Atomique | Transistor mos a source et drain metalliques, et procede de fabrication d'un tel transistor |
FR2810161B1 (fr) * | 2000-06-09 | 2005-03-11 | Commissariat Energie Atomique | Memoire electronique a architecture damascene et procede de realisation d'une telle memoire |
US6526996B1 (en) * | 2000-06-12 | 2003-03-04 | Promos Technologies, Inc. | Dry clean method instead of traditional wet clean after metal etch |
US6391782B1 (en) * | 2000-06-20 | 2002-05-21 | Advanced Micro Devices, Inc. | Process for forming multiple active lines and gate-all-around MOSFET |
KR100545706B1 (ko) | 2000-06-28 | 2006-01-24 | 주식회사 하이닉스반도체 | 반도체 소자 제조방법 |
WO2002003482A1 (de) | 2000-07-04 | 2002-01-10 | Infineon Technologies Ag | Feldeffekttransistor |
US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
JP2002047034A (ja) * | 2000-07-31 | 2002-02-12 | Shinetsu Quartz Prod Co Ltd | プラズマを利用したプロセス装置用の石英ガラス治具 |
US6403981B1 (en) * | 2000-08-07 | 2002-06-11 | Advanced Micro Devices, Inc. | Double gate transistor having a silicon/germanium channel region |
US6358800B1 (en) * | 2000-09-18 | 2002-03-19 | Vanguard International Semiconductor Corporation | Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit |
JP2002100762A (ja) * | 2000-09-22 | 2002-04-05 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP4044276B2 (ja) * | 2000-09-28 | 2008-02-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6562665B1 (en) * | 2000-10-16 | 2003-05-13 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology |
US7163864B1 (en) | 2000-10-18 | 2007-01-16 | International Business Machines Corporation | Method of fabricating semiconductor side wall fin |
US6413802B1 (en) | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US6396108B1 (en) * | 2000-11-13 | 2002-05-28 | Advanced Micro Devices, Inc. | Self-aligned double gate silicon-on-insulator (SOI) device |
US6472258B1 (en) | 2000-11-13 | 2002-10-29 | International Business Machines Corporation | Double gate trench transistor |
US6716684B1 (en) * | 2000-11-13 | 2004-04-06 | Advanced Micro Devices, Inc. | Method of making a self-aligned triple gate silicon-on-insulator device |
JP4597479B2 (ja) | 2000-11-22 | 2010-12-15 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6552401B1 (en) | 2000-11-27 | 2003-04-22 | Micron Technology | Use of gate electrode workfunction to improve DRAM refresh |
US6413877B1 (en) | 2000-12-22 | 2002-07-02 | Lam Research Corporation | Method of preventing damage to organo-silicate-glass materials during resist stripping |
JP2002198368A (ja) | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
US6537901B2 (en) * | 2000-12-29 | 2003-03-25 | Hynix Semiconductor Inc. | Method of manufacturing a transistor in a semiconductor device |
US6359311B1 (en) * | 2001-01-17 | 2002-03-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same |
US6524920B1 (en) | 2001-02-09 | 2003-02-25 | Advanced Micro Devices, Inc. | Low temperature process for a transistor with elevated source and drain |
US6475890B1 (en) | 2001-02-12 | 2002-11-05 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology |
US6475869B1 (en) | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
FR2822293B1 (fr) | 2001-03-13 | 2007-03-23 | Nat Inst Of Advanced Ind Scien | Transistor a effet de champ et double grille, circuit integre comportant ce transistor, et procede de fabrication de ce dernier |
US6444513B1 (en) * | 2001-03-19 | 2002-09-03 | Advanced Micro Devices, Inc. | Metal gate stack with etch stop layer having implanted metal species |
US6787402B1 (en) | 2001-04-27 | 2004-09-07 | Advanced Micro Devices, Inc. | Double-gate vertical MOSFET transistor and fabrication method |
US6902947B2 (en) * | 2001-05-07 | 2005-06-07 | Applied Materials, Inc. | Integrated method for release and passivation of MEMS structures |
SG112804A1 (en) | 2001-05-10 | 2005-07-28 | Inst Of Microelectronics | Sloped trench etching process |
KR100363332B1 (en) * | 2001-05-23 | 2002-12-05 | Samsung Electronics Co Ltd | Method for forming semiconductor device having gate all-around type transistor |
US6635923B2 (en) * | 2001-05-24 | 2003-10-21 | International Business Machines Corporation | Damascene double-gate MOSFET with vertical channel regions |
US6506692B2 (en) * | 2001-05-30 | 2003-01-14 | Intel Corporation | Method of making a semiconductor device using a silicon carbide hard mask |
US6952040B2 (en) | 2001-06-29 | 2005-10-04 | Intel Corporation | Transistor structure and method of fabrication |
JP2003017508A (ja) | 2001-07-05 | 2003-01-17 | Nec Corp | 電界効果トランジスタ |
US6534807B2 (en) * | 2001-08-13 | 2003-03-18 | International Business Machines Corporation | Local interconnect junction on insulator (JOI) structure |
US6764965B2 (en) * | 2001-08-17 | 2004-07-20 | United Microelectronics Corp. | Method for improving the coating capability of low-k dielectric layer |
US6689650B2 (en) * | 2001-09-27 | 2004-02-10 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
US6492212B1 (en) * | 2001-10-05 | 2002-12-10 | International Business Machines Corporation | Variable threshold voltage double gated transistors and method of fabrication |
JP2003142484A (ja) * | 2001-10-31 | 2003-05-16 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US20030085194A1 (en) * | 2001-11-07 | 2003-05-08 | Hopkins Dean A. | Method for fabricating close spaced mirror arrays |
US6509282B1 (en) * | 2001-11-26 | 2003-01-21 | Advanced Micro Devices, Inc. | Silicon-starved PECVD method for metal gate electrode dielectric spacer |
US7385262B2 (en) * | 2001-11-27 | 2008-06-10 | The Board Of Trustees Of The Leland Stanford Junior University | Band-structure modulation of nano-structures in an electric field |
US6967351B2 (en) | 2001-12-04 | 2005-11-22 | International Business Machines Corporation | Finfet SRAM cell using low mobility plane for cell stability and method for forming |
US6657259B2 (en) | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US6610576B2 (en) | 2001-12-13 | 2003-08-26 | International Business Machines Corporation | Method for forming asymmetric dual gate transistor |
US6583469B1 (en) * | 2002-01-28 | 2003-06-24 | International Business Machines Corporation | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same |
KR100442089B1 (ko) | 2002-01-29 | 2004-07-27 | 삼성전자주식회사 | 노치된 게이트 전극을 갖는 모스 트랜지스터의 제조방법 |
KR100458288B1 (ko) | 2002-01-30 | 2004-11-26 | 한국과학기술원 | 이중-게이트 FinFET 소자 및 그 제조방법 |
US20030151077A1 (en) | 2002-02-13 | 2003-08-14 | Leo Mathew | Method of forming a vertical double gate semiconductor device and structure thereof |
JP3782021B2 (ja) | 2002-02-22 | 2006-06-07 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、半導体基板の製造方法 |
US6635909B2 (en) * | 2002-03-19 | 2003-10-21 | International Business Machines Corporation | Strained fin FETs structure and method |
US6605498B1 (en) | 2002-03-29 | 2003-08-12 | Intel Corporation | Semiconductor transistor having a backfilled channel material |
FR2838238B1 (fr) | 2002-04-08 | 2005-04-15 | St Microelectronics Sa | Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant |
US6713396B2 (en) * | 2002-04-29 | 2004-03-30 | Hewlett-Packard Development Company, L.P. | Method of fabricating high density sub-lithographic features on a substrate |
US6537885B1 (en) * | 2002-05-09 | 2003-03-25 | Infineon Technologies Ag | Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer |
KR100410574B1 (ko) * | 2002-05-18 | 2003-12-18 | 주식회사 하이닉스반도체 | 데카보렌 도핑에 의한 초박형 에피채널을 갖는반도체소자의 제조 방법 |
US6642090B1 (en) | 2002-06-03 | 2003-11-04 | International Business Machines Corporation | Fin FET devices from bulk semiconductor and method for forming |
US7074623B2 (en) | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US7078284B2 (en) * | 2002-06-20 | 2006-07-18 | Micron Technology, Inc. | Method for forming a notched gate |
US6680240B1 (en) * | 2002-06-25 | 2004-01-20 | Advanced Micro Devices, Inc. | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
US7105891B2 (en) | 2002-07-15 | 2006-09-12 | Texas Instruments Incorporated | Gate structure and method |
US6974729B2 (en) * | 2002-07-16 | 2005-12-13 | Interuniversitair Microelektronica Centrum (Imec) | Integrated semiconductor fin device and a method for manufacturing such device |
US6705571B2 (en) * | 2002-07-22 | 2004-03-16 | Northrop Grumman Corporation | System and method for loading stores on an aircraft |
KR100477543B1 (ko) * | 2002-07-26 | 2005-03-18 | 동부아남반도체 주식회사 | 단채널 트랜지스터 형성방법 |
US6919238B2 (en) | 2002-07-29 | 2005-07-19 | Intel Corporation | Silicon on insulator (SOI) transistor and methods of fabrication |
US6921702B2 (en) | 2002-07-30 | 2005-07-26 | Micron Technology Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
EP1387395B1 (en) * | 2002-07-31 | 2016-11-23 | Micron Technology, Inc. | Method for manufacturing semiconductor integrated circuit structures |
US6777761B2 (en) * | 2002-08-06 | 2004-08-17 | International Business Machines Corporation | Semiconductor chip using both polysilicon and metal gate devices |
JP2004071996A (ja) * | 2002-08-09 | 2004-03-04 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US6833556B2 (en) | 2002-08-12 | 2004-12-21 | Acorn Technologies, Inc. | Insulated gate field effect transistor having passivated schottky barriers to the channel |
US6984585B2 (en) * | 2002-08-12 | 2006-01-10 | Applied Materials Inc | Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
US7163851B2 (en) * | 2002-08-26 | 2007-01-16 | International Business Machines Corporation | Concurrent Fin-FET and thick-body device fabrication |
US6812527B2 (en) * | 2002-09-05 | 2004-11-02 | International Business Machines Corporation | Method to control device threshold of SOI MOSFET's |
US6770516B2 (en) | 2002-09-05 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company | Method of forming an N channel and P channel FINFET device on the same semiconductor substrate |
US6794313B1 (en) | 2002-09-20 | 2004-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Oxidation process to improve polysilicon sidewall roughness |
CN1189923C (zh) | 2002-09-27 | 2005-02-16 | 上海华虹(集团)有限公司 | 一种高介电栅介质结构及其制备方法 |
JP3556651B2 (ja) * | 2002-09-27 | 2004-08-18 | 沖電気工業株式会社 | 半導体装置の製造方法 |
US6800910B2 (en) | 2002-09-30 | 2004-10-05 | Advanced Micro Devices, Inc. | FinFET device incorporating strained silicon in the channel region |
KR100481209B1 (ko) * | 2002-10-01 | 2005-04-08 | 삼성전자주식회사 | 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법 |
US6833588B2 (en) | 2002-10-22 | 2004-12-21 | Advanced Micro Devices, Inc. | Semiconductor device having a U-shaped gate structure |
US6706571B1 (en) * | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
US6706581B1 (en) * | 2002-10-29 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices |
DE10250902B4 (de) * | 2002-10-31 | 2009-06-18 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Entfernung von Strukturelementen unter Verwendung eines verbesserten Abtragungsprozess bei der Herstellung eines Halbleiterbauteils |
US6787439B2 (en) | 2002-11-08 | 2004-09-07 | Advanced Micro Devices, Inc. | Method using planarizing gate material to improve gate critical dimension in semiconductor devices |
US6611029B1 (en) | 2002-11-08 | 2003-08-26 | Advanced Micro Devices, Inc. | Double gate semiconductor device having separate gates |
US6709982B1 (en) * | 2002-11-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Double spacer FinFET formation |
US6855990B2 (en) * | 2002-11-26 | 2005-02-15 | Taiwan Semiconductor Manufacturing Co., Ltd | Strained-channel multiple-gate transistor |
US6821834B2 (en) | 2002-12-04 | 2004-11-23 | Yoshiyuki Ando | Ion implantation methods and transistor cell layout for fin type transistors |
KR100487922B1 (ko) * | 2002-12-06 | 2005-05-06 | 주식회사 하이닉스반도체 | 반도체소자의 트랜지스터 및 그 형성방법 |
US6686231B1 (en) * | 2002-12-06 | 2004-02-03 | Advanced Micro Devices, Inc. | Damascene gate process with sacrificial oxide in semiconductor devices |
US6645797B1 (en) | 2002-12-06 | 2003-11-11 | Advanced Micro Devices, Inc. | Method for forming fins in a FinFET device using sacrificial carbon layer |
US6869868B2 (en) | 2002-12-13 | 2005-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a MOSFET device with metal containing gate structures |
US6794718B2 (en) | 2002-12-19 | 2004-09-21 | International Business Machines Corporation | High mobility crystalline planes in double-gate CMOS technology |
AU2002368525A1 (en) | 2002-12-20 | 2004-07-22 | International Business Machines Corporation | Integrated antifuse structure for finfet and cmos devices |
KR100486609B1 (ko) * | 2002-12-30 | 2005-05-03 | 주식회사 하이닉스반도체 | 이중 도핑구조의 초박형 에피채널 피모스트랜지스터 및그의 제조 방법 |
US6780694B2 (en) | 2003-01-08 | 2004-08-24 | International Business Machines Corporation | MOS transistor |
US6803631B2 (en) | 2003-01-23 | 2004-10-12 | Advanced Micro Devices, Inc. | Strained channel finfet |
US6762483B1 (en) | 2003-01-23 | 2004-07-13 | Advanced Micro Devices, Inc. | Narrow fin FinFET |
US6885055B2 (en) * | 2003-02-04 | 2005-04-26 | Lee Jong-Ho | Double-gate FinFET device and fabricating method thereof |
US7304336B2 (en) | 2003-02-13 | 2007-12-04 | Massachusetts Institute Of Technology | FinFET structure and method to make the same |
US6746900B1 (en) * | 2003-02-19 | 2004-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a semiconductor device having high-K gate dielectric material |
US6855606B2 (en) * | 2003-02-20 | 2005-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor nano-rod devices |
US6716690B1 (en) * | 2003-03-12 | 2004-04-06 | Advanced Micro Devices, Inc. | Uniformly doped source/drain junction in a double-gate MOSFET |
US6787854B1 (en) | 2003-03-12 | 2004-09-07 | Advanced Micro Devices, Inc. | Method for forming a fin in a finFET device |
US6800885B1 (en) | 2003-03-12 | 2004-10-05 | Advance Micro Devices, Inc. | Asymmetrical double gate or all-around gate MOSFET devices and methods for making same |
JP4563652B2 (ja) * | 2003-03-13 | 2010-10-13 | シャープ株式会社 | メモリ機能体および微粒子形成方法並びにメモリ素子、半導体装置および電子機器 |
US6844238B2 (en) * | 2003-03-26 | 2005-01-18 | Taiwan Semiconductor Manufacturing Co., Ltd | Multiple-gate transistors with improved gate control |
US20040191980A1 (en) | 2003-03-27 | 2004-09-30 | Rafael Rios | Multi-corner FET for better immunity from short channel effects |
US6790733B1 (en) | 2003-03-28 | 2004-09-14 | International Business Machines Corporation | Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer |
US6764884B1 (en) | 2003-04-03 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
TWI231994B (en) | 2003-04-04 | 2005-05-01 | Univ Nat Taiwan | Strained Si FinFET |
US7442415B2 (en) | 2003-04-11 | 2008-10-28 | Sharp Laboratories Of America, Inc. | Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films |
US6888179B2 (en) * | 2003-04-17 | 2005-05-03 | Bae Systems Information And Electronic Systems Integration Inc | GaAs substrate with Sb buffering for high in devices |
TW200506093A (en) | 2003-04-21 | 2005-02-16 | Aviza Tech Inc | System and method for forming multi-component films |
WO2004097943A1 (ja) * | 2003-04-28 | 2004-11-11 | Matsushita Electric Industrial Co., Ltd. | 半導体装置とその製造方法 |
US7074656B2 (en) | 2003-04-29 | 2006-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
US6867433B2 (en) * | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
JP3976703B2 (ja) | 2003-04-30 | 2007-09-19 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
US6838322B2 (en) * | 2003-05-01 | 2005-01-04 | Freescale Semiconductor, Inc. | Method for forming a double-gated semiconductor device |
US6909147B2 (en) | 2003-05-05 | 2005-06-21 | International Business Machines Corporation | Multi-height FinFETS |
US7045401B2 (en) * | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
US20040262683A1 (en) | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US6960517B2 (en) | 2003-06-30 | 2005-11-01 | Intel Corporation | N-gate transistor |
US6921982B2 (en) | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
KR100487566B1 (ko) * | 2003-07-23 | 2005-05-03 | 삼성전자주식회사 | 핀 전계 효과 트랜지스터 및 그 형성 방법 |
KR100487567B1 (ko) | 2003-07-24 | 2005-05-03 | 삼성전자주식회사 | 핀 전계효과 트랜지스터 형성 방법 |
EP1519420A2 (en) * | 2003-09-25 | 2005-03-30 | Interuniversitaire Microelectronica Centrum vzw ( IMEC) | Multiple gate semiconductor device and method for forming same |
US7301206B2 (en) * | 2003-08-01 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
US6835618B1 (en) | 2003-08-05 | 2004-12-28 | Advanced Micro Devices, Inc. | Epitaxially grown fin for FinFET |
US6787406B1 (en) | 2003-08-12 | 2004-09-07 | Advanced Micro Devices, Inc. | Systems and methods for forming dense n-channel and p-channel fins using shadow implanting |
US7172943B2 (en) * | 2003-08-13 | 2007-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-gate transistors formed on bulk substrates |
KR100496891B1 (ko) | 2003-08-14 | 2005-06-23 | 삼성전자주식회사 | 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법 |
US7355253B2 (en) * | 2003-08-22 | 2008-04-08 | International Business Machines Corporation | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates |
US6998301B1 (en) * | 2003-09-03 | 2006-02-14 | Advanced Micro Devices, Inc. | Method for forming a tri-gate MOSFET |
US7170126B2 (en) * | 2003-09-16 | 2007-01-30 | International Business Machines Corporation | Structure of vertical strained silicon devices |
US7242041B2 (en) * | 2003-09-22 | 2007-07-10 | Lucent Technologies Inc. | Field-effect transistors with weakly coupled layered inorganic semiconductors |
US6970373B2 (en) | 2003-10-02 | 2005-11-29 | Intel Corporation | Method and apparatus for improving stability of a 6T CMOS SRAM cell |
US20050139860A1 (en) * | 2003-10-22 | 2005-06-30 | Snyder John P. | Dynamic schottky barrier MOSFET device and method of manufacture |
US7060576B2 (en) | 2003-10-24 | 2006-06-13 | Intel Corporation | Epitaxially deposited source/drain |
US7138320B2 (en) | 2003-10-31 | 2006-11-21 | Advanced Micro Devices, Inc. | Advanced technique for forming a transistor having raised drain and source regions |
US6867460B1 (en) * | 2003-11-05 | 2005-03-15 | International Business Machines Corporation | FinFET SRAM cell with chevron FinFET logic |
US6831310B1 (en) | 2003-11-10 | 2004-12-14 | Freescale Semiconductor, Inc. | Integrated circuit having multiple memory types and method of formation |
US6885072B1 (en) | 2003-11-18 | 2005-04-26 | Applied Intellectual Properties Co., Ltd. | Nonvolatile memory with undercut trapping structure |
US7183137B2 (en) * | 2003-12-01 | 2007-02-27 | Taiwan Semiconductor Manufacturing Company | Method for dicing semiconductor wafers |
US7075150B2 (en) | 2003-12-02 | 2006-07-11 | International Business Machines Corporation | Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique |
US7018551B2 (en) * | 2003-12-09 | 2006-03-28 | International Business Machines Corporation | Pull-back method of forming fins in FinFets |
US7388258B2 (en) * | 2003-12-10 | 2008-06-17 | International Business Machines Corporation | Sectional field effect devices |
US7247578B2 (en) | 2003-12-30 | 2007-07-24 | Intel Corporation | Method of varying etch selectivities of a film |
US7105390B2 (en) * | 2003-12-30 | 2006-09-12 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US7705345B2 (en) | 2004-01-07 | 2010-04-27 | International Business Machines Corporation | High performance strained silicon FinFETs device and method for forming same |
US7056794B2 (en) * | 2004-01-09 | 2006-06-06 | International Business Machines Corporation | FET gate structure with metal gate electrode and silicide contact |
US7385247B2 (en) | 2004-01-17 | 2008-06-10 | Samsung Electronics Co., Ltd. | At least penta-sided-channel type of FinFET transistor |
JP2005209782A (ja) | 2004-01-21 | 2005-08-04 | Toshiba Corp | 半導体装置 |
US7250645B1 (en) | 2004-01-22 | 2007-07-31 | Advanced Micro Devices, Inc. | Reversed T-shaped FinFET |
EP1566844A3 (en) | 2004-02-20 | 2006-04-05 | Samsung Electronics Co., Ltd. | Multi-gate transistor and method for manufacturing the same |
US7060539B2 (en) | 2004-03-01 | 2006-06-13 | International Business Machines Corporation | Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby |
US6921691B1 (en) | 2004-03-18 | 2005-07-26 | Infineon Technologies Ag | Transistor with dopant-bearing metal in source and drain |
US7141480B2 (en) | 2004-03-26 | 2006-11-28 | Texas Instruments Incorporated | Tri-gate low power device and method for manufacturing the same |
US8450806B2 (en) | 2004-03-31 | 2013-05-28 | International Business Machines Corporation | Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby |
US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US20050224797A1 (en) | 2004-04-01 | 2005-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS fabricated on different crystallographic orientation substrates |
US20050230763A1 (en) | 2004-04-15 | 2005-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a microelectronic device with electrode perturbing sill |
US6864540B1 (en) * | 2004-05-21 | 2005-03-08 | International Business Machines Corp. | High performance FET with elevated source/drain region |
KR100634372B1 (ko) | 2004-06-04 | 2006-10-16 | 삼성전자주식회사 | 반도체 소자들 및 그 형성 방법들 |
US7132360B2 (en) | 2004-06-10 | 2006-11-07 | Freescale Semiconductor, Inc. | Method for treating a semiconductor surface to form a metal-containing layer |
US7291886B2 (en) | 2004-06-21 | 2007-11-06 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs |
US8669145B2 (en) * | 2004-06-30 | 2014-03-11 | International Business Machines Corporation | Method and structure for strained FinFET devices |
US7084025B2 (en) * | 2004-07-07 | 2006-08-01 | Chartered Semiconductor Manufacturing Ltd | Selective oxide trimming to improve metal T-gate transistor |
US20060040054A1 (en) * | 2004-08-18 | 2006-02-23 | Pearlstein Ronald M | Passivating ALD reactor chamber internal surfaces to prevent residue buildup |
DE102004042169B4 (de) * | 2004-08-31 | 2009-08-20 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Erhöhung des Füllvermögens in einem elektrochemischen Abscheideprozess durch Verrundung der Kanten und Gräben |
US7250367B2 (en) | 2004-09-01 | 2007-07-31 | Micron Technology, Inc. | Deposition methods using heteroleptic precursors |
US7071064B2 (en) | 2004-09-23 | 2006-07-04 | Intel Corporation | U-gate transistors and methods of fabrication |
US20060289931A1 (en) * | 2004-09-26 | 2006-12-28 | Samsung Electronics Co., Ltd. | Recessed gate structures including blocking members, methods of forming the same, semiconductor devices having the recessed gate structures and methods of forming the semiconductor devices |
US20060086977A1 (en) * | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7875547B2 (en) | 2005-01-12 | 2011-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact hole structures and contact structures and fabrication methods thereof |
US7071047B1 (en) * | 2005-01-28 | 2006-07-04 | International Business Machines Corporation | Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions |
US7238564B2 (en) | 2005-03-10 | 2007-07-03 | Taiwan Semiconductor Manufacturing Company | Method of forming a shallow trench isolation structure |
US7858481B2 (en) * | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US20070023795A1 (en) * | 2005-07-15 | 2007-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
US7348642B2 (en) * | 2005-08-03 | 2008-03-25 | International Business Machines Corporation | Fin-type field effect transistor |
US7479421B2 (en) * | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US8513066B2 (en) * | 2005-10-25 | 2013-08-20 | Freescale Semiconductor, Inc. | Method of making an inverted-T channel transistor |
JP2007180310A (ja) * | 2005-12-28 | 2007-07-12 | Toshiba Corp | 半導体装置 |
KR100718159B1 (ko) * | 2006-05-18 | 2007-05-14 | 삼성전자주식회사 | 와이어-타입 반도체 소자 및 그 제조 방법 |
US20080017890A1 (en) * | 2006-06-30 | 2008-01-24 | Sandisk 3D Llc | Highly dense monolithic three dimensional memory array and method for forming |
US7655989B2 (en) * | 2006-11-30 | 2010-02-02 | International Business Machines Corporation | Triple gate and double gate finFETs with different vertical dimension fins |
-
2004
- 2004-09-29 US US10/955,669 patent/US7332439B2/en active Active
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- 2005-09-29 DE DE112005002302T patent/DE112005002302B4/de active Active
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- 2005-09-29 TW TW094133997A patent/TWI272681B/zh not_active IP Right Cessation
- 2005-09-29 CN CNA2005800324531A patent/CN101027763A/zh active Pending
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US20080142840A1 (en) | 2008-06-19 |
TW200618125A (en) | 2006-06-01 |
US20060068590A1 (en) | 2006-03-30 |
CN103560150B (zh) | 2017-01-11 |
US8344452B2 (en) | 2013-01-01 |
DE112005002302B4 (de) | 2009-07-23 |
US20160308014A1 (en) | 2016-10-20 |
DE112005002302T5 (de) | 2007-09-27 |
CN101027763A (zh) | 2007-08-29 |
WO2006039597A2 (en) | 2006-04-13 |
US20110156145A1 (en) | 2011-06-30 |
US20060068591A1 (en) | 2006-03-30 |
WO2006039597A3 (en) | 2006-07-13 |
US7915167B2 (en) | 2011-03-29 |
KR100867781B1 (ko) | 2008-11-10 |
KR20070052329A (ko) | 2007-05-21 |
US7332439B2 (en) | 2008-02-19 |
TWI272681B (en) | 2007-02-01 |
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