CN1894774A - 用于cmos的应变晶体管集成 - Google Patents
用于cmos的应变晶体管集成 Download PDFInfo
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- HNPSIPDUKPIQMN-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Al]O[Al]=O HNPSIPDUKPIQMN-UHFFFAOYSA-N 0.000 claims description 16
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Abstract
本发明各实施例涉及一种CMOS器件,该器件具有(1)选择性沉积在缓变硅着基片的第一区域上的硅材料的NMOS材料,使得选择性沉积硅材料承受由于该硅材料的晶格间距比第一区域上的缓变硅锗基片材料的晶格间距小而产生的拉伸应变,以及(2)选择性沉积在基片的第二区域上的硅锗材料的PMOS沟道,使得选择性沉积硅锗材料承受由于该选择性沉积硅锗材料的晶格间距比第二区域上的缓变硅锗基片材料的晶格间距大而产生的压缩应变。
Description
技术领域
电路器件及电路器件的制造和结构。
背景技术
提高基片上电路器件(例如,在诸如硅的半导体基片上的集成电路(IC)晶体管、电阻器、电容器等)的性能通常是在设计、制造和操作这些器件时所考虑的主要因素。例如,在设计和制造或构造诸如互补金属氧化物半导体(CMOS)中所常用的金属氧化物(MOS)晶体管半导体器件时,常常需要增加N型MOS器件(NMOS)沟道中电子的移动和增加P型MOS器件(PMOS)沟道中正电荷空穴的移动。
附图说明
本发明的各个实施例通过示例说明,但并不受到附图的限制,在附图中相似标号指示相似元件。应注意,对本说明书中本发明“一”实施例的引用并非必需是同一实施例,而表示至少一个实施例。
图1是一部分半导体基片衬底的横截面示图。
图2是基片上形成缓变(graded)硅锗材料层之后图1所示的半导体基片。
图3示出在缓变硅锗材料区域之间形成电绝缘材料之后图2所示的半导体基片。
图4示出硅材料层在选择性沉积在缓变硅锗材料的第一区域上之后图1所示的半导体基片。
图5示出硅锗材料层在选择性沉积在缓变硅锗材料的第二区域上之后图1所示的半导体基片,其中硅锗材料具有比缓变硅锗材料在第二区域上更高的锗浓度。
图6示出在选择性沉积硅和选择性沉积硅锗材料上形成高介电常数材料层之后图1的半导体基片。
图7示出在选择性沉积硅材料中形成NMOS器件和在选择性沉积硅锗材料中形成PMOS器件之后图1所示的半导体基片。
具体实施方式
图1是半导体衬底基片的局部横截面示图。如图1所示,硅基片110可包括由多晶硅、单晶硅形成或生长、或用于形成诸如硅晶片的硅衬底或基片的各种其它适当技术。例如,根据各实施例,衬底110可通过使单晶硅基片材料生长厚度H0为100埃到1000埃之间的纯硅来形成。
图2是在基片上形成缓变硅锗(SiGe)材料层之后图1所示的半导体基片。图2示出在基片衬底110的顶部形成缓变硅锗的基片材料120。例如,基片材料120可以是通过诸如半导体器件制造腔室的腔室内的缓变弛豫SiGe的化学气相沉积(CVD)外延生长所制成的缓变弛豫硅合金材料层。更具体地说,这种CVD生长可通过将基片衬底110置入腔室、在5标准升每分钟(SLM)到50SLM之间的氢气环绕流中将腔室内加热到500℃~1000℃之间的温度、(诸如通过大气压减压)使该腔室的压力处于10~200托之间、使硅先驱体(precursor)(比如在此所述的硅先驱体)以50~500SCCM的流速流入腔室、并将锗先驱体的流速从0SCCM缓慢增加到足以使上表面129具有10%~35%之间百分比的锗的最终流速流入腔室来完成的。更特别地,锗先驱体流可增加到足以使锗从诸如下表面121的0%初始浓度的缓变增加到诸如上表面129的20~30%的最终锗浓度,其中锗浓度的缓变速率为在深度上每毫米(诸如厚度H3中的每毫米)10%锗。根据各实施例,基片材料120可被视为在诸如上表面129上具有5~20%的最终锗浓度的锗浓度。
于是,根据各实施例,缓变硅锗材料的缓变速率和/或厚度可变化,以提供由下表面121上开始的选定缓变速率所导致的上表面129的最终选定锗浓度。此外,根据各实施例,缓变速率可通过缓变中的持续变化、缓变中的线性变化、缓变中的非线性变化、和/或基片材料120中锗度的阶跃缓变变化来建立。具体地说,例如,可增加锗先驱体流,使得缓变的速率可平稳连续地增加,或者使缓变速率可具有基片材料120中锗浓度的每1000~2000埃1%~2%之间增量的急剧阶跃缓变变化。此外,根据各实例,锗先驱体的初始流速、锗先驱体的流速增加、以及锗先驱体的最终流速可取决于(比如上表面129的)的基片材料120中锗的期望最终目标浓度、在形成期间使用的温度、以及锗先驱体的浓度来选择并广泛变化。
例如,在一实施例中,锗先驱体可以是锗烷(GeH4),并可在流速上随时间线性地或非线性地增加,以使上表面129具有所选定的锗百分比。此外,锗先驱体可以用H2稀释的锗烷先驱体,或者可以是增加到100SCCM或以下的最终流速的纯锗烷。实际上,有可能将锗先驱体的流速增加到使所生长的弛豫缓变硅锗薄膜在上表面129为100%锗。
类似地,根据各实施例,基片材料120可以是具有从下表面121的0%增加到上表面120的10%~30%的缓变浓度的缓变弛豫硅锗材料,其中缓变速率为在深度(诸如与厚度H3相关的深度)上每毫米增加5%~15%的锗。缓变弛豫硅锗包括“弛豫”状态的缓变硅锗,诸如其中SiGe结构(基片衬底110加基片材料120)中的硅和锗分子的对准具有相对较少的错位、甚至Ge的百分比缓变增加(比如通过平滑或阶跃缓变增加)。
此外,根据各实施例,形成缓变弛豫硅锗可包括在基片材料120的CVD外延生长期间HCl在50SCCM~100SCCM之间的流动。例如,足够量的HCl可在形成基片材料120期间引入,以增加或改进上表面129的平整度、减少或控制在弛豫硅锗生长期间发展的所谓“网状线”(诸如减少上表面129上可归因于沉积期间硅锗分子的弛豫的十字形应变或网格图案)。此外,根据各实施例,尽管上述基片材料120是由缓变硅锗所形成的,但基片材料120可通过CVD外延伸展、超高真空(UHV)CVD外延生长、和/或各种适当硅合金(比如硅锗)的分子束外延(MBE)外延生长而形成。因而,例如,基片材料120可通过各种适当硅合金材料的充分CVD形成,以形成具有厚度为1~3毫米之间的硅合金材料缓变弛豫层,诸如通过硅锗的CVD形成具有2毫米的厚度H3的缓变基片材料120。此外,基片材料120可通过适当的层转移/粘合技术形成,诸如绝缘体上基片SiGe(SGOI)处理,其中通过由适当处理在大块基片上生长SiGe、然后将SiGe的弛豫顶层转移到不同基片(诸如可以是二氧化硅晶片的基片衬底110)来准备弛豫SiGe基片,以形成基片材料120。基片材料120还被视为可以是非缓变的硅合金材料。
图2还示出上表面129具有第一区域123和第二区域125的基片材料120,这些区域适用于沉积晶体管器件半导体沟道材料。例如,图3示出在缓变硅锗材料的区域之间形成电绝缘材料之后图2所示的半导体基片。图3示出第一区域123和第二区域125之间的线沟槽绝缘(STI)材料130。尽管图3示出第一区域123和第二区域125之间的STI材料130,但可预期足以使CMOS器件的P型阱与CMOS器件的N型阱相隔离的各种适当电性能绝缘材料和结构。
然后,根据各实施例,基片材料120可在第一区域123上掺杂硼和铝之一,以形成诸如用于CMOS器件的NMOS晶体管的具有正电荷的P型阱区域122。类似地,基片材料120可在第二区域125上掺杂磷、砷、和/或锑,以形成诸如用于CMOS器件的PMOS晶体管的具有负电荷的N型阱区域124。为了有选择地掺杂第一区域123和第二区域125,可将掩模置于非选定区域上以防止沉积物质被引入到非选定的区域。
在基片材料120中形成P型阱区域122和N型阱区域124之后,可形成具有厚度适合于基片材料120的第一区域123上第一电路器件的第一沟道的硅材料层,以限定基片材料120的第一界面表面。此外,可形成适用于基片材料120的第二区域125上第二电路器件的第二沟道的硅锗层,以限定基片材料120的第二界面表面。例如,图4示出了在缓变硅锗材料的第一区域上的选择性沉积硅材料层之后图1所示的半导体基片。图4示出了在基片材料120的第二区域125上形成的第一介质层140。根据各实施例,第一介质层140可由诸如抗蚀刻和/或介质材料的材料形成,包括二氧化硅(SiO2)、氮化硅(Si3N4)、抗蚀刻介质、或其它适当介质。
在形成第一介质层140之后,可在基片材料120的第一区域123上形成第一层150。例如,如图4所示,第一层150是由拉伸应变硅的选择性CVD外延生长所形成的硅材料外延层,诸如可承受由于比第一区域123上弛豫缓变硅锗基片材料120的晶格间距小的硅材料晶格间距所引起的在箭头152和154方向上的拉伸应变的硅层。硅层的选择性CVD外延生长可包括:将不具第一层150的结构400置入腔室、在5SLM~50SLM之间的氢气环绕流中将腔室内加热到600℃~900℃之间的温度、(诸如通过大气压或减压)使该腔室的压力处于10~200托之间、并使硅先驱体以50~500SCCM的流速流入腔室以形成厚度H1为10纳米~20纳米之间的硅材料外延层。例如,第一层150可具有这样的厚度,从而在第一区域123上的第一层150与基片材料120的上表面129相耦合所限定的第一界面上足以避免第一层150和基片材料120之间的错位、错合或丝状错位。
更具体地说,形成第一层150可包括流入二氯甲硅烷(SiH2Cl2),以选择性地沉积具有100~1000埃厚度纯硅的硅材料。此外,可期望形成第一层150可包括诸如通过在拉伸应变硅的选择性CVD外延生长期间流入HCl,引入50~500SCCM之间的HCl(比如上述与形成基片材料120相关)。此外,根据各实施例,尽管如上所述第一层150可通过CVD外延生长形成,但第一层150可通过其它适当工艺来形成,包括本文所述的UHV CVD外延生长、SGOI、和/或MBE外延生长,以形成硅层。
同样,根据各实施例,第一层150可包括在第一区域123上形成时承受拉伸应变的其它适当硅材料。
在形成第一层150之后,第二介质层可在第一层150上形成,然后可在基片材料120的第二区域125上形成适用于第二电路器件的第二沟道的硅锗材料层。例如,图5示出在缓变硅锗材料的第二区域上的选择性沉积硅锗材料层之后图1所示的半导体基片,其中硅锗材料具有比缓变硅锗材料在第二区域上更高的锗浓度。图5示出适用于在缓变硅锗基片材料120的第二区域125上形成的第二电路器件的第二沟道的不同第二层160,以及在第一区域123的第一层150上共同形成的第二介质层142。根据各实施例,第二介质层142可在第一层150的表面上共同地沉积,因为第二介质层142的厚度全部一致,并符合第一层150表面的外形。
特别地,图5示出第二层160,诸如可通过压缩应变硅锗的选择性CVD外延生长形成的硅合金材料外延层。例如,通过将不具第二层160的结构500置入腔室,在5SLM~50SLM之间氢气环绕(H2)流中使腔室内加热到500℃~800℃之间的温度、(诸如通过大气压或减压)使该腔室的压力处于10~200托之间、使硅先驱体以50~500SCCM的流速流入腔室并以高达100SCCM(未加稀释的)流速使先驱体流入,以使第二层160具有20%~60%之间百分比的锗。因而,可形成诸如具有足够锗百分比的第二层160,以使第二层160可承受由于比第二区域125上缓变硅锗基片材料120的晶格间距大的硅合金材料外延层的晶格间距所引起的在箭头162和164方向的压缩应变。具体地,第二层160的形成可包括锗先驱体以这样的速度流动,使第二层160为厚度H2在10纳米~20纳米之间的硅锗材料外延层。因此,第二层160可具有这样的厚度,从而在第二区域125上的第二层160与基片材料120的上表面129相耦合的限定的第二界面上足以避免错位、错合或丝状错位。
可以理解,使硅先驱体流动用于形成第二层160可包括以诸如上述相对于流动硅先驱体形成基片初底110和第一层150的速率来使先驱体流入或流动。更具体地,例如,上述用于形成第二层160的硅先驱体可以是在与锗先驱体流入组合时以足够使硅锗材料形成来提供具有厚度H2为100~1000埃硅锗材料的第二层160的速率流入的二氯甲硅烷(SiH2Cl2)。类似地,与形成第二层160相关的上述锗先驱体的流入可包括使锗先驱体流入、或以与上述流入的锗先驱体相关的流速使锗先驱体流入,以形成缓变的硅锗基片材料120。具体地说,例如,所流入的锗先驱体而形成第二层160可包括使锗烷(GeH4)流入而足以使第二层160具有选定百分比的锗和选定厚度(比如通过与形成与形成图2的缓变硅锗基片材料相关地使锗烷流入)。
此外,可期望形成第二层160可包括引入50~500SCCM之间的HCl,如上述与形成图4第一层150相关。另外,根据各实施例,尽管上述第二层160为由缓变硅锗形成,但第二层160可通过各种适当硅合金(例如硅锗)的CVD外延生长、UHV CVD外延生长、SGOI、和/或MBE外延生长来形成。
除了在上述第一区域123和第二区域125上掺杂之外,根据各实施例,可用“自对准”(self-aligned)方式进行掺杂,诸如不用附加掩模的方式。例如,图4所示的第一介质140可在图3的晶片300上沉积(例如包括第一区域123和第二区域125)。然后,保护层(例如光致抗蚀剂)可旋涂并暴露在P阱122上。然后去除保护层并蚀刻第一介质140,以暴露P阱122上的第一区域123。然后,可进行离子注入以掺杂P阱122(比如用上述用于掺杂第一区域123的掺杂物)。从晶片300剥去剩下的保护层,且第一层150如图4所示地选择性沉积。此外,当形成第二介质142和第二层160时可使用相似工艺来掺杂第二区域125(比如用上述用于掺杂第二区域125的掺杂物),并产生图5所示的结构。可以理解,上述某些“自对准”掺杂工艺的顺序可颠倒。
此外,根据各实施例,对松弛豫硅锗基片材料中(比如,诸如通过平滑或阶跃缓变Ge百分比增加的、具有Ge百分比增加的基片材料120)锗的增加百分比或缓变浓度,以及缓变弛豫硅锗基片材料和沟道SiGe之间界面上锗的突然增加(诸如在第二区域125上具有比基片材料120高例如10%~30%之间锗百分比的第二层160上的突然增加)进行区分。因而,沟道SiGe材料(例如第二层160)可形成与缓变弛豫基片材料SiGe的相干对准(比如在基片材料120的第二区域125;其中基片材料120也可在缓变基片内诸如沿厚度H3相干对准),但由于基片/沟道界面处(比如第二区域125接触第二层160之处)沟道材料和基片材料之间锗百分比的跃变而将承受压缩应变162和164。另外,尽管以上对形成第二层160的描述集中于形成硅锗层,但根据各实施例。第二层160可由各种适当硅合金材料形成,诸如通过这种材料的选择性外延CVD。
注意,第一层150和/或第二层160可在形成第一区域123和第二区域125之间的电绝缘区域之后(比如在形成STI材料130之前)形成,使得用于形成电绝缘区域的高温处理将不是减少选定厚度、或第一层150中拉伸应变和/或第二层160中压缩应变的引入弛豫的一个因素。此外,可以理解,第一层150和/或第二层160在第一区域123和第二区域125上的选择性形成可包括选定为足够小以增大或提供第一层150的充分稳定性的第一区域123的尺寸和第二区域125的尺寸,以允许在第一区域123上具有选定锗百分比的驰预缓变硅锗基片材料120的缓冲区上的拉伸应变沉积、和允许在第二区域125上具有选定锗百分比的弛豫缓变硅锗基片材料120的缓冲区上的压缩应变沉积,其中第二区域125上的选定锗百分比约等于第一区域123上的选定锗百分比。
此外,第一层150可用硼和/或铝掺杂以形成具有正电荷的P型阱区域(参见上述第一介质层140),而第二层160可用磷、砷、和/或锑掺杂,以形成具有负电荷的N型阱区域。例如,第一层150和/或第二层160可通过引入以上在沉积期间相同的参杂物来掺杂、或用在沉积第一层150和/或第二层160之后相同的掺杂物掺杂。因而,第一层150和/或第二层160可用足量的适当类型掺杂物掺杂,以诸如为NMOS器件和/或PMOS器件分别形成N型沟道区域和/或P型沟道区域,用于CMOS电路。具体地说,例如,第一层150和、或第二层160可用沟道材料的1×1017和1×1018每立方厘米掺杂物粒子进行掺杂。因而,这种掺杂可用少于将因过度杂质散布而导致退化载流子迁移率的掺杂物粒子量来进行。
在形成第二层160之后,第三介质层可在第一层150和不同第二层160上形成。例如,图6示出在选择性沉积硅和选择性沉积硅锗材料上形成高介电常数材料层之后图1所示的半导体基片。图6示出第三介质层144,诸如具有相对较高介电常数的介质材料层(例如“高K介质”,K大于或等于3.9和/或二氧化硅(SiO2)的K),厚度为2~4纳米,在第一层150和第二层160上形成。第三介质层144可通过原子层沉积(ALD)来形成,诸如通过二氧化硅(SiO2)、氧化铪(HfO)、硅酸铪(HfSiO4)、四硅酸铪(HfSi4O7)、氧化锆(ZrO)、硅酸锆(ZrSiO4)、氧化钽(Ta2O5)。
图7示出在选择性沉积硅材料中形成NMOS器件和在选择性沉积硅锗材料中形成PMOS器件之后图1所示的半导体基片。图7示出掺杂后形成P型沟道区域176的第一层150和掺杂后形成N型沟道区域186的第二层160。图7还示出在第一层150上的第三介质层144的表面上具有N型栅电极170(例如具有负电荷的N型栅电极170)、在第一层150中与N型栅电极170相邻的N型第一结区172和第二结区174(诸如具有负电荷的N型第一结区172和第二结区174)的NMOS器件178。图7还示出在N型栅电极170的表面上形成的NMOS隔离片712和714。类似地,图7示出在第二层160上的第三介质层144的表面上具有P型栅电极180(例如其中P型栅电极180具有负电荷)、在第二层160中与P型栅电极180相邻的P型第一结区182和P型第二结区184(诸如其中P型第一结区182和P型第二结区184(诸如其中P型第一结区182的第二结区184具有负电荷)的PMOS器件188。图7还示出在P型栅电极180的表面上形成的PMOS隔离片412和414。
因而,根据各实施例,第一层150可形成为适用作基片材料120的第一区域123上的NMOS器件178的P型沟道区域176,第一层150具有与限定基片的第一界面表面(比如在第一区域123)的基片材料的基片晶格间距不同(诸如比之小)的第一晶格间距的第一材料。类似地,第二层160可形成为适用作基片材料120的不同第二区域125上的PMOS器件188的N型沟道区域186,第二层160具有与第一层的第一晶格间距不同且与基片材料的基片晶格间距不同的第二晶格间距的不同第二材料(比如,第二晶格间距具有比基片材料大的晶格间距),其中第二层限定基片的第二界面表面(比如在第二区域125)。显然,第一层150的第一晶格间距与第一区域123上基片晶格间距的差异可限定第一层150中箭头152和154方向上的拉伸应变,该拉伸应变足以增强或增加第一层150中的电子迁移率(诸如至少50%、75%、80%或85%)。类似地,第二层160的第二晶格间距和第二区域125上基片晶格间距之间的差异可限定第二层160中箭头162和164所示方向上的压缩应变,该压缩应变足以增强或增加第一层150中的空穴迁移率(诸如至少50%、80%、90%、100%或110%)。
此外,可以理解,第一层150中的拉伸应变可以是双轴拉伸应变,诸如在箭头152和154方向上、以及在指向观察者并离开图5-7所示的第一层150的横截面的箭头方向上向外拉伸或扩展第一层150。类似地,可以理解,第二层160中的压缩应变可以是双轴压缩应变,诸如在箭头162和164方向上、以及在离开观察者并指向图5-7所示的第二层160的横截面的箭头方向上向内收缩或挤压第二层160。更特别地,基片材料120的厚度、锗在上表面129上的浓度、第一层150的厚度、第二层160的厚度、以及锗在第二层160中的百分比如本文所述地作选择,使得两维相干拉伸应变因第一层150在第一区域123与基片材料120接合而在第一层150中感生(比如在第一区域123用基片材料120的原子结构排列的第一层150材料的原子结构引起的相干应变,虽然第一层150的材料具有比第一区域123的材料更小晶格间隔的晶格对准)。类似地,以上选择可作成:两维相干压缩应变因第二层160在第二区域125与基片材料120接合而在第二层160中感生(比如在第二区域125用基片材料120的原子结构排列的第二层160材料的原子结构引起的相干应变,虽然第二层160的材料具有比第二区域125的材料更大晶格间隔的晶格对准)。
因此,对于Si1-XGeX的基片材料、第一材料硅、和第二材料Si1-YGeY,其中10X表示锗在第一区域123和第二区域125上缓变硅锗基片材料120中的百分比,而10Y表示锗在接近第二域125的第二层160中的百分比,X可比Y小。例如,X可以为0.1~0.3,而Y为0.2~0.6。在一些实施例中,Y可以大于X为0.1~0.3。此外,在一实施例中,X可以为0.2而Y可以为0.5。
在前面说明书中,本发明参照其特定实施例进行了描述。然而,显然可对其作各种更改和改变,而不背离本发明如权利要求中所述的更精神和范围。因此,说明书和附图被视为是说明性的,而非限制性意义。
Claims (31)
1.一种方法,包括:
将第一层形成为适用作基片的第一区域上的第一电路器件的第一沟道,所述第一层包括具有与限定所述基片的第一界面表面的基片材料的基片晶格间距不同的第一晶格间距的第一材料;以及
将第二层形成为适用作基片的不同第二区域上的第二电路器件的第二沟道,所述第二层包括具有与第一晶格间距不同,且与限定所述基片的第二界面表面的基片材料的基片晶格间距不同的第二晶格间距的不同第二材料。
2.如权利要求1所述的方法,其特征在于,所述第一晶格间距和所述基片晶格间距之间的差异限定所述第一材料中的拉伸应变,且其中所述第二晶格间距和所述基片晶格间距之间的差异限定所述第二材料中的压缩应变。
3.如权利要求1所述的方法,其特征在于,所述基片材料包括缓变硅合金材料;
其中形成所述第一层包括沉积足够厚度的硅材料,以导致所述第一层中的双轴拉伸应变;以及
其中形成所述第二层包括沉积足够厚度的具有一定合金百分比的硅合金材料,以导致所述第二层中的双轴相干压缩应变。
4.如权利要求1所述的方法,其特征在于,所述基片材料是缓变硅合金材料,它具有足够厚度,并在第一和第二区域上具有在一合金百分比上足够增加到最终的合金百分比,以导致所述第一层中的双轴拉伸应变以及所述第二层中的双轴相关压缩应变。
5.如权利要求1所述的方法,其特征在于,所述基片材料包括Si1-XGeX,所述第一材料包括硅,所述第二材料包括Si1-YGeY,且X<Y。
6.如权利要求5所述的方法,其特征在于,X为0.1到0.3之间,而Y为0.2到0.6之间。
7.如权利要求1所述的方法,还包括通过硅合金材料的充分化学气相沉积以形成硅合金材料的缓变弛豫层来形成所述基片材料。
8.如权利要求7所述的方法,其特征在于,形成硅合金材料的缓变弛豫层包括:
缓变弛豫SiGe的化学气相沉积(CVD)外延生长包括:
在5标准升每分钟(SLM)到50SLM之间的氢气环绕流中将所述基片加热到500°到1000°之间的温度;
使所述基片的压力处于10到200托之间;
使硅先驱体以50标准立方厘米/分钟(SCCM)到500SCCM的流速流入;以及
使锗先驱体的流速从0SCCM缓慢增加到足以使所述基片的第一界面表面和第二界面表面具有10%到35%之间百分比的锗的最终流速。
9.如权利要求8所述的方法,其特征在于,所流入的硅先驱体包括流入硅烷(SiH4)、乙硅烷(Si2H6)、以及二氯甲硅烷(SiH2Cl2)之一,以沉积具有100到1000埃厚度纯硅的基片衬底材料。
10.如权利要求8所述的方法,其特征在于,增加锗先驱体的流速包括将锗烷(GeH4)的流速从0SCCM增大至足以使第一界面表面和所述基片的第二界面表面具有所述百分比的锗。
11.如权利要求7所述的方法,其特征在于,所形成的缓变弛豫SiGe包括在SiGe的化学气相沉积(CVD)外延生长期间流入50SCCM到100SCCM之间的HCl。
12.如权利要求1所述的方法,其特征在于,形成所述第一层包括硅材料的充分选择性化学气相沉积,以形成硅材料在所述第一区域上的外延层。
13.如权利要求12所述的方法,其特征在于,形成硅材料的外延层包括:
拉伸应变Si的选择性化学气相沉积(CVD)外延生长包括:
在5标准升每分钟(SLM)到50SLM之间的氢气环绕流中将所述基片加热到600°到900°之间的温度;
使所述基片的压力处于10到200托之间;
使硅先驱体以50标准立方厘米/分钟(SCCM)到500SCCM的流速流入。
14.如权利要求13所述的方法,其特征在于,使硅先驱体流入包括流入二氯甲硅烷(SiH2Cl2),以沉积具有100到1000埃厚度纯硅的基片衬底材料。
15.如权利要求12所述的方法,其特征在于,形成硅材料的外延层包括在拉伸应变Si的化学气相沉积(CVD)外延生长期间流入50到500SCCM之间的HCl。
16.如权利要求1所述的方法,其特征在于,形成所述第二层包括硅合金材料的充分选择性化学气相沉积,以形成硅合金材料在所述第二区域上的外延层。
17.如权利要求16所述的方法,其特征在于,形成硅合金材料的外延层包括:
压缩应变SiGe的化学气相沉积(CVD)外延生长包括:
在5标准升每分钟(SLM)到50SLM之间的氢气环绕流中将所述基片加热到500°到800°之间的温度;
使所述基片的压力处于10到200托之间;
使硅先驱体以50标准立方厘米/分钟(SCCM)到500SCCM的流速流入;以及
以高达100标准立方厘米/分钟(SCCM)的流速使锗先驱体流入,以使第二层具有20%到50%之间百分比的锗。
18.如权利要求17所述的方法,其特征在于,所流入的硅先驱体包括流入二氯甲硅烷(SiH2Cl2),以沉积具有100到1000埃厚度SiGe的SiGe材料。
19.如权利要求17所述的方法,其特征在于,所流入的锗先驱体包括流入锗烷(GeH4),以使所述第二层沉积具有100到1000埃厚度的SiGe材料。
20.如权利要求16所述的方法,其特征在于,形成硅合金材料的外延层包括在拉伸应变Si的化学气相沉积(CVD)外延生长期间流入50到500SCCM之间的HCl。
21.如权利要求1所述的方法,还包括:
在形成所述第一层之前形成缓变SiGe材料的基片;以及
在形成所述第一层之前形成所述第一区域和所述第二区域之间的电绝缘材料。
22.如权利要求21所述的方法,还包括:
在所述第一区域上用硼和铝之一掺杂,以形成具有正电荷的P型阱区域;以及
在所述第二区域上用磷、砷和锑之一掺杂,以形成具有负电荷的N型阱区域。
23.如权利要求22所述的方法,还包括:
在形成所述第一层之前在所述基片的不同第二区域上形成第一介质层;
在形成所述不同第二层之前在所述第一层上形成第二介质层;
在所述第一层和所述不同第二层上形成第三介质层;
其中,所述第三介质层通过二氧化硅(SiO2)、氧化铪(HfO)、硅酸铪(HfSiO4)、四硅酸铪(HfSi4O7)、氧化锆(ZrO)、硅酸锆(ZrSiO4)、氧化钽(Ta2O5)之一的原子层沉积(ALD)形成。
24.如权利要求23所述的方法,还包括:
用硼和铝之一掺杂所述第一层,以形成具有正电荷的P型阱区域;
用磷、砷和锑之一掺杂所述第二层,以形成具有负电荷的N型阱区域;
在所述第一层上的第三介质层的表面上形成N型栅电极;
在与所述N型栅电极相邻的第一层中形成N型第一结区和N型第二结区;
在所述第二层上的第三介质层的表面上形成P型栅电极;
在与所述P型栅电极相邻的第二层中形成P型第一结区和P型第二结区。
25.如权利要求1所述的方法,还包括通过以下来形成所述基片材料:
在大块基片上生长第一厚度的SiGe;
将弛豫顶层厚度的所述SiGe材料转移到包括绝缘体材料的基片上。
26.一种装置,包括:
硅材料层,适用作Si1-XGeX材料的第一区域上的第一电路器件的第一沟道,以限定缓变弛豫硅锗材料的基片的第一界面表面;
其中,所述硅材料层处于由于所述硅材料的晶格间距比所述第一界面上Si1-XGeX材料的晶格间距小而产生的拉伸应变。
27.如权利要求26所述的装置,还包括Si1-YGeY材料层,适用作Si1-XGeX材料的第二区域上的第二电路器件的第二沟道,以限定缓变弛豫硅锗材料的基片的第二界面表面;
其中,所述Si1-YGeY材料层处于由于所述Si1-YGeY材料层的晶格间距比所述第一界面上Si1-XGeX材料的晶格间距大而产生的压缩应变。
28.如权利要求27所述的装置,其特征在于,所述硅材料层是具有10纳米到20纳米之间厚度的硅材料外延层;且其中所述Si1-YGeY材料层是具有10纳米到20纳米之间厚度的Si1-YGeY材料外延层。
29.一种装置,包括:
Si1-YGeY材料层,适用作Si1-XGeX材料的第二区域上的第二电路器件的第二沟道,以限定缓变弛豫硅锗材料的基片的第二界面表面;
其中,所述Si1-YGeY材料层处于由于所述Si1-YGeY材料层的晶格间距比所述第一界面上Si1-XGeX材料的晶格间距大而产生的压缩应变。
30.如权利要求29所述的装置,其特征在于,X为0.2而Y为0.5。
31.如权利要求29所述的装置,其特征在于,所述缓变弛豫硅锗材料具有以下之一:厚度为1微米到3微米之间、锗的缓变浓度在第一和第二界面之间从0%增加到10%到30%之间、以及缓变浓度速率为在深度上每微米增加5%到15%的锗。
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CN101527280B (zh) * | 2008-03-06 | 2011-07-13 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
US7993998B2 (en) | 2008-03-06 | 2011-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS devices having dual high-mobility channels |
CN101847605A (zh) * | 2009-03-27 | 2010-09-29 | 国际商业机器公司 | 用于正规化半导体器件中的应变的方法以及半导体器件 |
CN101847605B (zh) * | 2009-03-27 | 2014-01-15 | 国际商业机器公司 | 用于正规化半导体器件中的应变的方法以及半导体器件 |
CN102163619A (zh) * | 2010-02-19 | 2011-08-24 | 三星电子株式会社 | 晶体管及其制造方法 |
CN102163619B (zh) * | 2010-02-19 | 2015-06-10 | 三星电子株式会社 | 晶体管及其制造方法 |
CN101976667B (zh) * | 2010-09-06 | 2012-07-18 | 清华大学 | 一种高性能cmos器件 |
CN101976667A (zh) * | 2010-09-06 | 2011-02-16 | 清华大学 | 一种高性能cmos器件 |
CN105206583A (zh) * | 2015-08-28 | 2015-12-30 | 西安电子科技大学 | 基于SOI的应变Si沟道倒梯形栅CMOS集成器件及制备方法 |
CN109314133A (zh) * | 2016-06-30 | 2019-02-05 | 英特尔公司 | 具有后道晶体管的集成电路管芯 |
CN112542482A (zh) * | 2020-12-02 | 2021-03-23 | 海宁波恩斯坦生物科技有限公司 | 一种无源空腔型单晶FBAR与有源GaN HEMT的单片异质异构集成结构 |
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DE112004002373B4 (de) | 2010-09-16 |
JP2007515808A (ja) | 2007-06-14 |
WO2005067014A1 (en) | 2005-07-21 |
US7662689B2 (en) | 2010-02-16 |
TWI256140B (en) | 2006-06-01 |
US8373154B2 (en) | 2013-02-12 |
US9112029B2 (en) | 2015-08-18 |
US20130153965A1 (en) | 2013-06-20 |
JP5175367B2 (ja) | 2013-04-03 |
JP2011142325A (ja) | 2011-07-21 |
US20100044754A1 (en) | 2010-02-25 |
CN100583395C (zh) | 2010-01-20 |
CN101714528A (zh) | 2010-05-26 |
KR20060103936A (ko) | 2006-10-04 |
DE112004002373T5 (de) | 2006-11-16 |
CN101714528B (zh) | 2014-04-30 |
KR100940863B1 (ko) | 2010-02-09 |
US20140239345A1 (en) | 2014-08-28 |
US8748869B2 (en) | 2014-06-10 |
US20050136584A1 (en) | 2005-06-23 |
TW200527684A (en) | 2005-08-16 |
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