CN109074332A - 包含命令延迟调整电路的方法及设备 - Google Patents

包含命令延迟调整电路的方法及设备 Download PDF

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CN109074332A
CN109074332A CN201780026103.7A CN201780026103A CN109074332A CN 109074332 A CN109074332 A CN 109074332A CN 201780026103 A CN201780026103 A CN 201780026103A CN 109074332 A CN109074332 A CN 109074332A
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CN109074332B (zh
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石桥秋
石桥秋一
宫野孝
宫野一孝
富士广木
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Micron Technology Inc
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Abstract

本发明揭示用于控制半导体装置中的输入信号路径上的等待时间的设备。一种实例性设备包含：时钟输入缓冲器，其基于外部时钟信号而提供参考时钟信号及系统时钟信号；命令解码器，其利用所述系统时钟信号锁存命令信号且基于所述命令信号而进一步提供信号；及命令延迟调整电路，其包含：时钟同步电路，所述时钟同步电路接收所述信号、利用所述系统时钟信号锁存所述信号且响应于移位循环参数而提供经时钟同步读取信号。

Description

包含命令延迟调整电路的方法及设备
背景技术
高数据可靠性、高存储器存取速度及低电力消耗为半导体存储器所需求的特征。近年来，已努力进一步增加存储器存取速度。半导体装置中的许多同步集成电路基于时钟信号而执行操作以满足关键时序要求。
为了评定脉冲信号发射系统的性能，可对窗口或“数据眼”图案进行评估。针对数据信号中的每一者的数据眼定义了在考虑影响信号的各种因素(例如，时序偏斜、电压及电流驱动能力)之后的每一信号有效的实际持续时间。在信号时序偏斜的情形中，其通常由多种时序误差(例如总线的各线上的负载及此类线的物理长度)引起。举例来说，可使用秩裕度测试(RMT)来评估窗口以便评定半导体装置中的输入缓冲器的性能容差。在RMT中，可使参考电压(VREF)电平从输入高电压(VIH)与输入低电压(VIL)之间的中点变化以测试RMT的裕度作为性能容差。只要参考电压处于预定范围内，即使参考电压移位，输入缓冲器仍需要在无任何误差的情况下进行操作。
图1是包含命令延迟调整电路130的设备100的框图。设备100可包含时钟输入缓冲器110、命令输入缓冲器111、命令解码器电路120、命令延迟调整电路130、针对命令信号及时钟信号的信号树190及191以及输出缓冲器195。
命令延迟调整电路130可包含DLL时钟路径及命令路径。DLL时钟路径可包含命令副本121，及用于时钟信号的延迟线141。命令副本121复制命令解码器电路120的延迟以响应于命令信号CMD及系统时钟信号SCLK_CMD信号而提供RdClk信号。命令副本121可使SCLK_DLL信号延迟且将经延迟系统时钟信号SCLKD提供到延迟线141。命令路径包含用于命令信号的延迟线140以及dQ-启用-延迟(QED)电路160。命令延迟调整电路130进一步包含与用于时钟信号的延迟线141一起形成DLL电路的DLL时钟路径副本151、相位检测器170及DLL控制电路180。
命令延迟调整电路130可使dQ-启用-延迟电路160的输出信号与来自延迟线141的DLL时钟信号DllClk同步，同时在dQ-启用-延迟电路160的输出信号上提供等待时间。等待时间在此处为(举例来说)可基于时钟信号CK的时钟频率而被设定的列地址选通(CAS)等待时间(CL)。CL值可计及在存储器接收到READ(读取)命令时与在输出缓冲器195响应于READ命令而将读取数据提供到输出总线(例如，经由在输出缓冲器195之后的DQ垫)时之间的延迟时间。CL值可被表示为时钟循环的数目。一个时钟循环可由T表示。
然而，存在以下副效应：增加来自命令副本121的SCLKD信号的抖动，且增加有效待机电流(例如，IDD3N)。SCLKD信号中的抖动又增加DLL时钟信号DllClk的抖动，此导致RMT的裕度降低。因此，通过添加命令副本121而实现的较高存储器存取速度可导致RMT的裕度降低，伴有较高电力消耗。
发明内容
根据本发明的实施例的一种实例性设备可包含：第一电路，其可经配置以对第一时钟信号做出响应以锁存第一信号，所述第一电路可经配置以提供第二信号；及第二电路，其可耦合到所述第一电路以锁存所述第二信号，所述第二电路可经配置以响应于与所述第一时钟信号大体上同相的第一输出时序信号基于所述第二信号而提供第三信号。
根据本发明的实施例的另一实例性设备可包含：时钟输入缓冲器，其可经配置以基于外部时钟信号而提供参考时钟信号及系统时钟信号；命令解码器，其可经配置以响应于所述系统时钟信号而锁存命令信号且进一步经配置以基于所述命令信号而提供信号；及命令延迟调整电路。所述命令延迟调整电路可包含：时钟同步电路，其可经配置以从所述命令解码器接收所述信号、经配置以响应于所述系统时钟信号而锁存所述信号且进一步经配置以响应于移位循环参数而提供经时钟同步读取信号。
根据本发明的实施例的一种实例性方法可包含：在时钟输入缓冲器中基于外部时钟信号而提供参考时钟信号及系统时钟信号；响应于所述系统时钟信号而锁存命令信号；基于所述命令信号而提供信号；响应于所述系统时钟信号而锁存所述信号；及响应于移位循环参数、响应于等待时间信息而提供经时钟同步读取信号。
附图说明
图1是在读取操作中的包含命令延迟调整电路的设备的框图。
图2是根据本发明的实施例的包含命令延迟调整电路的设备的框图。
图3是根据本发明的实施例的时钟同步电路的框图。
图4A是根据本发明的实施例的时钟同步电路中的输入指针寄存器的单元的图式。
图4B是根据本发明的实施例的图4A的输入指针寄存器的单元中的信号的时序图。
图5是根据本发明的实施例的包含命令延迟调整电路的设备中的命令解码器电路的电路图。
图6是根据本发明的实施例的包含命令延迟调整电路的设备中的信号的时序图。
具体实施方式
下文将参考附图更详细地描述本发明的各种实施例。以下详细描述参考附图，附图以图解说明方式展示其中可实践本发明的特定方面及实施例。充分详细地描述这些实施例以使所属领域的技术人员能够实践本发明。在不背离本发明的范围的情况下，可利用其它实施例，且可做出结构、逻辑及电学上的改变。本文中所揭示的各种实施例未必相互排斥，这是因为一些所揭示实施例可与一或多个其它所揭示实施例组合以形成新的实施例。
图2是根据本发明的实施例的包含命令延迟调整电路230的设备200的框图。设备200可包含时钟输入缓冲器210、命令输入缓冲器211、第一电路220(其还可在本文中称为命令解码器电路)、命令延迟调整电路230、针对命令信号及时钟信号的信号树290及291，以及输出缓冲器295。时钟输入缓冲器210接收时钟信号CK、互补时钟信号CKB(此两者均为外部时钟信号)，且进一步接收互补复位信号RESETB。时钟输入缓冲器210基于来自命令解码器电路220的READ命令而进一步接收启用信号Rdi。时钟输入缓冲器210可至少部分地响应于时钟信号CK及互补时钟信号CKB而提供系统时钟信号SCLK_CMD及参考时钟信号SCLK_DLL。系统时钟信号SCLK_CMD与参考时钟信号SCLK_DLL可彼此同步或彼此同相。时钟输入缓冲器210可至少部分地响应于启用信号Rdi而启用或停用提供参考时钟信号SCLK_DLL。命令输入缓冲器211接收第一信号(其还可在本文中称为命令信号CMD)、参考电压VREF以及互补信号RESETB或时钟启用信号CKE。命令输入缓冲器211将命令信号CMD提供到命令解码器电路220。命令解码器电路220接收系统时钟信号SCLK_CMD及命令信号CMD。命令解码器电路220响应于系统时钟信号SCLK_CMD而将命令信号CMD上的命令解码，以在第二信号(其还可在本文中称为命令延迟线输入信号RdClk)上提供脉冲。如较早所描述，命令解码器电路220可响应于用于READ操作的命令信号而提供启用信号Rdi。
命令延迟调整电路230可包含DLL时钟路径及命令路径。DLL时钟路径可包含用于时钟信号的延迟线电路241。命令路径包含第二电路231(其还可在本文中称为时钟同步电路)、用于命令信号的延迟线电路240及第三电路260(其还可在本文中称为QED电路)。命令延迟调整电路230进一步包含选择器控制信号产生器电路232、DLL时钟路径副本251、相位检测器270及延迟控制电路280(其还可在本文中称为DLL控制电路)。DLL时钟路径副本251、相位检测器270及DLL控制电路280与用于时钟信号的延迟线241一起形成DLL电路。时钟同步电路231从命令解码器电路220接收命令延迟线输入信号RdClk、从时钟输入缓冲器210接收系统时钟信号SCLK_CMD且从选择器控制信号产生器电路232接收移位循环参数X(X[3:0])。提供时钟同步电路231以吸收由命令解码器电路220中的命令解码及锁存所致的时滞tDec。时钟同步电路231使命令延迟线输入信号RdClk的上升沿与系统时钟信号SCLK_CMD的上升沿同步，且提供第三信号(其还可在本文中称为经时钟同步读取信号RdClk_shift)。选择器控制信号产生器电路232可将移位循环参数X(X[3:0])提供到时钟同步电路231及QED电路260。移位循环参数X表示用于吸收时滞tDec的待移位的时钟循环数目(例如，在此实施例中，最多三个时钟循环)。在一些实施例中，移位循环参数X可表示三个以上时钟循环。选择器控制信号产生器电路232从DLL控制电路280接收N值(可稍后详细地描述)以及预定CL值(其可为频率相依值)，且通过利用减法器向移位循环参数X(X[3:0])指派额外周期“CL-N”而在DLL复位序列或DLL更新序列中提供X。
延迟线240及241包含可调整延迟电路。延迟线240从DLL控制电路280接收经时钟同步读取信号RdClk-shift及分接信号(dTap[x:0])且提供第四信号(其还可在本文中称为经延迟读取信号RdDll)。DLL控制电路280进一步提供N值，所述N值表示参考时钟信号SCLK_DLL与反馈时钟信号SCLK_DLL_fb之间的时序关系，所述N值可为用以实现锁定条件的时钟循环数目，在所述锁定条件中，参考时钟信号SCLK_DLL与反馈时钟信号SCLK_DLL_fb彼此同相。在达到锁定条件之后，可将N值提供到选择器控制信号产生器电路232及QED电路260。QED电路260使来自延迟线240的经延迟读取信号RdDll与来自延迟线241的DLL时钟信号DllClk同步。QED电路260使用N值及CL值以及移位循环参数X来调整经延迟读取信号RdDll的等待时间。QED电路260提供第五信号(其还可在本文中称为读取激活信号)。
相位检测器270通过模型延迟而检测反馈时钟信号SCLK_DLL_fb与参考信号SCLK_DLL之间的相位差且将所检测相位差提供到DLL控制电路280。基于参考信号SCLK_DLL与反馈时钟信号SCLK_DLL_fb之间的相位差，DLL控制电路280可调整延迟线240及241的延迟，使得反馈时钟信号SCLK_DLL_fb的上升沿与参考时钟信号SCLK_DLL的上升沿同步。DLL控制电路280将延迟线240及241控制为具有大体上相同延迟。为在来自延迟线241的DLL时钟信号DllClk与QED电路260中的经延迟读取信号RdDll之间提供锁存裕度，将参考时钟SCLK_DLL的上升沿与经时钟同步读取信号RdClk_shift的上升沿控制为在延迟线240之前同步。通过包含时钟同步电路231，两个延迟线240及241可使用相同分接信号dTap[x:0]以具有相同延迟。因此，可通过在用于数据发射的命令路径上添加时钟同步电路231而使参考时钟信号SCLK_DLL的上升沿时序与经时钟同步读取信号RdClk_shift的上升沿同步。
图3是根据本发明的实施例的时钟同步电路的框图。举例来说，时钟同步电路30可为图2中的命令路径上的时钟同步电路231。时钟同步电路30为接收命令延迟线输入信号RdClk、系统时钟信号SCLK_CMD及移位循环参数X(X[3:0])的先进先出(FIFO)电路。时钟同步电路30包含计数器电路310、多个解码器电路320及321、包含多个单元的输入指针寄存器330以及包含多个单元的输出指针寄存器331。多个解码器320及321可为四位解码器。可通过使用计数器电路310而产生FIFO时钟信号。在一些实施例中，计数器电路310可为格雷(Gray)码计数器，然而在其它实施例中，可使用其它类型的计数器作为计数器电路310。在此实施例中，计数器电路310可为两位计数器电路且在输入指针寄存器330与输出指针寄存器331之间被共享。时钟同步电路30还可包含位于计数器电路310的输出节点处的延迟电路340，所述延迟电路响应于计数器电路310的输出信号而将经延迟计数器信号提供到解码器电路320。延迟电路340可补偿系统时钟信号SCLK_CMD与命令延迟线输入信号RdClk之间的等待时间，所述等待时间等效于“tDec+tSU”的总和，其中tSU为命令延迟线输入信号RdClk的设置时间且tDec为由命令解码器电路220中的命令解码及锁存所致的时间延迟。延迟电路340位于命令路径上，而非位于DLL时钟路径上，因此延迟电路340并不增加参考时钟信号SCLK_DLL中的抖动，此可改进RMT的裕度。
输入指针寄存器330的每一单元可包含两个锁存器以实现较低电力消耗，如稍后将更详细地描述。在其它实施例中，输入指针寄存器330单元的可为触发器。举例来说，输入指针寄存器330的单元[0]到[3]中的每一者接收来自解码器电路320的对应指针输入信号PI<0>到<3>，以及命令延迟线输入信号RdClk。举例来说，输入指针寄存器330的单元[0]到[3]中的每一者可响应于对应指针输入信号PI<0>到<3>的激活而接收命令延迟线输入信号RdClk。输入指针寄存器330的单元[0]到[3]将输出信号(例如指针信号RdClk_Out<0>到<3>)提供到选择器350。选择器350接收移位循环参数X(X[3:0])作为选择器控制信号且响应于移位循环参数X(X[3:0])而选择路径。输出指针寄存器331的单元可为触发器。解码器电路321从计数器电路310接收系统时钟信号SCLK_CMD及输出信号，且将多个对应指针输出信号PO<0>到<3>提供到输出指针寄存器331的单元[0]到[3]。输出指针寄存器331的单元[0]到[3]响应于移位循环参数X及指针输出信号PO<0>到<3>通过将输入指针寄存器330的一个单元选择性地耦合到输出指针寄存器331的对应单元而从选择器350接收信号。输出指针寄存器331响应于来自选择器350的信号及指针输出信号PO<0>到<3>而通过OR电路360提供经时钟同步读取信号RdClk_shift。举例来说，输出指针寄存器331的单元[0]到[3]中的每一者可响应于对应指针输出信号PO<0>到<3>的激活而提供经时钟同步读取信号RdClk_shift。可将经时钟同步读取信号RdClk_shift提供到延迟线，举例来说，提供到图2的延迟线240。经时钟同步读取信号RdClk_shift可与SCLK_CMD信号同步。
图4A是根据本发明的实施例的时钟同步电路中的输入指针寄存器的单元的图式。单元[0]530a、单元[1]530b、单元[2]530c及单元[3]530d可以是图3的时钟同步电路30中的输入指针寄存器330的单元[0]到[3]。单元530a、530b、530c及530d可接收命令延迟线输入信号RdClk，且可分别响应于指针输入信号PI<0>到PI<3>而进一步提供指针信号RdClk_Out<0>到<3>。单元530a、530b、530c及530d中的每一者包含两个锁存器。举例来说，单元[0]530a包含AND门51a以及锁存器52a及52b。锁存器52a可包含两个NAND门521及522且锁存器52b可包含两个NAND门523及524。类似地，单元[1]530b包含AND门51b以及锁存器52c及52d。锁存器52c可包含两个NAND门525及526，且锁存器52d可包含两个NAND门527及528。
图4B是根据本发明的实施例的图4A的输入指针寄存器的单元中的信号的时序图。指针输入信号PI<0>到PI<3>为具有命令延迟线输入信号RdClk的脉冲宽度1T的脉冲信号，其中T为一个时钟循环。指针输入信号PI<0>到PI<3>按PI<0>、PI<1>、PI<2>、PI<3>的次序被交替地激活，且由解码器电路(例如图3中的解码器电路320)提供。
举例来说，单元[0]530a接收指针输入信号PI<0>。锁存器52a中的NAND门522提供信号En1<0>，所述信号En1<0>分别在时间T1及时间T3处响应于指针输入信号PI<0>的上升沿及下降沿而具有下降沿及上升沿，同时NAND门521的输出信号-信号EnF1<0>为无效的(例如，处于逻辑低电平)。NAND门521提供信号EnF1<0>，所述信号EnF1<0>在时间T3处响应于信号En1<0>的上升沿而具有下降沿且在时间T4处响应于命令延迟线输入信号RdClk的下降沿而具有上升沿。
将信号En2<0>及指针输入信号PI<0>提供到锁存器52b中的NAND门524。锁存器52b中的NAND门524提供信号EnF2<0>，所述信号EnF2<0>在时间T3之前响应于NAND门523的输出信号-信号En2<0>的逻辑低电平且从时间T3起进一步响应于指针输入信号PI<0>的逻辑低电平而为有效的(例如，处于逻辑高电平)。锁存器52b中的NAND门523提供信号En2<0>，所述信号En2<0>分别在时间T3及时间T4处响应于信号EnF1<0>的下降沿及上升沿而具有上升沿及下降沿，同时信号EnF2<0>为有效的(例如，处于逻辑高电平“高”)。AND门51a接收指针输入信号PI<0>及信号En2<0>且提供为无效(例如，处于逻辑低电平“低”)的指针信号RdClk_Out<0>。
同时，单元[1]530b接收指针输入信号PI<1>。锁存器52c中的NAND门526提供信号En1<1>，所述信号En1<1>在时间T4处响应于命令延迟线输入信号RdClk的下降沿而具有下降沿且在时间T5处响应于指针输入信号PI<1>的下降沿而具有上升沿。NAND门525提供信号EnF1<1>，所述信号EnF1<1>分别在时间T2及时间T4处响应于命令延迟线输入信号RdClk的上升沿及下降沿而具有下降沿及上升沿，同时信号En1<1>在时间T4之前为有效的(例如，处于逻辑高电平)。将信号En2<1>及指针输入信号PI<1>提供到锁存器52d中的NAND门528。锁存器52d中的NAND门528提供信号EnF2<1>，所述信号EnF2<1>分别在时间T3及时间T5处响应于指针输入信号PI<1>的上升沿及下降沿而具有下降沿及上升沿。锁存器52d中的NAND门527提供信号En2<1>，所述信号En2<1>响应于信号EnF1<1>的下降沿而具有上升沿且响应于信号EnF2<1>的上升沿而具有下降沿。AND门51b接收指针输入信号PI<1>及信号En2<1>且提供指针信号RdClk_Out<1>，所述指针信号RdClk_Out<1>在时间T3处具有上升沿且在时间T5处具有下降沿。
因此，在图4B的实例中，命令延迟线输入信号RdClk可由指针输入信号PI<1>捕获。如上文所描述，锁存器52a及锁存器52c通过指针输入信号PI<0>及<1>的上升沿而捕获命令延迟线输入信号RdClk，且锁存器52b及锁存器52d提供脉冲宽度1T。
图5是根据本发明的实施例的包含命令延迟调整电路的设备中的命令解码器电路的电路图。命令解码器电路70可在命令解码之前及之后基于系统时钟信号SCLK_CMD而利用时钟信号GCLK锁存命令信号CMD上的命令。在命令解码器电路70中，将命令信号CMD提供到具有延迟d1的缓冲器门73。将系统时钟信号SCLK_CMD提供到延迟器71以提供延迟d2，延迟d2大约等于缓冲器门73的延迟d1，且延迟器71提供时钟信号GCLK。触发器74利用时钟信号GCLK锁存来自缓冲器门73的经延迟命令信号。将来自触发器74的输出信号提供到解码器电路75。解码器电路75可基于来自触发器74的输出信号而将命令解码且响应于输出信号而提供信号(举例来说，读取信号)。触发器76利用时钟信号GCLK’锁存来自解码器电路75的信号且提供内部读取信号Rd。具有延迟d3的延迟器72接收时钟信号GCLK且提供时钟信号GCLK’。延迟器72的延迟d3可等效于通过触发器74、解码器电路75及触发器76而导致的延迟。触发器77利用时钟信号GCLK’锁存内部读取信号Rd且将启用信号Rdi提供到时钟输入缓冲器210。具有延迟d4的缓冲器门78接收内部读取信号Rd且将命令延迟线输入信号RdClk提供到图2中的命令延迟调整电路230的时钟同步电路231。因此，将约为延迟d1、d3及d4的总和的时滞tDec提供到命令延迟线输入信号RdClk。时钟同步电路231经配置以吸收被提供到命令延迟线输入信号RdClk的时滞。
图6是根据本发明的实施例的包含命令延迟调整电路的设备中的信号的时序图。在将DLL复位或更新之后，将时钟信号CK提供到图2中的设备200的时钟输入缓冲器210。时钟信号CK为在T0、T1、T2、T3、T4、T5、T6、T7、T8、T9、…T16、T17等处包含上升沿的时钟脉冲信号。时钟输入缓冲器210响应于时钟信号CK而在时钟输入缓冲器210处提供具有延迟tIB的系统时钟信号SCLK_CMD。当在T0处发布READ命令时，命令输入缓冲器211在命令信号CMD上接收READ命令且将命令信号CMD提供到命令解码器电路220。系统时钟信号SCLK_CMD响应于时钟信号CK在T0处的上升沿而具有具延迟tIB的上升沿。时钟信号GCLK的上升沿由于延迟器71而具有相对于系统时钟信号SCLK_CMD的上升沿的延迟d2，所述延迟等效于图5中的缓冲器门73处的延迟d1。启用信号Rdi具有上升沿，所述上升沿具有相对于时钟信号GCLK的上升沿的延迟d3。命令延迟线输入信号RdClk具有由缓冲器门78导致的相对于启用信号Rdi的延迟d4。因此，命令延迟线输入信号RdClk具有延迟“tDec(＝d2+d3+d4)”。在读取操作之后，启用信号Rdi可由突发结束信号(未图解说明)复位。在时钟同步电路30中，延迟电路340将延迟“tDec+tSU”从系统时钟信号SCLK_CMD提供到指针输入信号PI<3:0>。在图6的时序图中，指针输入信号PI<0>在T0处具有相对于系统时钟信号SCLK_CMD的上升沿的延迟“tDec+tSU”。因此，指针输入信号PI<0>具有相对于命令延迟线输入信号RdClk的延迟tSU，所述延迟为命令延迟线输入信号RdClk的设置时间。
举例来说，在图6的时序图中，此实例中的移位循环参数X为三，此意味着RdClk_shift信号具有相对于系统时钟信号SCLK_CMD的对应脉冲的三循环延迟。仅在激活指针输入信号PI<0>之后激活指针输出信号PO<3>。指针输出信号PO<2>到PO<0>可维持无效状态(例如，处于逻辑低电平)。因此，响应于指针输出信号PO<3>而激活RdClk_shift信号。反馈时钟信号SCLK_DLL_fb具有相对于DllClk的延迟，所述延迟为以下延迟的总和：时钟输入缓冲器210处的延迟tIB、树290处的延迟tTREE及输出缓冲器295处的延迟tOB。此实例中的N值为五，此意味着反馈时钟信号SCLK_DLL_fb信号具有相对于系统时钟信号SCLK_CMD的对应脉冲的五循环延迟。举例来说，在具有延迟tDL的延迟线240之后，利用QED电路260中的DLL时钟信号DllClk的下降沿来锁存经延迟读取信号RdDll。为确保QED电路260中的DLL时钟信号DllClk与经延迟读取信号RdDll之间的锁存裕度“tlat”，可通过时钟同步电路231而使参考时钟信号SCLK_DLL的上升沿与经时钟同步读取信号RdClk_shift的上升沿同步，如较早所描述。QED电路260通过将经延迟读取信号RdDll移位达总共(CL-N-X)个循环而使经延迟读取信号RdDll与DLL时钟信号DllClk同步。因此，DQ信号上的输出数据具有相对于DLL时钟信号DllClk的总共为“tTree+tOB+(CL-N-X)*T”的延迟。
所属领域的技术人员将进一步了解，结合本文中所揭示的实施例所描述的各种说明性逻辑块、配置、模块、电路及算法步骤可实施为电子硬件、由处理器执行的计算机软件或两者的组合。各种说明性组件、块、配置、模块、电路及步骤已大体按照其功能性在上文进行描述。虽然所属领域的技术人员可针对每一特定应用以变化的方式实施所描述功能性，但不应将此类实施方案决策解释为导致背离本发明的范围。
提供所揭示实施例的前述说明以使所属领域的技术人员能够制作或使用所揭示的实施例。所属领域的技术人员将易于明了对这些实施例的各种修改，且本文中所定义的原理可在不背离本发明的范围的情况下应用于其它实施例。因此，本发明并不打算限于本文中所展示的实施例，而是将被赋予与如由所附权利要求书所界定的原理及新颖特征相一致的可能的最宽广范围。

Claims (20)

1.一种设备，其包括：
第一电路，其经配置以对第一时钟信号做出响应以锁存第一信号，所述第一电路经配置以提供第二信号；及
第二电路，其耦合到所述第一电路以锁存所述第二信号，所述第二电路经配置以响应于与所述第一时钟信号大体上同相的第一输出时序信号基于所述第二信号而提供第三信号。
2.根据权利要求1所述的设备，其中所述第一电路经配置以将所述第一信号解码以提供所述第二信号。
3.根据权利要求2所述的设备，其中所述第一电路为命令解码器电路且所述第一信号包含命令信号。
4.根据权利要求1所述的设备，其进一步包括：
第一延迟电路，其经配置以接收与所述第一时钟信号大体上同相的第二时钟信号，且通过使所述第二时钟信号延迟达可调整的第一延迟而提供第三时钟信号；
第二延迟电路，其耦合到所述第二电路且经配置以使所述第三信号延迟达可调整的第二延迟以提供第四信号；及
延迟控制电路，其经配置以将所述第一电路的所述第一延迟及所述第二延迟电路的所述第二延迟调整为彼此大体上相等。
5.根据权利要求4所述的设备，其进一步包括时钟输入缓冲器电路，所述时钟输入缓冲器电路经配置以响应于启用信号而产生所述第二时钟信号，且其中所述第一电路耦合到所述时钟输入缓冲器电路并进一步经配置以将所述启用信号提供到所述时钟输入缓冲器。
6.根据权利要求4所述的设备，其进一步包括：
第三电路，其耦合到所述第二延迟电路且经配置以响应于所述第三时钟信号及等待时间信息而使所述第四信号延迟以提供第五信号；及
输出缓冲器，其耦合到所述第三电路且经配置以响应于所述第五信号而被激活并响应于所述第三时钟信号而进行操作。
7.根据权利要求1所述的设备，其中所述第二电路进一步经配置以响应于相对于所述第一时钟信号在相位上延迟的第一输入信号而锁存所述第二信号。
8.根据权利要求7所述的设备，其中所述第二电路进一步包括：
计数器电路，其经配置以接收所述第一时钟信号且进一步经配置以响应于所述第一时钟信号而提供多个时序控制信号；
第三延迟电路，其耦合到所述计数器电路且经配置以通过使所述时序控制信号延迟而提供多个第二输入时序信号；
第一解码器，其耦合到所述第三延迟电路且经配置以通过将所述第二输入时序信号解码而提供第一输入时序信号；及
第二解码器，其耦合到所述计数器电路且经配置以通过将所述时序控制信号解码而提供所述第一输出时序信号。
9.根据权利要求8所述的设备，其中所述第三延迟电路经配置以表示大体上恒定的第一延迟。
10.根据权利要求8所述的设备，其中
所述第一解码器进一步经配置以通过将所述第二输入时序信号解码而提供第三输入时序信号，
其中所述第二解码器进一步经配置以通过将所述时序控制信号解码而提供第二输出时序信号，且
其中所述第二电路进一步包括：
第一输入锁存电路及第二输入锁存电路，其共同地耦合到所述第一电路且经配置以分别响应于所述第一输入时序信号及所述第二输入时序信号而锁存所述第二信号；
第一输出锁存电路及第二输出锁存电路，其分别耦合到所述第一输入锁存电路及所述第二输入锁存电路且经配置以分别响应于所述第一输出时序信号及所述第二输出时序信号而输出所述第三信号；及
选择器电路，其包含分别耦合到所述第一输入锁存电路及所述第二输入锁存电路的第一输入节点及第二输入节点，以及分别耦合到所述第一输出锁存电路及所述第二输出锁存电路的第一输出节点及第二输出节点，所述选择器电路经配置以响应于选择器控制信号而将所述第一输入锁存电路及所述第二输入锁存电路连接到所述第一输出锁存电路及所述第二输出锁存电路。
11.根据权利要求10所述的设备，其进一步包括：
第三电路，其耦合到所述第二电路且经配置以响应于等待时间信息而提供所述选择器控制信号。
12.一种设备，其包括：
时钟输入缓冲器，其经配置以基于外部时钟信号而提供参考时钟信号及系统时钟信号；
命令解码器，其经配置以响应于所述系统时钟信号而锁存命令信号且进一步经配置以基于所述命令信号而提供信号；及
命令延迟调整电路，其包括：
时钟同步电路，其经配置以从所述命令解码器接收所述信号，所述时钟同步电路经配置以响应于所述系统时钟信号而锁存所述信号且进一步经配置以响应于移位循环参数而提供经时钟同步读取信号。
13.根据权利要求12所述的设备，其中所述命令解码器进一步包括：
第一触发器，其经配置以响应于第一时钟信号、响应于所述系统时钟信号而锁存所述命令信号且进一步经配置以提供输出信号；
解码器，其耦合到所述第一触发器且经配置以响应于所述输出信号而提供读取信号及写入信号中的一者；
第二触发器，其经配置以响应于第二时钟信号、响应于所述第一时钟信号而锁存读取信号及所述写入信号中的所述一者且进一步经配置以提供内部信号；及
第三触发器，其经配置以响应于所述第二时钟信号而锁存所述内部信号且进一步经配置以提供启用信号。
14.根据权利要求13所述的设备，其中
所述命令解码器进一步经配置以将所述启用信号提供到所述时钟输入缓冲器，所述启用信号具有上升沿，所述上升沿具有相对于所述命令信号的延迟，所述延迟等效于所述输出信号相对于所述命令信号的延迟，且
其中所述时钟输入缓冲器经配置以至少部分地响应于所述启用信号而提供所述参考时钟信号。
15.根据权利要求12所述的设备，其中所述时钟同步电路进一步经配置以响应于具有相对于所述系统时钟信号的延迟的指针输入信号中的一者而锁存来自所述命令解码器的所述信号。
16.根据权利要求15所述的设备，其中所述时钟同步电路进一步包括：
计数器电路，其经配置以接收所述系统时钟信号且进一步经配置以响应于所述系统时钟信号而提供多个第一时序控制信号；
延迟电路，其耦合到所述计数器电路且经配置以提供多个第二时序控制信号，所述多个第二时序控制信号具有相对于所述系统时钟信号的预定延迟；
第一解码器电路，其耦合到所述延迟电路且经配置以通过将所述多个第二时序控制信号解码而提供指针输入信号；及
第二解码器电路，其耦合到所述计数器电路且经配置以接收所述系统时钟信号及所述多个第一时序控制信号，并且进一步经配置以响应于所述系统时钟信号通过将所述多个第一时序控制信号解码而提供指针输出信号。
17.根据权利要求16所述的设备，其中所述时钟同步电路进一步包括：
输入指针寄存器，其包括多个单元，每一单元包括：
第一锁存器，其经配置以接收来自所述命令解码器的所述信号以及所述指针输入信号中的对应一者；及
第二锁存器，其经配置以接收所述指针输入信号中的所述对应一者及来自所述
第一锁存器的输出信号；以及
输出指针寄存器，其包括多个单元，每一单元包括：
第三锁存器，其经配置以响应于所述指针输出信号中的对应一者而提供输出信号；及
第四锁存器，其经配置以接收所述指针输出信号中的对应一者及来自所述第三锁存器的所述输出信号；以及
选择器电路，其包括耦合到所述输入指针寄存器的所述对应多个单元的多个输入节点，及耦合到所述输出指针寄存器的所述对应多个单元的多个输出节点，
其中所述选择器电路经配置以响应于选择器控制信号而将所述输入指针寄存器的所述多个单元中的一个单元选择性地耦合到所述输出指针寄存器的所述多个单元中的一个对应单元。
18.一种方法，其包括：
在时钟输入缓冲器中基于外部时钟信号而提供参考时钟信号及系统时钟信号；
响应于所述系统时钟信号而锁存命令信号；
基于所述命令信号而提供信号；
响应于所述系统时钟信号而锁存所述信号；及
响应于移位循环参数、响应于等待时间信息而提供经时钟同步读取信号。
19.根据权利要求18所述的方法，其中响应于所述系统时钟信号而锁存命令信号包括：
响应于第一时钟信号、响应于所述系统时钟信号而锁存所述命令信号；
响应于所述命令信号上的读取命令或写入命令而提供读取信号或写入信号作为输出信号；
响应于第二时钟信号、响应于所述第一时钟信号而锁存所述读取信号或所述写入信号；
提供所述经锁存读取信号或所述经锁存写入信号作为内部信号；
响应于所述第二时钟信号而锁存所述内部信号；及
响应于所述经锁存内部信号而提供启用信号。
20.根据权利要求19所述的方法，其中响应于所述系统时钟信号而锁存所述信号包括：
接收所述系统时钟信号；
响应于所述系统时钟信号而提供多个第一时序控制信号；
提供多个第二时序控制信号，所述多个第二时序控制信号具有相对于所述系统时钟信号的预定延迟；及
通过将所述多个第二时序控制信号解码而提供指针输入信号；且
其中响应于所述移位循环参数、响应于等待时间信息而提供所述经时钟同步读取信号包括：
接收所述系统时钟信号及所述多个第一时序控制信号；及
响应于所述系统时钟信号通过将所述多个第一时序控制信号解码而提供指针输出信号。
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