JP5197485B2 - Pll回路 - Google Patents
Pll回路 Download PDFInfo
- Publication number
- JP5197485B2 JP5197485B2 JP2009124160A JP2009124160A JP5197485B2 JP 5197485 B2 JP5197485 B2 JP 5197485B2 JP 2009124160 A JP2009124160 A JP 2009124160A JP 2009124160 A JP2009124160 A JP 2009124160A JP 5197485 B2 JP5197485 B2 JP 5197485B2
- Authority
- JP
- Japan
- Prior art keywords
- clock
- circuit
- output
- clocks
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 description 58
- 238000010586 diagram Methods 0.000 description 15
- 230000000630 rising effect Effects 0.000 description 12
- 238000004364 calculation method Methods 0.000 description 5
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 2
- 241000282421 Canidae Species 0.000 description 2
- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
ここで、基準信号に高精度に同期したクロック信号を生成するPLL回路の例が特許文献1に開示されている。図17に特許文献1のPLL回路1の構成を示す。図17に示すように、PLL回路1は、多相基準クロック出力回路10と、デジタルVCO(Voltage Controlled Oscillator)20と、選択回路30と、周波数制御端子40と、高精度クロック出力端子50とを有する。
110 多相基準クロック出力回路
120 デジタルVCO
130 選択回路
140 周波数制御端子
150 高精度クロック出力端子
160 多相2分周回路
170 セレクタ
FF11〜FF28 Dフリップフロップ
SEL131 セレクタ
DCELL111〜DCELL114 ディレイセル
BUF111〜BUF114 バッファ回路
FF31〜FF38 Dフリップフロップ
FF41〜FF48 Dフリップフロップ
IV161 インバータ回路
121 加算器
122 デコーダ
123 レジスタ
124 余剰演算器
125 比較器
126 遅延データ演算器
127 レジスタ
200 PLL回路
210 多相バッファ回路
C1〜C8 外部出力端子
221〜22n 分周回路
NOR221 NOR(否定論理和)回路
FF211、FF212 Dフリップフロップ
NAND211〜NAND223 NAND(否定論理積)回路
OR211 OR(論理和)回路
NOR271 NOR(否定論理和)回路
FF271、FF272 Dフリップフロップ
NAND271〜NAND273 NAND(否定論理積)回路
OR271 OR(論理和)回路
RS211 RSラッチ回路
300 光ディスク装置
310 コントローラ回路
311 ロジック回路
320 光ディスクドライブ回路
321 記録データ書き込み・読み出し回路
500 PLL回路
501 セレクタ
Claims (1)
- それぞれ位相が異なる複数の基準クロックを出力する多相基準クロック出力回路と、
前記複数の基準クロックをそれぞれ所定の値で分周した複数の分周クロックを出力する多相分周回路と、
前記複数の基準クロックのいずれか1つ、もしくは、前記複数の分周クロックのいずれか1つのうちのどちらかを選択し、その選択したクロックを選択クロックとして出力する選択スイッチ回路と、
前記選択クロックを動作クロックとし、周波数制御入力データの値に応じて周波数が変動する出力クロックと、前記出力クロックと前記周波数制御入力データの値に応じて計算される理想位相との位相差を示す遅延量データとを出力するデジタルVCOと、
前記遅延量データに応じて前記複数の分周クロックのうち1つに同期した前記出力クロックを選択して出力する選択回路と、を有する
PLL回路。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009124160A JP5197485B2 (ja) | 2009-05-22 | 2009-05-22 | Pll回路 |
US12/773,971 US8258841B2 (en) | 2009-05-22 | 2010-05-05 | PLL circuit and optical disc apparatus |
US13/474,182 US20120229179A1 (en) | 2009-05-22 | 2012-05-17 | Pll circuit and optical disc apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009124160A JP5197485B2 (ja) | 2009-05-22 | 2009-05-22 | Pll回路 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010273187A JP2010273187A (ja) | 2010-12-02 |
JP2010273187A5 JP2010273187A5 (ja) | 2012-04-05 |
JP5197485B2 true JP5197485B2 (ja) | 2013-05-15 |
Family
ID=43124182
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009124160A Expired - Fee Related JP5197485B2 (ja) | 2009-05-22 | 2009-05-22 | Pll回路 |
Country Status (2)
Country | Link |
---|---|
US (2) | US8258841B2 (ja) |
JP (1) | JP5197485B2 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7656745B2 (en) | 2007-03-15 | 2010-02-02 | Micron Technology, Inc. | Circuit, system and method for controlling read latency |
TWI378636B (en) * | 2009-02-18 | 2012-12-01 | Novatek Microelectronics Corp | Frequency dividing circuit |
IT1394705B1 (it) * | 2009-05-29 | 2012-07-13 | St Microelectronics Srl | Divisore di un segnale multifase. |
US8791729B2 (en) * | 2012-06-11 | 2014-07-29 | Cisco Technology, Inc. | Multi-phase frequency divider having one or more delay latches |
US9813067B2 (en) | 2015-06-10 | 2017-11-07 | Micron Technology, Inc. | Clock signal and supply voltage variation tracking |
US9865317B2 (en) | 2016-04-26 | 2018-01-09 | Micron Technology, Inc. | Methods and apparatuses including command delay adjustment circuit |
US9997220B2 (en) * | 2016-08-22 | 2018-06-12 | Micron Technology, Inc. | Apparatuses and methods for adjusting delay of command signal path |
US10110214B2 (en) * | 2017-01-11 | 2018-10-23 | Stmicroelectronics (Research & Development) Limited | Voltage comparator circuit including a plurality of voltage controlled delay lines |
US10224938B2 (en) | 2017-07-26 | 2019-03-05 | Micron Technology, Inc. | Apparatuses and methods for indirectly detecting phase variations |
JP2020202439A (ja) | 2019-06-06 | 2020-12-17 | ソニーセミコンダクタソリューションズ株式会社 | 位相同期回路、電子装置、および、位相同期回路の制御方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7295077B2 (en) * | 2003-05-02 | 2007-11-13 | Silicon Laboratories Inc. | Multi-frequency clock synthesizer |
JP2008205730A (ja) * | 2007-02-19 | 2008-09-04 | Nec Electronics Corp | Pll回路 |
-
2009
- 2009-05-22 JP JP2009124160A patent/JP5197485B2/ja not_active Expired - Fee Related
-
2010
- 2010-05-05 US US12/773,971 patent/US8258841B2/en not_active Expired - Fee Related
-
2012
- 2012-05-17 US US13/474,182 patent/US20120229179A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2010273187A (ja) | 2010-12-02 |
US20100295584A1 (en) | 2010-11-25 |
US20120229179A1 (en) | 2012-09-13 |
US8258841B2 (en) | 2012-09-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5197485B2 (ja) | Pll回路 | |
JP4435723B2 (ja) | 位相同期回路およびそれを用いた半導体集積回路装置 | |
US7605661B2 (en) | Phase locked loop circuit including digital voltage-controlled oscillator, ring oscillator and selector | |
JP3564855B2 (ja) | リングオシレータ及びpll回路 | |
US7554373B2 (en) | Pulse width modulation circuit with multiphase clock | |
JP2012205046A (ja) | 半導体集積回路およびその動作方法 | |
JP2013102372A (ja) | クロックデータリカバリ回路およびそれを内蔵する送受信半導体集積回路 | |
US20050001665A1 (en) | Method for multiple-phase splitting by phase interpolation and circuit the same | |
US6493305B1 (en) | Pulse width control circuit | |
JP2008172512A (ja) | 周波数シンセサイザ及びフェーズロックループ、並びにクロック生成方法 | |
JP3921321B2 (ja) | 記録メディア読み出しシステム | |
EP1693966A1 (en) | Digital phase locked loop apparatus | |
US7424087B2 (en) | Clock divider | |
JP3547984B2 (ja) | パルス幅制御回路及びディスク記録制御回路 | |
US20070086555A1 (en) | DLL circuit having two input standard clocks, clock signal generation circuit having the DLL circuit and clock signal generation method | |
WO2020246092A1 (ja) | 位相同期回路、電子装置、および、位相同期回路の制御方法 | |
JP3547983B2 (ja) | パルス幅制御回路及びディスク記録制御回路 | |
JP4555379B2 (ja) | 位相同期回路およびそれを用いた半導体集積回路装置 | |
CN100449631C (zh) | 包括生成更高定时分辩率的定时信号的装置的光记录载体记录设备和方法 | |
JP3843104B2 (ja) | パルス幅制御回路 | |
JP3568815B2 (ja) | フレーム位相同期回路 | |
JP3506732B2 (ja) | タイミング再生回路 | |
JP3506729B2 (ja) | タイミング再生回路 | |
CN114301450A (zh) | 可配置门控单元、可配置跟踪保持电路及相位内插分频器 | |
JP2000357950A (ja) | 自己校正型可変遅延回路方式および装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120220 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120220 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130129 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130205 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160215 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5197485 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |