CN106415824A - 叠层封装微电子组件的分批工艺制造 - Google Patents

叠层封装微电子组件的分批工艺制造 Download PDF

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Publication number
CN106415824A
CN106415824A CN201580020842.6A CN201580020842A CN106415824A CN 106415824 A CN106415824 A CN 106415824A CN 201580020842 A CN201580020842 A CN 201580020842A CN 106415824 A CN106415824 A CN 106415824A
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China
Prior art keywords
support component
terminal
micromodule
piece
layer
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CN201580020842.6A
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English (en)
Inventor
B·哈巴
I·莫哈梅德
王亮
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Vertical Circuits Inc
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Vertical Circuits Inc
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Publication of CN106415824A publication Critical patent/CN106415824A/zh
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Abstract

本发明涉及叠层封装微电子组件的分批工艺制造，公开了一种微电子组件，所述微电子组件可通过如下方式制备：通过导电块来接合第一子组件和第二子组件，以连接每个子组件的支撑元件上的导电元件。感光材料的图案化层可覆盖在所述支撑元件之一的表面上并且具有开口，所述开口的截面尺寸保持恒定，或随着从该支撑元件的所述表面的高度而单调递增，其中所述块延伸穿过所述开口并且具有由所述开口限定的尺寸。可通过使囊封剂流入所述接合的第一子组件和第二子组件之间的空间中而形成囊封层。

Description

叠层封装微电子组件的分批工艺制造
技术领域
本发明涉及微电子元件的封装，尤其涉及半导体芯片的封装。
背景技术
微电子元件通常包括半导体材料诸如硅或砷化镓的薄板，该薄板通常被称为裸片或半导体芯片。半导体芯片通常作为单独的预封装的单元提供。在一些单元设计中，将半导体芯片安装到衬底或芯片载体上，该衬底或芯片载体继而安装到电路面板诸如印刷电路板上。
有源电路被制作在半导体芯片的第一面(例如正面)中。为了便于电连接至有源电路，芯片在相同的面上设有接合垫。接合垫通常设置成规则的阵列，其或者围绕裸片的边缘设置，或者对于许多存储器装置而言设置在裸片的中心。接合垫通常由大约0.5微米(μm)厚的导电金属诸如铜或铝制成。接合垫可包括单层或多层金属。接合垫的尺寸将随器件类型而有所不同，但其侧边通常测得为数十至数百微米。
微电子元件(诸如半导体芯片)通常要求到其他电子部件的许多输入和输出连接。半导体芯片或其他相当的器件的输入和输出触点通常设置成基本上覆盖芯片表面的栅格状图案(俗称为“面积阵列”)，或设置成可平行于且相邻于芯片的前表面的每个边缘延伸的或在前表面的中心中延伸的细长行。半导体芯片通常在封装中提供，所述封装促进在制造期间和在将芯片安装在外部衬底(诸如电路板或其他电路面板)上期间处置芯片。例如，将诸多半导体芯片在适于进行表面安装的封装中提供。已提议这种一般类型的众多封装来用于各种应用。最常见的是，这些封装包括在电介质上具有形成为电镀或蚀刻的金属结构的端子的介电元件，俗称为“芯片载体”。这些端子通常通过以下项连接到芯片自身的触点：诸如沿芯片载体自身延伸的薄迹线的特征结构，和在芯片触点与端子或迹线之间延伸的细引线或导线。在表面安装操作中，将封装放置到电路板上，使得封装上的每个端子与电路板上的对应接触垫对准。在端子与接触垫之间提供焊料或其他粘结材料。可通过对组件加热以便使焊料熔化或“回流”或以其他方式使粘结材料活化，来将封装永久性粘结在适当位置。
诸多封装包括呈焊料球形式的、通常直径为约0.1mm和约0.8mm(5密耳和30密耳)、附接到封装端子的焊料块。具有从其底部表面凸出的焊料球阵列的封装俗称为球栅阵列或“BGA”封装。其他封装(称为接点栅格阵列或“LGA”封装)通过由焊料形成的薄层或接点固定到衬底。这种类型的封装可以相当紧凑。某些封装(俗称为“芯片级封装”)占据电路板的面积等于或略大于整合在封装中的器件的面积。此有利之处在于其减小组件的整体大小且允许在衬底上的各种器件之间使用短互连，这继而限制器件之间的信号传播时间且因此促进以高速度操作组件。
封装式半导体芯片通常以“堆叠式”布置提供，其中例如在电路板上提供一个封装，且在第一封装的顶部上安装另一封装。这些布置可允许多个不同芯片安装在电路板上的单个覆盖面积内，且可通过在封装之间提供短互连来进一步促进高速度操作。通常，这个互连距离仅略大于芯片自身的厚度。为了在芯片封装的堆叠内实现互连，必须在每个封装(最顶部封装除外)的两侧上提供用于机械连接和电连接的结构。例如，这已通过在安装有芯片的衬底的两侧上提供接触垫或接点完成，所述垫通过导电通孔等连接到衬底。堆叠式芯片布置和互连结构的实例提供在美国专利申请公布No.2010/0232129中，该专利的公开内容以引用的方式并入本文。
在芯片的任何物理布置方式中，尺寸是重要的考虑因素。随着便携式电子装置的迅速发展，使芯片的物理布置方式更为紧凑这一需要变得越来越强烈。仅以举例的方式，通常称为“智能手机”和平板电脑的便携式装置将移动电话的功能与强大的数据处理器、存储器和辅助装置例如，全球定位系统接收器、电子相机、局域网络连接、以及高分辨率显示器和相关的图像处理芯片集成在一起。此类装置可以提供诸如全互联网连接、包括全分辨率视频在内的娱乐、导航、电子银行服务以及甚至更多的功能，所有这些功能全部存在于一台袖珍型装置中。复杂的便携式装置需要将很多芯片组装进小的空间中。此外，一些芯片具有多个通常被称为“I/O”的输入和输出连接。这些I/O必须与其他芯片的I/O互连。所述互连应当是短的，并且应当具有低阻抗以最小化信号传播延迟。形成所述互连的元件不应显著增大组件的尺寸。类似的需求在例如数据服务器(诸如在互联网搜索引擎中使用的那些)的其他应用中出现。例如，在复杂的芯片之间提供多个短的低阻抗互连的结构可以增大搜索引擎的带宽并降低其电力消耗。
尽管已取得进展，仍可作出进一步改进以增强具有堆叠端子的微电子封装结构及用于制备此类封装的工艺。
发明内容
根据本发明的一个方面，提供了一种微电子组件，其可包括第一支撑元件和第二支撑元件，每个支撑元件具有第一表面，该第一表面面向组件的向外方向，并且每个支撑元件具有第二表面，该第二表面面向组件的向内方向、朝向第一支撑元件和第二支撑元件中的另一者的第二表面。微电子组件可具有以下各项中的至少一者：第一支撑元件的第一表面处的第一端子、或第二支撑元件的第一表面处的第二端子。导电第一元件可设置在第一支撑元件的第二表面处。感光材料的图案化层可覆盖在第一支撑元件的第二表面上，并且具有与第一元件对齐的开口。在一个实例中，每个开口可具有截面尺寸，该截面尺寸保持恒定或随着从第一支撑元件的第二表面的高度而增加。粘结材料的导电块可穿过图案化层的对应开口而与第一元件电耦接并凸出在第一元件上方。每个块可具有截面尺寸，该截面尺寸由块从中凸出的对应开口的截面尺寸限定。微电子元件可安装到第一支撑元件或第二支撑元件之一的第二表面。导电第二元件可设置在第二支撑元件的第二表面处，并可与块电耦接，且可通过块而与第一元件电耦接。囊封层可覆盖在第二支撑元件的第二表面、图案化层的表面上，并且可接触至少一些块，其中所述块延伸穿过囊封层的至少一部分。在具体实例中，所述块可具有球状部分，其中所述块延伸穿过囊封层的所述至少一部分。
根据本发明的一个方面的堆叠式多芯片微电子组件可包括微电子组件和覆盖在第一支撑元件的第一表面上的微电子封装，其中所述微电子封装具有与微电子组件的第一端子连接的端子。
根据本发明的具体方面的堆叠式多芯片微电子组件可包括微电子组件，并且具有第二端子而不具有第一端子。第二端子可通过其间的块而与第一元件电耦接。
根据本发明的一个方面的制造微电子组件的方法可包括将第一子组件和第二子组件接合而形成组件。所述组件可包括第一支撑元件和第二支撑元件，所述第一支撑元件具有面向第一方向的、面朝外的第一表面，而所述第二支撑元件具有面向与第一方向相反的第二方向的、面朝外的第一表面。第一支撑元件在其面朝内的第二表面处可具有导电第一元件，而第二支撑元件在其面朝内的第二表面处可具有导电第二元件，并且可安装至少一个微电子元件，使之覆盖在第一支撑元件和第二支撑元件之一的第二表面上。所述组件还可包括覆盖在第一支撑元件或第二支撑元件之一的第二表面上的感光材料的图案化层，所述图案化层具有开口，其截面尺寸保持恒定或随着从图案化层位于其上的支撑元件的表面的高度而增加。所述组件还可包括粘结材料的块，其从第一元件延伸穿过开口并与第二元件电耦接，所述块具有由开口的截面尺寸限定的截面尺寸。
在形成所述组件之后，囊封剂可流入第一子组件和第二子组件之间的空间中，从而形成与块的至少部分的表面接触的囊封层。
根据这种方法，所述组件可包括第一支撑元件的第一表面处的第一端子以及第二支撑元件的第一表面处的第二端子，所述第一端子通过第一元件、第二元件和其间的块而与第二端子电耦接。
或者，根据这种方法，所述组件可包括以下各项中的一者：第一支撑元件的第一表面处的第一端子，所述第一端子通过其间的块而与第二元件电耦接；或第二支撑元件的第一表面处的第二端子，所述第二端子通过其间的块而与第一元件电耦接。
根据一个具体方面，所述方法还可包括通过如下方式形成图案化层：沉积感光材料的第一层并沉积包括感光材料的第二层的临时层，对临时层进行光刻图案化以形成小孔，使用图案化临时层根据临时层中的小孔对第一层进行图案化以形成开口，接着用块填充开口，然后移除临时层使得块凸出到一定高度，所述高度大于第一层在图案化层位于其上的支撑元件的第二表面上方的高度。
附图说明
图1为剖视图，示出了根据本发明实施例的微电子组件。
图1A为局部片段剖视图，进一步示出了图1中所描绘的微电子组件的一个方面。
图2为剖视图，示出了与附加部件(诸如电路面板)耦接的、根据本发明实施例的微电子组件。
图3为剖视图，示出了包括多个堆叠式电耦接微电子组件(诸如图1中所示的多个微电子组件)的堆叠式多芯片组件。
图4为剖视图，示出了根据图1中所描绘的本发明实施例的变型的微电子组件。
图5至12为剖视图，示出了根据本发明实施例的微电子组件的制造中的各阶段，其中：
图6示出了图5中所描绘的阶段之后的阶段；
图7示出了图6中所描绘的阶段之后的阶段；
图8示出了图7中所描绘的阶段之后的阶段；
图9示出了图8中所描绘的阶段之后的阶段；
图10示出了图9中所描绘的阶段之后的阶段；
图11示出了图10中所描绘的阶段之后的阶段；以及
图12示出了根据图6-11中所描绘的实施例的变型的、制造微电子组件的方法中的阶段。
图13为剖视图，示出了根据图5至12中所示的方法的变型的、制造微电子组件的方法中的阶段。
图14为剖视图，示出了进一步结合到根据本发明实施例的系统中且可用于该系统中的微电子封装或组件。
具体实施方式
因此，本文的本发明实施例可提供改进的组件，其包含微电子元件且具有第一端子和第二端子，例如顶部端子和底部端子，其中电耦接顶部端子和底部端子的竖直互连件提供所需的悬空高度，同时还允许竖直互连件在与组件中的微电子元件的表面平行的横向方向上，以所需节距紧密封装。参见图1中所示的微电子组件10或微电子封装，在一个实例中，支撑元件的第二表面之间的悬空高度H在与第一支撑元件的第二表面平行的至少一个方向上大于粘结材料的块136的最小节距“a”一半。在其他实例中，悬空高度可等于或大于最小节距a，或可等于或大于最小节距a的1.5倍。
如在图1中可进一步看出，微电子封装10包括第一支撑元件102和第二支撑元件104。每个支撑元件可为例如封装衬底，诸如芯片载体或介电元件或结构，其将介电材料、半导体材料和导电材料中的两者或更多者组合在一起，所述材料上可设置导电结构，诸如端子、迹线、触点和通孔。例如，一个或两个支撑元件可为或可包括片状或板状介电元件，所述介电元件包含无机介电材料或有机介电材料中的至少一者，并且可主要包含无机材料或主要包含聚合物材料，或可为包含无机材料和聚合物材料两者的复合结构。因此，例如，非限制性地，一个或两个支撑元件可包括这样的介电元件，其包含聚合物材料，诸如聚酰亚胺、聚酰胺、环氧树脂、热塑性材料、热固性材料等等。或者，一个或两个支撑元件可包括这样的介电元件，其包含无机介电材料，诸如硅的氧化物、硅的氮化物、硅的碳化物、氧氮化硅、氧化铝，并且一个或两个支撑元件可包含半导体材料，诸如硅、锗或碳等等，或一种或多种此类无机材料的组合。在另一个实例中，一个或两个支撑元件可包括这样的介电元件，其为一种或多种聚合物材料与一种或多种无机材料(诸如上述的材料)的组合。在特定实例中，一个或两个支撑元件可具有玻璃增强环氧树脂的结构，诸如通常称为“FR-4”或“BT树脂”板结构。在另一个实例中，一个或两个支撑元件可例如基本上由聚合物材料(诸如聚酰亚胺)组成。一个或两个支撑元件可包括一层或多层顺应性材料，其在一些情况下可暴露于这种支撑元件的第一表面、第二表面、或第一表面和第二表面两者处。顺应性材料在一些情况下可包括杨氏模量通常小于2.0吉帕(“GPa”)的聚酰亚胺、聚酰胺，或在一些情况下顺应性材料可包括杨氏模量显著更低(例如远低于1.0GPa)的弹性体。
如在图1中可看出，每个支撑元件具有相对面向的第一表面和第二表面。当装配在微电子组件10或微电子封装中时，支撑元件的第一表面101、105朝外相互背离，并且第二表面103、106朝内相互面对。微电子元件120(其可为未封装或封装的半导体芯片)安装到支撑元件102、104中的一者或两者的第二表面。在具体实施例中，微电子元件可为在其表面处具有与芯片垫耦接的附加导电结构的半导体芯片。尽管未示出，在一个实施例中，第二微电子元件可安装在微电子元件120的背离支撑元件104的表面129上方的空间中。第二微电子元件可设置在表面129与第一支撑元件102的表面103之间。第二微电子元件可安装到第一支撑元件102的表面103，并且可与第一元件132电耦接。或者，第二微电子元件可与第二支撑元件104的表面106处的导电元件电耦接。第二囊封层(未示出)可设置或覆盖在一个或多个边缘表面上或第二微电子元件的表面上。
在具体实施例中，第一支撑元件102可称为“内插器”，特别是当第一支撑元件102在其第二表面103处具有导电第一元件132时，这些导电第一元件以与内插器102的第一表面处的一组第一端子141不同的图案(例如，不同的位置或不同的节距)安置。如在图1中可进一步看出，在一个实例中，第一元件132的最小节距“a”可显著小于第一端子141的最小节距“b”。第一端子141所具有的最小节距“b”可与微电子组件10的相对面向的表面105处第二端子142的最小节距“c”相同或不同。第一端子141和第二端子142具有相同节距的微电子组件10可用于例如较高级组件，该较高级组件包括多个堆叠且电耦接的微电子组件10，如在图3中可看出。
如本公开中结合部件(例如，内插器、微电子元件、电路面板、衬底等)所使用，当陈述导电元件“处于”部件的表面时，表示如果所述部件没有与任何其他元件装配在一起，则所述导电元件可以与某个理论点接触，该理论点在垂直于部件表面的方向上从部件的外部朝部件表面移动。因此，处于衬底的表面处的端子或其他导电元件可从该表面凸出；可与该表面齐平；或可相对于该表面以衬底中的孔或凹陷形式凹进。在一个实例中，该部件的“表面”可为介电结构的表面；然而，在具体实施例中，该表面可为其他材料(诸如金属或其他导电材料或半导体材料)的表面。
在图1中，与第一支撑元件的第一表面101平行的方向在本文中被称为第一横向方向178和第二横向方向179或者“水平”或“侧向”方向，而垂直于第一表面的方向180在本文中被称为向上或向下方向，且在本文中还被称为“竖直”方向。在本文中提到的方向处于所提及结构的参照系中。因此，这些方向可以在垂直或重力参照系中以任意取向设置。在陈述一个特征设置在“一个表面上方”比另一个特征更大的高度处时，是指在相同的正交方向上一个特征与表面的距离大于另一个特征与表面的距离。相反，在陈述一个特征设置在“一个表面上方”比另一个特征更小的高度处时，是指在相同的正交方向上一个特征与表面的距离小于另一个特征与表面的距离。
参见图1，在一个实例中，微电子元件120的“前”触点承载面可朝下面向第二支撑元件104的第二表面106，并且微电子元件正面处的多个触点124可面向第二支撑元件的表面106处的对应触点并与所述对应触点电耦接，诸如在2013年7月15日提交的、共同拥有的美国申请13/942,568(下文称“'568申请”)的图1A中可看出，该申请的公开内容以引用的方式并入本文。在具体实例中，如例如在2012年4月4日提交的、共同拥有的美国申请13/439,299(下文称“'299申请”，该申请的公开内容以引用的方式并入本文)中可看出，触点可以面积阵列形式分布在微电子元件的正面的至少一部分中，该面积阵列具有两行或更多行触点且具有两列或更多列触点。底充胶可安置在微电子元件的正面与第二支撑元件的第二表面106之间，所述底充胶围绕各个连接，并且在一些情况下可机械地加固这些连接。微电子元件120的触点124可与第二支撑元件的第一表面105处的导电第二端子142电耦接。在此类实例中，触点124可通过倒装芯片连接，即通过粘结金属(例如锡、铟、焊料或低共熔材料)或嵌入聚合物材料中的金属颗粒的导电基体材料，而与面向触点124的第二表面106处的对应触点电耦接。
或者，作为倒装芯片连接的替代，向下取向的正面上的触点(未示出)可布置在一行或多行触点和/或一列或多列触点内的位置处，这些位置与在支撑元件104的第一表面105和第二表面106之间延伸的小孔或“粘结窗”(未示出)对齐。在这种情况下，微电子元件的触点124可通过接合到触点的引线而与第二端子142耦接，诸如在例如2011年11月29日提交的美国申请13/306,068的图1A-1C、5B-5C和9A-15中的任何一者或多者中可看出，该申请的公开内容以引用的方式并入本文。在具体实例中，引线可为导线引线(未示出)，例如焊线，其延伸穿过小孔并接合到触点及第一表面105处的对应触点(未示出)。在另一个实例中，所述引线可为这样的引线，每个引线包括作为迹线沿第一表面105或第二表面106延伸的第一部分，以及与第一部分成一体的、从该迹线延伸到小孔区域中并接合到触点的第二部分。
在再一个实例中，尽管未示出，但微电子元件的背面可倒装粘结到第二支撑元件的第二表面106，并且微电子器件的前(触点承载)面可相反背离支撑元件104的第一表面106，且微电子元件的触点124'背离第二表面106。在此类实例中，触点124'可通过在安置触点124'的触点承载面129上方延伸的导电结构，而与第二表面106处的对应触点电耦接。例如，焊线、引线、带式连接结构等等可用于提供导电互连。
如在图1中可进一步看出，微电子封装10可包括感光材料的图案化层130，其在第一支撑元件的第二表面103上方的一定高度处具有表面131。如在图1中可进一步看出，图案化层130具有多个开口133，这些开口与第一支撑元件102的第二表面103处的对应导电第一元件132对齐。参见图1A，所述多个开口中的每一者具有截面尺寸134，该截面尺寸保持恒定或随着从第一支撑元件的第二表面103的高度而单调递增。
如在图1中可进一步看出，粘结材料的导电块136与第一元件132电耦接，并且远离第一元件132凸出穿过图案化层的对应开口133。在一个实例中，块可包含粘结金属，例如锡、铟、焊料或低共熔材料。在其他实例中，块可包含嵌入聚合物材料中的金属颗粒的导电基体材料。在一个实例中，块在微电子组件的竖直方向180上可具有20与500微米(下文称“微米”)之间的竖直高度。第二方向178或179平行于第一支撑元件的表面103在其中延伸的平面，在该第二方向上，每个柱的竖直尺寸通常大于相邻第一元件132的最小中心区节距“a”的一半。
在图案化层130内，每个块136具有截面尺寸134，该截面尺寸由块从中凸出的对应开口130的截面尺寸限定。因此，块136的截面尺寸至少在图案化层130内的高度处保持恒定或单调递增。所述块凸出在图案化层130的表面131上方，并且与第二支撑元件的表面106处的对应导电第二元件152接合。如在图1中可看出，块136可具有球状部分138，其中所述块在图案化层的表面131与第二元件152之间延伸。
如在图1中可进一步看出，囊封层150可形成为与第二支撑元件104的第二表面106相接触，并且可形成为与图案化层的表面131并与块136的表面相接触。在一个实施例中，囊封层150可形成为与微电子元件120的边缘表面127和主表面129相接触。或者，囊封层150可形成为与覆盖在边缘表面127上的一层或多层材料(未示出)相接触，和/或可形成为与覆盖在微电子元件129的主表面129上的一层或多层材料(未示出)相接触，使得囊封层150覆盖在微电子元件129的边缘表面127、主表面129任一者或边缘表面和主表面两者上，但不接触这些表面。在一个实例中，一层或多层材料可为或可包括第二囊封层，该第二囊封层覆盖在微电子元件120的一个或多个主表面129和一个或多个边缘表面127上。
囊封层150可包含聚合物材料或基本上由聚合物材料组成。制成囊封层的材料的例子为灌封化合物、环氧树脂、液晶聚合物、热塑性塑料和热固性聚合物。在具体实例中，囊封层可包含聚合物基体和聚合物基体内的颗粒装填材料，诸如通过将含有颗粒装填材料的未固化聚合物材料模制或以其他方式沉积到图案化层130的表面131上而形成。在一个实例中，颗粒装填材料可任选地具有低热膨胀系数(“CTE”)，使得所得囊封层150可具有低于10百万分率/摄氏度(下文称“ppm/℃”)的CTE。在一个实例中，囊封层可包含填料材料，诸如玻璃或陶瓷介电填料或半导体填料等等。
在上述实施例的任一个或全部的一种变型中，可从微电子组件10省略所述多个第一端子或所述多个第二端子中的一者。在这种情况下，第一元件可通过安置在其间的导电块136而与第二端子电耦接，或第二元件可通过安置在其间的导电块136而与第一端子电耦接。在上述实施例的任一个或全部的一种变型中，微电子元件120可安装到第一支撑元件102的表面103，而非安装到第二支撑元件104的表面106。
图2示出了板级组件110，该板级组件包括根据上文描述的微电子组件10或封装，以及在其表面112处具有多个触点144的电路面板108，这些触点通过导电接合元件146与微电子组件10的第二端子142对齐并接合到所述第二端子。接合元件可包括一个或多个导电块146，诸如由如上文结合块136所述的材料构成，或其可包括导电实心金属柱，例如具有基本上由铜组成的整体式金属区域的柱，并且其大致呈圆柱形或截头圆锥形的形状，且当在截面中观察时，大致呈矩形或梯形。
图3示出了微电子封装10的组件14，其中多个微电子组件10或封装通过它们各自的第一端子141、与其对齐的第二端子142以及与各自的成对第一端子和第二端子接触的导电接合元件16，而彼此堆叠和电耦接。微电子组件10之一可具有与电路面板108的触点耦接的第二端子142，如上文结合图2所述。
参见图4，在根据上述组件10的一种变型的微电子组件20或封装中，设置了第二微电子元件220，其覆盖在第一支撑元件102的第一表面101上，并且可从微电子组件20省略第一端子。第二微电子元件220可通过设置在第一支撑元件102上的接线154以及通过块136，而与导电第二元件152电耦接。第二微电子元件220可通过接线154、块136和第二元件152，而与第二端子142电耦接。在另一种变型(未示出)中，可从微电子组件20省略第二端子，而除了接线154之外还将大致在第二支撑元件102的表面101处设置第一端子。在这种情况下，第二微电子元件220可与第一端子电耦接(例如，在根据图1的位置处)，并且可通过设置在第一支撑元件102上的接线154以及块136，而与其电耦接。
现在转到图5至12，现将描述用于制造根据本发明实施例的微电子组件的方法。如在图5中可看出，设置了具有上述特征的第一支撑元件102或内插器。如在图6中可看出，设置了感光材料的第一层130，其覆盖在第一支撑元件102的第二表面103上。在一个实例中，感光材料可为诸如SU8的负性光致抗蚀剂材料，其更具体地讲可为诸如SU8-2150的材料，其厚度162可在从约20微米且最多至650微米范围内，并且一旦其通过适当加工(例如，图案化后的热处理或辐射处理)而发生交联，就将为永久层。可通过旋涂或辊涂方法等等，将第一层的感光材料(例如，SU8)施加到支撑元件的第二表面103或覆盖在第二表面103上。在一个实施例中，厚度162可为200微米。在施加第一层130之后，将感光材料的临时层164施加到第一层的表面131或覆盖在表面131上。在一个实例中，临时层可为可在图案化后移除的干膜。临时层164的厚度166可在50微米与300微米之间的范围内。在一个实例中，厚度166可为100微米。
此后，如在图7中可看出，临时层164被图案化(诸如通过光刻法)，以在其中形成小孔。然后可使用这些小孔对第一层130进行图案化(诸如通过蚀刻或光刻法)，以在其中形成与临时层中的图案对齐的开口133，其中第一元件132的表面至少部分地暴露于开口133内。在一个实例中，开口133在方向178、179(图1)上的横向尺寸168保持恒定，或在第一元件132上方延伸到临时层的表面165的方向180'上单调递增。在开口133形成的同时或在不同时间，可使用相同或类似的加工在临时层164和第一层130中形成较大的开口135，该开口135在方向178和179上的横向尺寸大于微电子元件120(图1)，使得开口135至少部分地容纳微电子元件120。
在图8中所见的阶段中，可用导电材料的块136填充开口133，所述导电材料诸如(例如)为与助焊剂、溶剂或其他挥发性材料、或粘结剂中的一者或多者混合的金属浆料或金属薄片或金属颗粒材料，所述材料可回流或在受到充分热处理时发生硬化。在具体实例中，非限制性地，所述材料可为包含焊料、锡、铟、银、金或铜中的一者或多者的颗粒的浆料。在另一个实例中，所述材料可为可永久固化或硬化的导电材料。在一个实例中，可使用具有越过临时层164的表面165的头部的工具，通过导体浆料的丝网印刷、镂花涂装或点胶中的一者或多者来填充开口133。
图9描绘了加热其中所示的结构的任选阶段，此时，若在其中沉积的材料为可回流材料，则使导电材料的块136在开口133内回流。或者，若导电材料为可永久固化或硬化的导电材料，则如果需要，可施加一定量的干燥或加热以使材料部分地固化。在一个实例中，可通过加热到某一温度而使这种可固化导电材料部分地固化，该温度低于构成导电材料的聚合物材料的玻璃化转变温度。或者，在上述加工的一种变型中，可通过将熔融状态的粘结金属(例如，焊料、锡、铟或低共熔混合物)注入开口133中，诸如通过分批加工，来填充开口133。
参见图10，现在可移除临时层，以使得块136的部分凸出在第一层130的表面131上方。在一个实例中，通过溶解，例如通过针对第一层130的材料选择性地洗涤或蚀刻，来移除临时层。在一个实例中，第一子组件170(包括支撑元件102、其上的第一层130及凸出在第一层的表面131上方的导电材料的块136)准备好与另一个部件进行进一步装配。因此，如在图11中可看出，导电材料的块136与第二子组件172的第二支撑元件104的表面106处的对应导电第二元件152对齐。第一层130中的开口135与微电子元件120对齐。然后，第一子组件170和第二子组件172可集合在一起，使得块136接触第二元件152或紧密接近地安置。当块136包含可回流材料时，块136可随后回流而与第二元件152形成具有图1中所见的外观的连接，其中块136的球状部分138出现于第一层的表面131上方。或者，可固化或可硬化材料的块136可在与第二元件152相接触之后固化或硬化，以与其形成永久连接。
参见图12，在上述加工的一种变型中，可在装配第一子组件170和第二子组件172之前，将具有可回流块136的第一子组件170加热到回流温度。以这种方式，凸出在第一层的表面131上方的块部分可回流而形成球状部分138。然后可诸如通过如下方式进行第一子组件和第二子组件彼此的进一步装配以形成微电子组件10(图1)：将块136与对应的第二元件152对齐并将开口135与微电子元件120对齐，使块的球状部分138与第二元件152相接触，然后使至少球状部分138回流以形成块136与第二元件152之间的连接。
此后，另外参考图1，可使用诸如上述的囊封剂材料形成囊封层150。在一个实例中，可将组件10放入模具中并将囊封剂注入第一子组件170和第二子组件172之间的空间中，使得囊封剂接触块136的表面，所述表面可为块的笔直部分或球状部分138。囊封剂可接触感光材料的第一层的表面131，并且可接触第二支撑元件的第二表面106。囊封剂可接触微电子元件120的表面127和129。可在组件仍在模具中时实现囊封剂的固化或部分固化，或可通过后续加工来固化囊封剂。在适用于本文所述的任何或所有微电子组件10、20的一个实例中，可在联合第一子组件170和第二子组件172以形成组件20之前，先用第二囊封层176部分地或完全地覆盖微电子元件120的表面127、129，如图13中所见。囊封层150可形成为与微电子元件120相接触和/或与微电子元件120的表面上所形成的第二囊封层176相接触。
图13描绘了根据上述加工的一种变型的、如图4中所见的微电子组件20的制造中的阶段。如在图13中可看出，微电子子组件174可包括第一支撑元件102和安装到表面101的微电子元件220，所述表面面向由所述微电子元件构造而成的组件20的向外方向。微电子元件220的触点224和/或224'可通过第一支撑元件102上的接线154以及通过第一元件132，而与导电材料的块136电耦接。然后，块136可以诸如上文结合图11或图12所述的方式，与第二子组件上的对应第二元件152对齐和接合。形成囊封层150的进一步加工可以如上所述的方式进行。
上文所论述的结构提供了出色的三维互连能力。这些能力可与任何类型的芯片一起使用。仅以举例的方式，下列芯片的组合可包括在如上所论述的结构中：(i)处理器和与处理器一起使用的存储器；(ii)相同类型的多个存储器芯片；(iii)不同类型的多个存储器芯片，诸如DRAM和SRAM；(iv)图像传感器和用于处理来自传感器的图像的图像处理器；(v)应用型专用集成电路(“ASIC”)和存储器。上文所论述的结构可用于构造各式各样的电子系统。例如，参见图14，根据本发明的另一个实施例的系统500包括与其他电子部件508和510相结合的上述结构506。在所述的实例中，部件508为半导体芯片，而部件510为显示屏，但可以使用任何其他部件。当然，尽管为了图示清楚起见，在图14中仅描绘了两个额外部件，但该系统可包括任何数量的此类部件。如上所述的结构506可为例如之前在上文所论述的微电子封装，或可为诸如上文针对图1、2、3或4所论述的微电子组件。结构506以及部件508和510安装在用虚线示意性描绘的共同外壳501中，并且在必要时彼此电互连以形成所需的电路。在示出的示例性系统中，该系统包括电路面板502，诸如柔性印刷电路板，并且该电路面板包括将部件彼此互连的许多导体504，在图14中仅示出了其中一个。然而，这仅是示例性的；可以使用任何适于进行电连接的结构。外壳501被描绘为可用于例如移动电话或个人数字助理的便携式外壳，并且屏幕510暴露在外壳的表面处。如果结构506包括光敏元件诸如成像芯片，则还可提供用于将光路由至该结构的透镜511或其他光学装置。此外，图14中所示的简化系统也仅是示例性的；可以使用上文所论述的结构制成其他系统，包括通常被视为固定结构的系统，诸如台式计算机、路由器等。
由于在不脱离本发明的前提下可以使用上述特征的这些和其他的变型和组合，所以，以上优选实施例的描述应看作是说明性的，而不是限制由权利要求书所限定的本发明。

Claims (20)

1.一种微电子组件，包括：
第一支撑元件和第二支撑元件，每个支撑元件具有第一表面，所述第一表面面向所述组件的向外方向，并且每个支撑元件具有第二表面，所述第二表面面向所述组件的向内方向、朝向所述第一支撑元件和所述第二支撑元件中的另一者的第二表面，以及以下各项中的至少一者：所述第一支撑元件的所述第一表面处的第一端子，或所述第二支撑元件的所述第一表面处的第二端子；
所述第一支撑元件的所述第二表面处的导电第一元件；
感光材料的图案化层，所述图案化层覆盖在所述第一支撑元件的所述第二表面上，并且具有与所述第一元件对齐的开口，每个开口所具有的截面尺寸保持恒定，或随着从所述第一支撑元件的所述第二表面的高度而增加；
粘结材料的导电块，所述导电块穿过所述图案化层的所述对应开口，而与所述第一元件电耦接并凸出在所述第一元件上方，每个块具有截面尺寸，所述截面尺寸由所述块从中凸出的所述对应开口的截面尺寸限定；
微电子元件，所述微电子元件安装到所述第一支撑元件或所述第二支撑元件之一的所述第二表面；
所述第二支撑元件的所述第二表面处的导电第二元件，所述第二元件与所述块电耦接，并且通过所述块而与所述第一元件电耦接；以及
囊封层，所述囊封层覆盖在所述第二支撑元件的所述第二表面、所述图案化层的表面上，并且接触至少一些所述块，所述块延伸穿过所述囊封层的至少一部分。
2.根据权利要求1所述的微电子组件，
其中所述组件包括所述第一支撑元件的所述第一表面处的第一端子以及所述第二支撑元件的所述第一表面处的第二端子，所述第一端子通过所述第一元件、所述第二元件和其间的所述块而与所述第二端子电耦接，或
所述组件包括以下各项中的一者：
所述第一支撑元件的所述第一表面处的第一端子，所述第一端子通过其间的所述块而与所述第二元件电耦接；或
所述第二支撑元件的所述第一表面处的第二端子，所述第二端子通过其间的所述块而与所述第一元件电耦接。
3.根据权利要求1所述的微电子组件，其中所述块包括球状部分，其中所述块延伸穿过所述囊封层的所述至少一部分。
4.根据权利要求2所述的微电子组件，其中所述囊封层形成为与所述图案化层的所述表面相接触，并且与所述第二支撑元件的所述第二表面相接触。
5.根据权利要求2所述的微电子组件，其中所述微电子元件具有背离所述第二支撑元件的表面，并且所述囊封层为第一囊封层，所述第一囊封层形成为与以下各项中的至少一者相接触：所述微电子元件的所述表面，或所述微电子元件的所述表面上所形成的第二囊封层。
6.根据权利要求5所述的微电子组件，其中所述微电子组件包括在所述微电子元件的所述表面上形成的所述第二囊封层，并且所述第一囊封层形成为与所述第二囊封层相接触。
7.一种堆叠式多芯片微电子组件，所述堆叠式多芯片微电子组件包括根据权利要求2所述的微电子组件以及覆盖在所述第一支撑元件的所述第一表面上的微电子封装，所述微电子封装具有与所述微电子组件的所述第一端子连接的端子。
8.根据权利要求7所述的堆叠式多芯片微电子组件，其中所述第一端子的最小节距大于所述第一元件的最小节距。
9.根据权利要求8所述的堆叠式多芯片微电子组件，其中所述第一端子的所述最小节距与所述第二端子的最小节距相同。
10.一种堆叠式多芯片微电子组件，所述堆叠式多芯片微电子组件包括根据权利要求2所述的微电子组件，其中所述微电子组件包括所述第二端子而不包括所述第一端子，并且所述第二端子通过其间的所述块而与所述第一元件电耦接。
11.根据权利要求10所述的堆叠式多芯片微电子组件，还包括第二微电子元件和第二囊封层，所述第二微电子元件安装到所述第一支撑元件的所述第一表面，并且所述第二囊封层接触所述第一支撑元件的所述第一表面和所述第二微电子元件的表面。
12.根据权利要求11所述的堆叠式多芯片微电子组件，其中所述第二微电子元件通过所述第一元件并通过在其间电耦接的所述块，而与所述第二端子电耦接。
13.一种制造微电子组件的方法，所述方法包括：
接合第一子组件和第二子组件以形成组件，所述组件包括第一支撑元件和第二支撑元件，所述第一支撑元件具有面向第一方向的、面朝外的第一表面，并且所述第二支撑元件具有面向与所述第一方向相反的第二方向的、面朝外的第一表面，所述第一支撑元件在其面朝内的第二表面处具有导电第一元件，并且所述第二支撑元件在其面朝内的第二表面处具有导电第二元件，安装至少一个微电子元件，使之覆盖在所述第一支撑元件和所述第二支撑元件之一的所述第二表面上，感光材料的图案化层覆盖在所述第一支撑元件或所述第二支撑元件之一的所述第二表面上，所述图案化层具有开口，所述开口的截面尺寸保持恒定，或随着从所述图案化层位于其上的所述支撑元件的所述表面的高度而增加，并且所述组件还包括粘结材料的块，所述块从所述第一元件延伸穿过所述开口并与所述第二元件电耦接，所述块具有由所述开口的所述截面尺寸限定的截面尺寸；以及
使囊封剂流入所述第一子组件和所述第二子组件之间的空间中，从而形成与所述块的至少部分的表面接触的囊封层。
14.根据权利要求13所述的方法，其中以下中的一者：
所述组件包括所述第一支撑元件的所述第一表面处的第一端子以及所述第二支撑元件的所述第一表面处的第二端子，所述第一端子通过所述第一元件、所述第二元件和其间的所述块而与所述第二端子电耦接，或
所述组件包括以下中的一者：
所述第一支撑元件的所述第一表面处的第一端子，所述第一端子通过其间的所述块而与所述第二元件电耦接；或
所述第二支撑元件的所述第一表面处的第二端子，所述第二端子通过其间的所述块而与所述第一元件电耦接。
15.根据权利要求13所述的方法，还包括通过如下方式形成所述图案化层：沉积感光材料的第一层并沉积包括感光材料的临时层的临时层，对所述临时层进行光刻图案化以形成小孔，使用所述图案化临时层根据所述临时层中的所述小孔对所述第一层进行图案化以形成所述开口，接着用所述块填充所述开口，然后移除所述临时层使得所述块凸出到一定高度，所述高度大于所述第一层在所述图案化层位于其上的所述支撑元件的所述第二表面上方的高度。
16.根据权利要求15所述的方法，还包括在所述第一子组件和所述第二子组件的所述接合之前将所述块加热到回流温度，其中所述加热使所述块的凸出在所述第一层的所述表面上方的部分回流，所述回流的部分为球状。
17.根据权利要求14所述的方法，其中所述微电子元件具有背离所述第二支撑元件的表面，并且所述囊封剂的所述流动形成与以下各项中的至少一者相接触的第一囊封层：所述微电子元件的所述表面，或所述微电子元件的所述表面上所形成的第二囊封层。
18.根据权利要求17所述的方法，其中所述囊封剂的所述流动形成第一囊封层，所述第一囊封层与所述微电子元件的所述表面上形成的第二囊封层相接触。
19.根据权利要求14所述的方法，其中所述组件包括所述第二端子而不包括所述第一端子，并且所述第二端子通过其间的所述块而与所述第一元件电耦接。
20.根据权利要求14所述的方法，其中所述第一子组件还包括第二微电子元件和第二囊封层，所述第二微电子元件安装到所述第一支撑元件的所述第一表面，并且所述第二囊封层接触所述第一支撑元件的所述第一表面以及所述第二微电子元件的表面，所述第二微电子元件通过所述第一元件并通过电耦接在其间的所述块，而与所述第二端子电耦接。
CN201580020842.6A 2014-03-31 2015-03-26 叠层封装微电子组件的分批工艺制造 Pending CN106415824A (zh)

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