CN100483653C - 导电通道的制造方法和半导体器件及系统 - Google Patents
导电通道的制造方法和半导体器件及系统 Download PDFInfo
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Abstract
揭示了一种用来在半导体部件中形成导电通道的方法。该方法包括提供具有第一表面和相反的第二表面的基片(112)。在基片中形成至少一个在第一表面和相反的第二表面之间延伸的孔(118)。在限定所述至少一个孔的基片侧壁上形成籽晶层(128)，镀敷以导电层(130)，并在所述至少一个孔的剩余空间内引入导电或不导电的填充材料。还揭示了一种采用掩蔽孔形成通过基片的导电通道的方法。还揭示了具有包含本发明导电通道的基片的半导体部件和电子系统。
Description
技术领域
发明领域：本发明一般涉及半导体制造。更具体来说，本发明涉及用来制造半导体部件基片一个表面到该半导体部件基片相反表面的电互连的方法，更具体来说，涉及在晶片、插入件(interposer)、或其它基片中制造通道的方法。
背景
现有技术：半导体芯片可制成芯片两面均具有集成电路，或者可设计成与其它电子元件或其它半导体芯片相连接或互相作用。可使用插入件连接半导体器件和印刷电路板之类的两个电子元件，可使用接触板将半导体晶片与探测板相连，用来测试半导体晶片上的芯片。半导体芯片可由半导体晶片或其它大块基片材料制成，插入件和接触板可由硅、陶瓷或聚合物基片制成。
导电性内衬或填充的孔(下文称为＂通道＂)被用来将芯片一面的集成电路与该芯片另一面的集成电路、大地或其它偏压、另外的电子元件或另外芯片上的集成电路相连。通道还被用来为插入件或接触板相反面的结构提供电通信，所述结构可与接触垫或电子元件的其它结构对齐，在各种部件之间建立电连接。
集成电路不断的微型化产生了长宽比日益增大的通道，术语长宽比表示通道的高度或长度与宽度或直径之比。造成长宽比日益增长的一个因素是通道的宽度正在不断减小。已知的用来在通常约50微米宽的层叠芯片、插入件和接触板中填充大长宽比的通道的方法难以在填充这些通道的同时不在通道中形成空洞或小孔。通常可采用化学气相沉积(CVD)或物理气相沉积(PVD)在通道中衬入铜之类金属的籽晶层(seed layer)，然后电镀镀敷籽晶层。随着通道长宽比变大，要在通道中衬入或填充镀敷材料而不在其中造成孔洞、空洞或小孔变得更加困难，所述孔洞、空洞或小孔会对通道的导电性造成负面影响。
参见图1，图中显示了基片10的截面。该基片包括使用本领域已知的电镀法填充的通道12。使用电镀法在通道12的内部沉积镀敷着金属层14。电镀法是一种电化学法，通过该方法可将溶液中离子形式的金属沉积在浸没于包含所述金属离子形式的镀液内的基片上。电流由阳极通过电镀液，使得金属离子沉积在由基片金属的籽晶层提供的阴极上。如图所示，金属层14的表面不平整，在对通道12的填充直至完成时，该不平整的平面可能会导致在填充通道的接触物质中形成一个或多个空洞。在其它已知的方法中，可通过无电镀敷法填充通道。在无电镀敷法中，可采用例如等离子体增强的化学气相沉积(PECVD)形成籽晶层。将基片放置在包含溶于水溶液的金属离子和化学还原剂的镀液中，通过化学还原法使金属离子沉积在籽晶层上，从而在籽晶层上镀敷金属层。
图2说明了另一基片20的截面。该基片20包括以本领域已知的电镀法填充金属层24的通道22。金属层24在基片20上表面和下表面附近的沉积更加有效，使得通道22在基片上表面和下表面附近基本闭合，而通道的中部未填充。通道22的未填充部分26被称为小孔，小孔会降低通道22的电导率。
为避免在通道中形成空洞和小孔，已开发了其它方法来填充通道。图3是基片30的截面图。基片30包括正在使用本领域已知的无电镀敷填充的通道32。无电镀敷法也被称为浸镀法，在此方法中将基片30置于镀液中。如图所示，金属连续沉积在通道32侧壁上的籽晶层(未显示)上形成金属层34，直至通道32基本被金属填满。然而，图3的无电沉积法可能会在通道32中形成空洞或凹陷。另外，由于无电镀敷较慢，即镍之类的金属沉积的最大速率约为20微米/小时，延长沉积过程的时间是不适合的。例如，如果通道宽70微米，为使金属层34向着通道的中心内向生长以完全填满通道32，该沉积法要在通道32内部沉积约35微米(75微米/2)的金属约需要一又四分之三小时。
在另一种避免在通道中形成空洞和小孔的尝试中，使用了本领域称为无电底部填充法(electroless bottom fill process)的方法。图4显示基片40的截面图。基片40包括通道42以及沉积在通道42底部46的金属层44，该金属层44向着通道42的顶部48生长。通道42的底部46可具有合适的金属，例如铜(Cu)、镍(Ni)或钨(W)。底部填充法是朝一个向上的方向沉积金属层44，不是从通道42的侧面进行沉积(如图3所示)，不会在互相相向生长的层之间形成空洞和小孔。可以用铜进行底部填充法，以免由于铜的迁移而在通道中形成小孔。然而，由于通道可能深达例如700微米，无电镀敷以上述较慢的速率沉积金属，完全填满通道所需的时间将会是令人无法接受的长。从通道的底部进行电镀也是已知的，在此方法中将作为阴极的导体置于基片顶部，覆盖着通道的底部。然而，这种方法严重限制了可填充通道的晶片加工阶段，对形成于或将要形成于基片上的其它结构造成设计上的限制。
因此，需要有用来填充通道的一种改进的方法，该方法应比已知方法更快，不会在填满的通道中留下空洞、凹陷或小孔，而且制造成本不高。
发明内容
在本发明许多实施方式中，通过提供在半导体部件中形成导电通道的方法、以及由此制得的半导体部件，克服了上述难题。本发明形成导电通道的方法比已知方法更快，这是由于所述导电通道不是用电镀的或无电镀敷的金属完全填充的。另外，本发明的导电通道具有基本不含孔洞、空洞和小孔的导电材料环形层，使得该通道的电导率不会受影响。
用来在半导体部件中形成导电通道的方法的一个示例性实施方式包括：提供具有第一表面和相反的第二表面的基片。形成穿过该基片、从基片的第一表面延伸到第二表面的至少一个孔。在所述第一表面、第二表面和限定所述至少一个形成于基片中的孔的侧壁上施加籽晶层。除去覆盖在基片第一表面和相反的第二表面上的籽晶层，留下覆盖在所述至少一个孔的侧壁上的籽晶层。在侧壁上的籽晶层上镀敷导电层，在所述至少一个孔内剩余的空间填入导电的或不导电的填充材料。
在另一示例性的实施方式中，还揭示了第二种制造穿过基片的导电通道的方法。该方法包括提供具有第一表面和相反的第二表面的基片。在基片的第一表面上形成至少一个孔穴(cavity)。在所述基片的第一表面和限定所述至少一个孔穴的基片裸露区域上施加导电层。在所述至少一个孔穴的剩余空间内引入填充材料。导电层和填入至少一个孔穴的填充材料裸露在基片相反的第二表面上。
另一示例性的实施方式包括具有至少一个导电通道前体结构的中间半导体部件。该中间半导体部件包括具有第一表面和相反的第二表面的基片。所述至少一个导电通道前体结构延伸入基片的第一表面，在达到相反的第二表面之前在基片内终止。所述至少一个通道前体结构具有从第一表面延伸、包围着导电或不导电填充材料的环形导电层。
本发明另一示例性实施方式包括半导体部件，该半导体部件包括具有第一表面、相反的第二表面以及至少一个穿过它们之间的导电通道的基片。所述至少一条导电通道包括从基片的第一表面延伸到基片的第二表面的环状导电层。导电的或不导电的填充材料被环状导电层包围，从基片的第一表面延伸到相反的基片第二表面。
在另一实施方式中，本发明还涉及包括微处理器和至少一个与该微处理器通信的存储装置的系统。所述至少一个存储装置包括具有第一表面、相反的第二表面、和至少一个在此两个表面之间延伸的导电通道的基片。所述至少一个导电通道具有从基片的第一表面延伸到基片的相反第二表面的导电材料环形层。导电的或不导电的填充材料被导电材料环形层包围，从基片的第一表面延伸到相反的基片第二表面。所述存储装置还具有至少一个位于所述至少一个导电通道上面的结合垫。
附图简述
附图显示目前认为是实施本发明的最佳方式：
图1是使用本领域已知的电镀法填充的基片中通道的截面图；
图2是具有使用本领域已知电镀法基本填满的通道的基片的截面图；
图3显示具有使用本领域已知无电镀敷法填充的通道的基片的截面图；
图4是具有使用本领域已知的底部填充法填充的通道的基片的截面图；
图5A至图5G显示本发明用来填充通道的方法的示例性实施方式的过程；
图6A至图6H显示本发明用来填充通道的方法的示例性实施方式的过程；
图7A至图7B显示本发明用来形成通道的方法的另一实施方式的过程；
图8显示具有使用本发明形成的电互连的半导体部件；
图9是结合了使用本发明方法制造的电互连的电子系统的示意图。
本发明最佳实施方式
一般来说，本发明包括用来制造由半导体部件基片的一个表面到该基片相反表面的电互连即通道的方法。该通道可将半导体部件的各种电结构进行电连接，或者可用来与其它部件电连接。本领域普通技术人员不难明白，本发明制造通道的方法可用于需要电互连的插入件的制造以及接触板之类的其它基片的制造。在本文中，术语＂半导体部件＂表示丙包括由半导体晶片、其它大块半导体基片、以及可以根据本发明形成通过其中的通道的其它基片制造的电子元件。
参见附图，在附图中类似的结构和元件用相同或类似的数字表示，图中显示了用来制造通过晶片或其它基片厚度的通道的方法的各种实施方式。本领域普通技术人员不难明白，尽管本文所述的各个步骤说明了制造通道的方法，但是本文所述的各个步骤是整个半导体部件制造过程的一部分，而且可与其它制造过程结合。在本文中，术语＂基片＂表示其中可形成通道的任何支承结构，包括但不限于半导体晶片、插入件基片、接触板或其它基片基的结构。
本发明包括制造通过晶片或其它基片厚度的方法，其中所述通道包含导电衬里材料和填充材料。所述填充材料可以是导电材料或不导电材料。现在参见图5A，图中显示了半导体部件100的截面图。该半导体部件100包括具有第一表面114和相反的第二表面116的基片112。基片112可包括未加工的半导体晶片或其它基片，该基片上可形成包括一层或多层半导体层的各种加工层(process layer)或其它结构。基片112上还可包括通过蚀刻、沉积或其它已知技术制造的位于其上的有源(active)部分或其它可操作部分。基片112还可包括用于测试装置和将要进行测试的半导体器件(接触板)之间的插入件基片，或用于存储装置和封装中的系统之间用来在其它基片之间提供路径的插入件基片。在此示例性的实施方式中，基片112包括单晶硅之类的半导体材料。在其它实施方式中，基片112可为多晶硅、锗、覆有硅的玻璃(siliconon glass)、覆有硅的蓝宝石(silicon-on-sapphire)、陶瓷、聚合物或玻璃填充的环氧树脂材料。基片112还可以是任意其它已知的基片材料。
所述半导体部件100具有从基片112的第一表面114延伸到第二表面116的通道118。在示例性的实施方式中，所述通道118基本为圆柱形，被侧壁120的内表面所包围。在另外的实施方式中，通道118可具有其它形状，例如计时沙漏形或用来形成通道的任意其它形状。限定出通道118的上部边界122和下部边界124的基片112的两部分用虚线表示。为方便表示，下面的各附图中将省去通道118的上部边界122和下部边界124。
在所示的实施方式中，通过激光烧蚀在基片112中形成通道118，该通道代表性的直径约为10微米至2密耳或更大。当半导体部件100是用于层叠的芯片、插入件、接触板或其它已知电子元件时，通道118的直径通常约为50微米。由于随着集成电路的微型化，通道的长-宽比在不断减小，应当理解所形成的通道118的直径可约为30微米。本领域普通技术人员不难明白，任何适合用来在用于制造半导体部件100的基片112中形成通道的已知方法均可用来形成通道118，这些方法包括但不限于活性离子蚀刻(RIE)、光化学蚀刻之类的干蚀刻或任何其它已知的通道形成方法，根据基片的种类，所述活性离子蚀刻对基片的蚀刻速率可高达5微米/分钟。本领域普通技术人员还不难看出，所述通道118的直径和基片112的厚度可以根据半导体部件100的所需用途为任何所需的尺寸。
在基片112中形成了通道118后，便可对内表面120进行清洁除去激光烧蚀热量影响的基片材料。如果需要的话，在形成通道118之后，可用TMAH(氢氧化四甲铵)清洁通道118，这可使通道具有正方形横截面。
可在基片112的内表面120上镀敷对基片112材料种类适合的介电材料或绝缘材料的绝缘层126，使清洁过的内表面120钝化。所述绝缘层126可以是旋涂玻璃、热氧化物、ParyleneTM聚合物、二氧化硅、氮化硅、氮氧化硅、玻璃(即硼磷硅酸盐玻璃、磷硅酸盐玻璃或硼硅酸盐玻璃)、或本领域已知的具有低介电常数的任何电介质。进行钝化时，可采用任何已知的方法沉积绝缘层126，所述已知的方法包括，但不限于物理气相沉积(PVD)、CVD、低压化学气相沉积(LPCVD)、快速热氮化(RTN)、旋涂玻璃(SOG)法、流涂或任何其它已知方法。在其它实施方式中，绝缘层126可以是通过注射法或毛细管法或真空抽吸沉淀的绝缘聚合物，例如BT树脂、聚酰亚胺、苯并环丁烯或聚苯并噁唑。所述绝缘层126的厚度可例如约为1-5微米。如果基片112是陶瓷之类的电绝缘材料，可省去绝缘层126。
如图5B所示，在基片112的第一表面114和第二表面116a以及通道118的内表面120上沉积导电材料的籽晶层128，该籽晶层128镀敷在绝缘层126(图5A所示)上。为便于表示，在图5B和以后的各图中省去图5A中的绝缘层126。在所示的实施方式中，籽晶层128包含氮化钛(TiN)，通过CVD沉积。其它可用作籽晶层128的材料包括，但不限于钛(Ti)、氮化硅(Si3N4)、多晶硅、氮化钽(TaN)和铜。可用来沉积籽晶层128的其它沉积法包括PVD、原子层沉积(ALD)、PECVD、真空蒸发和溅射。很明显对用于沉淀籽晶层128的材料种类和沉淀方法的选择，将根据用来形成通过通道118的电互连的材料种类而改变。
如图5C所示，除去籽晶层128覆盖着基片112第一表面114和第二表面116的部分，使基片112的第一表面114和第二表面116裸露出来。在所示的实施方式中，通过化学机械平面化(CMP)之类的研磨平面化法除去籽晶层128。然而，籽晶层128的选择性去除可在掩蔽通道118内的籽晶层128后，通过任意其它已知方法进行，例如使用适用于构成籽晶层128的材料种类的蚀刻剂的湿蚀刻或干蚀刻。
也可在籽晶层128上覆盖保护层129。在进行CMP之前在籽晶层128上施涂保护层129，保护层129可防止CMP过程中产生的颗粒沉淀到通道118中。完成了CMP后，便可使用已知的技术除去保护层129，得到用于选择性沉淀导电材料的原始籽晶层128表面。
在另一示例性实施方式中，可在基片112的第一表面114和第二表面116上镀敷氮化物层，以防籽晶层128沉积在基片112的第一表面114和第二表面116上，为的是防止发生剥落，这种剥落可能会根据用来镀敷在基片112表面上的导电材料的种类和所用基片112的种类而产生。可将通道118掩蔽，以防氮化物层沉积在通道118中，或者可以在基片中形成通道118之前将氮化物层施加在基片112的第一表面114和第二表面116上。本领域普通技术人员不难看出，除使用氮化物层以外，还可使用任何能够防止籽晶层128沉积在基片112第一表面114和第二表面116上的其它材料。
如图5D所示，通过无电沉积法在籽晶层128上镀敷金属导电层130。该导电层130沉积在籽晶层128上，并不沉积在基片112裸露的第一表面114和第二表面116上，这是由于从这些表面上除去(或从不曾有过)籽晶层128，而无电沉积法需要籽晶层128来沉淀导电层130。通过选择性地从基片112的第一表面114和第二表面116除去籽晶层128，在通道118中留下籽晶层128，或者在通道中选择性地沉积导电层130，可以不需要随后的除去多余材料的CMP步骤。导电材料130的选择性沉淀减少了用作导电层的金属的量，从而降低了制造成本。另外，在通道118中选择性地沉淀导电层130有助于防止粘着问题，该问题在镀敷厚导电层130时可能发生。造成基片112的裸露第一表面114和裸露第二表面116的导电层剥落的应力大于通道118内的剥落应力。导电层130可包含任意种类的金属，包括但不限于镍、钴、铜、银、钛、铱、金、钨、钽、钼、铂、钯、镍磷(NiP)、钯磷(Pd-P)、钴磷(Co-P)、Co-W-P合金、上述金属的其它合金及其混合物。用于导电层130的金属种类和厚度根据半导体部件100所需的电导率和用途而异，可至少部分地用本领域已知的方程式R＝ρL/A由金属或导电层的电阻(R)决定。
通过在籽晶层128上镀敷合适金属的导电层130，制造出通过通道118的环形导电通路。无电镀敷法在通道118中形成了基本不含空洞或小孔的基本贴合(conformal)的镀层。由无电镀敷法形成的导电层130通常具有均匀的厚度和低孔隙率，会提供防腐蚀作用而且较硬。进行无电镀敷时，将基片112置于包含离子形式的要进行沉淀的金属的水溶液的镀液中。该水溶液还包含化学还原剂，使得金属无需使用电能便可沉淀。无电镀敷法中金属离子还原的驱动力和随后的沉淀由化学还原剂产生。只要充分搅拌(例如通过超声)该水溶液，确保水溶液中金属离子和还原剂浓度分布均匀，籽晶层128所有部位上的还原反应就是基本恒定的。
在另一示例性的实施方式中，使用浸镀法之类的浸入法在导电层130上衬以银或金。如果导电层130包含镍或钴，则使用银或金衬里代替镍或钴，这是由于银和金比镍和钴更稀有。银或金衬里会提高电导率，帮助浸润焊料，从而帮助确保焊料的无空洞填充，以及焊料与通道118侧壁的连续接触。
由于籽晶层128延伸到与基片112的第一表面114和第二表面116齐平的平面，沉积导电层130会使得导电层130的一小部分132延伸越过基片112的第一表面114或第二表面116。如果需要的话，可使用CMP或其它已知的去除方法除去这小部分132，使得如图5E所示，导电层130基本与基片112的第一表面114和第二表面116的平面齐平。
如图5E所示，通道118具有从第一表面114延伸到第二表面116的开口134，该开口134由导电层130所限定。尽管用来形成导电层130的无电镀敷法可能偶然会在导电层130中形成微小的凹陷或空洞，但是达到所需电导率要求的导电层130的厚度应满足使得任何空洞或凹陷都不会影响电导率。如图5F所示，在通道118的开口134中引入填充材料136。通过形成所需厚度的导电层130，并在通道118余下的开口中引入填充材料136，在基片的通道内提供物理支承的同时，通过导电层130保持提供导电通路。
根据填充的通道118所需的电导率和半导体部件100的预期用途，填充材料136可以是导电材料或不导电材料。例如，由于填充的通道118的电导率至少是最低限度地由导电层130的材料和厚度决定的，如果导电层130提供了足够的导电通路，可使用不导电的材料填充通道118的开口134。可用作填充材料136的物质的代表性、非限制性例子包括含硅填料，例如用作不导电填充材料136的使用旋涂法施加的旋涂玻璃(SOG)，或用作导电填充材料136的使用扩散法施加的多晶硅。使用刮板施涂，然后软熔的焊膏也可用作导电填充材料136。焊膏可包括低熔点焊料，Cu-Sn-Ag、Sn-Ag、其它已知焊料或它们的组合。其它可用的填充材料136包括，但不限于在开口134中丝网印刷(screen printed)的焊料、导电和不导电的聚合物、金属填充的硅、碳填充的油墨、各向同性或各向异性的导电粘合剂和导体填充的环氧树脂，例如银填充的环氧树脂糊剂。
如果通道118的开口134填充之后，有填充材料136延伸越过基片112的第一表面114或第二表面116的平面之外，可采用CMP或其它已知的平面化方法除去突出的填充材料136，从而如图5G所示依照本领域已知方法在通道118的一端或两端上形成结合垫138。填充材料136为覆盖在通道118上的结合垫138提供物理支承。尽管此示例性实施方式中所示的半导体部件100具有一个通道118，但是本领域技术人员不难理解，可使用所揭示的方法同时在半导体部件100中形成任意数量的通道118，并对其施加衬里和填充。
在另一示例性实施方式中，可使用掩蔽通道形成本发明的导电通道。图6A显示半导体部件200的截面图。该半导体部件200包括具有第一表面214和相反的第二表面216的基片212。基片212可包括未加工的半导体晶片或用于如上文所述像图5A的基片112一样的制造法中所用的其它基片材料。
半导体部件200包括部分穿透基片212的掩蔽通道218，该掩蔽通道218基本由第一表面214延伸通过基片212，该掩蔽通道218的底部213在距离基片212第二表面216不远处终止。可采用激光烧蚀法或如本文中图5A所述能够在基片112中形成通道118的任何其它方法在基片212中形成掩蔽通道218。掩蔽通道218由基片212内表面侧壁220限定。基片212限定出掩蔽通道218最上部边界的部分用虚线表示，为简化起见，在以下附图中略去该边界。
在图6A的示例性实施方式中，掩蔽通道218还可包括位于基片212中，延伸通过基片212的开口(与图5A的通道118中基本类似)，该开口上密封覆盖着覆盖层225，用幻线表示。覆盖层225充分密封住掩蔽通道218，使得被覆盖的通道大体上以与掩蔽通道218基本相同的方式填充。因此也可在形成掩蔽通道218底部213的覆盖层225上沉积籽晶层。在另一示例性实施方式中，覆盖层225可包括在基片212中形成掩蔽通道218之前结合在基片212上的金属层。然后可使用激光烧蚀部分地形成掩蔽通道218，然后采用干蚀刻法完全形成掩蔽通道218，该干蚀刻停止在覆盖层225的金属处。如果需要，可使用钝化层(未显示)使掩蔽通道218绝缘。
使用图6A的实施方式形成掩蔽通道218，可防止污染物和其它过程材料落在晶片夹217或其它支承结构上或对其造成污染。在制造过程中可使用晶片夹217支承半导体部件200，在下面各图中将略去晶片夹217。
可对掩蔽通道218的内表面220进行清洁，除去碎屑、残余材料或受到掩蔽通道218形成不利影响的基片材料。可在基片212内表面220上镀敷适用于基片212类型的介电材料或绝缘材料，使清洁过的内表面220钝化。为便于说明，图6A中未显示钝化层，但是本领域普通技术人员不难理解，掩蔽通道218的钝化层可与参照图5A所述的绝缘层126基本类似。另外，根据基片212的材料情况，可省去绝缘层。
参见图6B，图中显示的半导体部件200上，在基片212第一表面214上和掩蔽通道218的内表面220上形成导电金属的籽晶层228。在所示的实施方式中，籽晶层228为TiN，通过CVD沉积。然而，籽晶层228可以是参照图5B的籽晶层128所述的其它材料。
如图6C所示，通过CMP法除去籽晶层228覆盖着基片212的第一表面214的部分，裸露出基片212的第一表面214。很明显也可采用上文所述的任意已知方法除去籽晶层228。如图6D所示，采用上文所述的无电沉积法在籽晶层228上沉积导电层230。由于基片212的第一表面214上没有籽晶层，导电层230不会附着在基片212的第一表面214上。导电层230可包含参照图5D的导电层所述的任意导电金属，用于导电层230的金属的种类和厚度要根据半导体部件200所需的电导率和最终用途改变。
在另一示例性实施方式中，在进行CMP之前在籽晶层228上施加保护层229。保护层229的存在可防止CMP产生的颗粒污染掩蔽通道218。进行CMP之后，采用已知的技术除去保护层229，得到用于随后导电层230沉积的原始表面。
当导电层230沉积在籽晶层228上时，导电层230的一部分232可能会延伸越过基片212第一表面214的平面。如果发生这种情况，可依照上文参照图5E所述，除去导电层230延伸越过第一表面214平面的部分232，制得图6E的半导体部件200。在另一示例性实施方式中，导电层230延伸在基片212第一表面214平面以上的部分232可保留下来，至少部分地用来形成随后形成于基片212第一表面214上的结合垫的至少一部分(见图6H)。
在另一示例性实施方式中，可通过浸镀法在导电层230上衬以银或金。如果导电层130包含镍或钴，可用银或金代替镍或钴，这是由于银和金更加稀有。在导电层130中衬以银或金还将提高电导率并有助于焊料浸润。
如图图6E所示，掩蔽通道218包括基本被导电层230围绕的开口，所述导电层230基本贯通基片212，从基片212的第一表面214延伸至掩蔽通道218底部上方。如图6F中斜线阴影所示，掩蔽通道218的开口234被填充材料236所填充。如上文参照图5F所述，根据填充的掩蔽通道218所需的电导率，填充材料236可包括导电或不导电的材料。
采用CMP之类的研磨平面化法或任意其它已知合适的去除法除去半导体部件200中基片212的第二表面216。依照图6F中虚线所示深度除去基片212材料，使得掩蔽通道218如图6G所示暴露于基片212的第二表面216。如图6H所示，依照本领域已知的方法在掩蔽通道218的相对端上形成结合垫238。在此示例性实施方式的一种变体中，如果掩蔽通道218如图6A所示延伸通过基片212到达覆盖层225，可除去覆盖层225，使衬有导电层230、填有填充材料236的掩蔽通道218裸露出来。
图7A和图7B显示了实施本发明方法的另一示例性实施方式。图中显示了的半导体部件200′。该半导体部件200′包括具有第一表面214和相反的第二表面216的基片212。在基片212的第一表面214上形成了阻挡层203。该阻挡层203包含能够防止籽晶层228沉积在其上的材料。阻挡层203可包含二氧化硅或氮化硅之类的含氧化物或含氮化物的材料。在基片212中形成通过阻挡层203的掩蔽通道218。在掩蔽通道218中形成籽晶层228和导电层230，然后如上文所述在掩蔽通道218剩余的开口中填充以填充材料。可如上所述完成导电掩蔽通道218的制造。
现在参见图8，图中显示了使用本发明方法制造的半导体部件300的部分截面图。该半导体部件300包括具有导电通道318的基片312。导电通道318包括填充材料336和用来形成位于半导体部件300相反表面的结合垫338之间电连接的环形导电衬里330。
半导体部件300可包括电路线340或其它互连件和接触结构，用来将通道318与接触垫342或其它导电结构连接。也可使用电路线340或其它导电结构将半导体部件300的电路连接到位于基片312相反面的集成电路之类的其它电路、在一层叠中位于半导体部件300上方或下方的另一半导体部件的电路、插入件、接触板或载体基片、例如支承着微处理器之类的其它半导体部件的母版或模块板。另外，也可在形成结合垫338的覆盖材料层上形成图案，形成从通道318到接触垫342的电路线340。因此导电通道318可用来使基片312第一表面314的接触垫342与基片312第二表面316的接触垫342产生电接触。
如上所述，半导体部件300的基片312可设计制造成连接各种半导体部件的插入件、半导体测试基片(接触板)或形成可与半导体芯片相连的更高级封装的载体基片。如果制成具有有源电路的半导体器件，可使半导体部件300的结合垫338或接触垫342以对应于测试基片或载体基片中终端垫的图案排列。如果用作插入件或接触板，可使结合垫338或接触垫342在基片312的一面上以对应于测试基片或载体基片的终端垫的图案排列，在另一面上以对应于将要接触的半导体器件上的结合垫或其它I/O部位的图案排列。
现在参见图9，图中显示了包括本发明导电通道的系统400的一个实施方式。该系统400至少有一个存储装置402，例如静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)或其它已知的存储装置，其中至少一个存储装置402中具有至少一个使用本发明方法制造的导电通道。该存储装置402与微处理器404操作耦合，该微处理器404可被编程用来执行本领域已知的特定功能。
本发明上述实施方式揭示了通道形式的电互连，该电互连可采用低成本材料制得，方法简单，制得的电互连稳固且基本不含空洞和小孔。尽管已结合各种示例性实施方式叙述和描述了本发明，但是可以在本发明范围或本质特征内进行各种添加、删除和修改。另外，尽管本文描述的是半导体器件或插入件，但是本发明可用于在任何半导体部件制成的器件或部件中形成电互连。因此，本发明的范围由所附的权利要求书而非上述说明书限定。位于权利要求书含义或等价范围之内的所有改变均包括在本发明范围内。
Claims (24)
1.一种用来在半导体部件中形成导电通道的方法，该方法包括：
提供具有第一表面和相反的第二表面的基片；
在选定的位置形成至少一个穿过该基片的孔，该至少一个孔由侧壁所限定，从所述基片的第一表面延伸到相反的该基片第二表面；
在所述基片的第一表面、所述基片相反的第二表面以及所述至少一个孔的侧壁上施加镀敷籽晶层；
除去所有覆盖在所述基片第一表面和相反的第二表面上的镀敷籽晶层；
在所述至少一个孔的侧壁上的镀敷籽晶层上镀敷导电层；
在所述至少一个孔内剩余的空间内引入填充材料。
2.如权利要求1所述的方法，其特征在于，形成所述至少一个通过基片的孔是通过激光烧蚀、干蚀刻和湿蚀刻中的至少一种进行。
3.如权利要求1所述的方法，该方法还包括在施加镀敷籽晶层之前对限定所述至少一个孔的侧壁进行清洁。
4.如权利要求1所述的方法，该方法还包括在施加镀敷籽晶层之前，在所述第一表面、相反的第二表面以及限定所述至少一个孔的侧壁上形成绝缘层。
5.如权利要求1所述的方法，该方法还包括在引入填充材料之后，在所述第一表面和相反的第二表面中至少一个表面上形成覆盖导电通道至少一部分的至少一个结合垫。
6.如权利要求1所述的方法，其特征在于，施加镀敷籽晶层包括采用化学气相沉积法、物理气相沉积法、原子层沉积法、等离子体增强的化学气相沉积法、真空蒸发或溅射法沉积导电材料。
7.如权利要求1所述的方法，其特征在于，除去覆盖在基片的第一表面上和相反的第二表面上的镀敷籽晶层是通过研磨平面化进行。
8.如权利要求1所述的方法，其特征在于，在镀敷籽晶层上镀敷导电层包括在镀敷籽晶层上无电镀敷金属材料。
9.如权利要求1所述的方法，其特征在于，向所述至少一个孔的剩余空间引入填充材料包括以下操作中的一种：在剩余空间中旋涂旋涂玻璃，使用扩散法在剩余空间沉积多晶硅，或在剩余空间中沉积焊膏或焊料。
10.如权利要求1所述的方法，其特征在于，引入填充材料包括引入导电的或不导电的填充材料。
11.如权利要求1所述的方法，该方法还包括：在所述至少一个孔的侧壁上施加保护层，以保护镀敷籽晶层部分；和在除去所有覆盖基片的第一表面和相反的第二表面的镀敷籽晶层之后，从所述至少一个孔的侧壁上的镀敷籽晶层部分上除去保护层。
12.一种用来在半导体部件中形成导电通道的方法，该方法包括：
提供具有第一表面和相反的第二表面的半导体基片；
形成至少一个通过所述半导体基片的选定位置、被侧壁所限定而且从所述半导体基片的第一表面延伸到其相反的第二表面的孔；
在所述至少一个孔的表面上形成镀敷籽晶层；
在所述至少一个孔的表面上的镀敷籽晶层上镀敷导电涂层；
将包含焊料的导电填充材料引入所述至少一个孔内。
13.如权利要求12所述的方法，其特征在于，所述焊料以熔融态形式流入所述至少一个通道内。
14.如权利要求12所述的方法，其特征在于，所述焊料通过丝网印刷引入所述至少一个通道内。
15.如权利要求12所述的方法，其特征在于，形成所述至少一个通过半导体基片的孔，是通过激光烧蚀、干蚀刻和湿蚀刻中的至少一种方法进行的。
16.如权利要求12所述的方法，该方法还包括，在引入所述导电填充材料之前对限定所述至少一个孔的侧壁进行清洁。
17.如权利要求12所述的方法，该方法还包括，在形成镀敷籽晶层之前，在所述第一表面、相反的第二表面以及限定所述至少一个孔的侧壁上形成绝缘层。
18.如权利要求12所述的方法，该方法还包括，在引入导电填充材料后，在所述第一表面和相反的第二表面中至少一个表面上形成覆盖所述导电通道的至少一部分的至少一个结合垫。
19.一种半导体部件，该半导体部件包括：
具有第一表面和相反的第二表面的半导体基片；和
至少一个通道，该通道包括：
在一个孔的表面上的镀敷籽晶层；
在所述孔的表面上的镀敷籽晶层上的导电涂层；和
从半导体基片的第一表面延伸到其相反的第二表面的包含焊料的导电填充材料，该导电填充材料被导电涂层所包围。
20.如权利要求19所述的半导体部件，该半导体部件还包括在所述半导体基片的第一表面和相反的第二表面中至少一个表面上的覆盖所述至少一个导电通道的至少一部分的至少一个结合垫。
21.如权利要求19所述的半导体部件，该部件还包括位于所述镀敷籽晶层和半导体基片之间的绝缘层。
22.一种系统，该系统包括：
微处理器；
至少一个与所述微处理器通信的存储装置，该存储装置包括：
具有第一表面和相反的第二表面的半导体基片；和
至少一个通道，该通道包括：
在一个孔的表面上的镀敷籽晶层；
在所述孔的表面上的镀敷籽晶层上的导电涂层；和
从所述半导体基片的第一表面延伸到其相反的第二表面的包含焊料
的导电填充材料，该导电填充材料被导电涂层所包围。
23.如权利要求22所述的系统，其特征在于，所述至少一个存储装置还包括在所述第一表面和相反的第二表面中至少一个表面上覆盖所述至少一个导电通道的至少一部分的至少一个结合垫。
24.如权利要求22所述的系统，该系统还包括位于所述镀敷籽晶层和半导体基片之间的钝化层。
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| US10/668,914 US7345350B2 (en) | 2003-09-23 | 2003-09-23 | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias |
| US10/668,914 | 2003-09-23 |
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| US (5) | US7345350B2 (zh) |
| EP (2) | EP2393109B1 (zh) |
| JP (2) | JP5093563B2 (zh) |
| KR (1) | KR20070006667A (zh) |
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- 2004-09-21 KR KR1020067005723A patent/KR20070006667A/ko active Search and Examination
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102668728A (zh) * | 2009-12-25 | 2012-09-12 | 株式会社藤仓 | 贯通布线基板及其制造方法 |
| CN102646785A (zh) * | 2011-02-21 | 2012-08-22 | 光颉科技股份有限公司 | 封装基板及其制造方法 |
| CN102646785B (zh) * | 2011-02-21 | 2015-12-16 | 光颉科技股份有限公司 | 封装基板及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2005031811A3 (en) | 2005-06-02 |
| TWI293793B (en) | 2008-02-21 |
| US7666788B2 (en) | 2010-02-23 |
| EP1668689B1 (en) | 2019-03-20 |
| JP5093563B2 (ja) | 2012-12-12 |
| CN1853262A (zh) | 2006-10-25 |
| US20050064707A1 (en) | 2005-03-24 |
| US7608904B2 (en) | 2009-10-27 |
| US8148263B2 (en) | 2012-04-03 |
| US20070166991A1 (en) | 2007-07-19 |
| JP2012235134A (ja) | 2012-11-29 |
| US20100133661A1 (en) | 2010-06-03 |
| US7345350B2 (en) | 2008-03-18 |
| EP2393109A1 (en) | 2011-12-07 |
| US20070170595A1 (en) | 2007-07-26 |
| EP2393109B1 (en) | 2021-09-15 |
| US9287207B2 (en) | 2016-03-15 |
| US20120156871A1 (en) | 2012-06-21 |
| WO2005031811A2 (en) | 2005-04-07 |
| JP2007520051A (ja) | 2007-07-19 |
| KR20070006667A (ko) | 2007-01-11 |
| EP1668689A2 (en) | 2006-06-14 |
| TW200512877A (en) | 2005-04-01 |
| JP5639120B2 (ja) | 2014-12-10 |
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