JP5218497B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5218497B2 JP5218497B2 JP2010176742A JP2010176742A JP5218497B2 JP 5218497 B2 JP5218497 B2 JP 5218497B2 JP 2010176742 A JP2010176742 A JP 2010176742A JP 2010176742 A JP2010176742 A JP 2010176742A JP 5218497 B2 JP5218497 B2 JP 5218497B2
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Description
(Au)−シリコン(Si)共晶接合により貼り合わされてなる構成としてもよい。これによっても、ベース基板とキャップ基板が導電性を確保した状態で強固に貼り合わされると共に、前記ベース基板の所定領域とキャップ基板とで構成される空間を完全密封することができる。
30,39,40 基板
31a トレンチ
Ce 部分領域
35 導電層
100〜110 半導体装置
Claims (28)
- 基板の第1表面から第2表面に亘って、当該基板を貫通するように形成されたトレンチによって、当該基板が複数の部分領域に分割され、
前記トレンチによって形成された前記部分領域の側壁に、前記第1表面の側から前記第2表面の側に亘って、当該基板より高い導電率を有する導電層が形成され、
前記導電層を介して、前記トレンチに絶縁体が埋め込まれてなる領域分割基板を用いた半導体装置であって、
半導体からなるベース基板であって、絶縁分離された複数個のベース半導体領域が表層部に形成されてなるベース基板と、
前記ベース基板に貼り合わされる前記領域分割基板を用いたキャップ基板と、を有してなり、
前記キャップ基板が、前記ベース基板の表層部における所定領域に対向して貼り合わされて、所定の前記ベース半導体領域に電気的に接続されてなる、引き出し導電領域として機能しており、
前記引き出し導電領域として機能する部分領域の側壁に前記導電層が形成されて、当該引き出し導電領域の抵抗値が小さくされていることを特徴とする半導体装置。 - 前記基板が、単結晶シリコンからなることを特徴とする請求項1に記載の半導体装置。
- 前記基板と前記導電層の間に、絶縁体層が形成されてなることを特徴とする請求項2に記載の半導体装置。
- 前記絶縁体層が、酸化シリコン層であることを特徴とする請求項3に記載の半導体装置。
- 前記導電層が、金属層、高不純物濃度シリコン層または金属シリサイド層、およびそれらの積層体からなることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
- 前記導電層が、前記トレンチの周りにおいて、前記第1表面および前記第2表面の少なくとも一方を覆うように形成されてなることを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。
- 前記絶縁体が、酸化シリコンからなることを特徴とする請求項1乃至6のいずれか一項に記載の半導体装置。
- 前記絶縁体が、前記第1表面の側から前記第2表面の側に亘って埋め込まれてなることを特徴とする請求項1乃至7のいずれか一項に記載の半導体装置。
- 前記キャップ基板において、前記ベース基板の前記所定領域に対向して凹部が形成され、
前記キャップ基板が、前記凹部の周りで前記ベース基板に貼り合わされてなることを特徴とする請求項1乃至8のいずれか一項に記載の半導体装置。 - 前記ベース基板または前記キャップ基板において、前記所定領域のベース半導体領域の部分に導電性を有する凸部が形成され、
前記ベース基板と前記キャップ基板が、前記凸部で貼り合わされてなることを特徴とする請求項9に記載の半導体装置。 - 前記凸部が、単結晶シリコン、多結晶シリコンまたは金属のいずれかからなることを特徴とする請求項10に記載の半導体装置。
- 前記ベース基板が、埋め込み酸化膜を有するSOI基板からなり、
前記ベース半導体領域が、前記埋め込み酸化膜に達するトレンチにより周囲から絶縁分離された、SOI層からなる領域であることを特徴とする請求項1乃至11のいずれか一項に記載の半導体装置。 - 前記半導体装置が、力学量センサ素子を有してなり、
前記複数個のベース半導体領域のうち、
少なくとも一個のベース半導体領域が、前記埋め込み酸化膜の一部を犠牲層エッチングすることにより、変位可能に形成された可動電極を有する可動半導体領域であり、
少なくとももう一個のベース半導体領域が、前記可動電極と対向する固定電極を有する固定半導体領域であり、
前記可動電極と固定電極の対向する面の間の前記空間を誘電体層とする静電容量が形成され、
前記可動半導体領域と前記固定半導体領域に、それぞれ、前記引き出し導電領域が接続され、
前記可動電極が、印加される力学量に応じて前記対向面に対して垂直方向に変位し、
前記可動電極と固定電極の間の距離変化に伴う前記静電容量の変化を測定して、前記印加される力学量を検出することを特徴とする請求項12に記載の半導体装置。 - 前記力学量が、加速度または角速度であることを特徴とする請求項13に記載の半導体装置。
- 前記キャップ基板を構成する前記基板が、単結晶シリコンからなり、
前記複数個の部分領域のうち、所定の部分領域に、IC回路が形成されてなることを特徴とする請求項1乃至14のいずれか一項に記載の半導体装置。 - 前記基板と前記導電層の間に、絶縁体層が形成されてなることを特徴とする請求項15に記載の半導体装置。
- 前記絶縁体層が、酸化シリコン層であることを特徴とする請求項16に記載の半導体装置。
- 前記IC回路が、前記キャップ基板における前記ベース基板の所定領域と対向する側に形成されて、前記貼り合わせにより密封される空間内に配置されてなることを特徴とする請求項16または17に記載の半導体装置。
- 前記IC回路が形成されてなる部分領域に、前記導電層が、該部分領域を包み込むようにして形成されてなることを特徴とする請求項16乃至18のいずれか一項に記載の半導体装置。
- 前記ベース基板と前記キャップ基板を構成する前記基板が、シリコン(Si)からなり、
前記ベース基板と前記キャップ基板が、シリコン(Si)直接接合により貼り合わされてなることを特徴とする請求項1乃至15のいずれか一項に記載の半導体装置。 - 前記ベース基板と前記キャップ基板を構成する前記基板が、シリコン(Si)からなり、
前記ベース基板と前記キャップ基板が、金(Au)−シリコン(Si)共晶接合により貼り合わされてなることを特徴とする請求項1乃至15のいずれか一項に記載の半導体装置。 - 前記ベース基板と前記キャップ基板が、導電性接着剤により貼り合わされてなることを特徴とする請求項1乃至19のいずれか一項に記載の半導体装置。
- 請求項1に記載の半導体装置の製造方法であって、
前記基板となる1次基板の前記第1表面の側に、前記トレンチとなる所定深さで当該1次基板を貫通しない1次トレンチを形成する1次トレンチ形成工程と、
前記1次トレンチの側壁を覆うようにして、前記導電層となる1次導電層を形成する1次導電層形成工程と、
前記絶縁体となる1次絶縁体を前記1次トレンチに埋め込む1次絶縁体埋め込み工程と、
前記第1表面の側から研削して、前記1次基板を露出し、前記基板の第1表面とする第1表面形成工程と、
前記1次絶縁体埋め込み工程の後、前記第2表面の側から研削して、前記基板の第2表面とすると共に、前記1次絶縁体を露出して、前記導電層および前記絶縁体とする第2表面形成工程とを有してなることを特徴とする半導体装置の製造方法。 - 前記1次導電層形成工程の後、前記1次絶縁体埋め込み工程を実施し、
前記1次絶縁体埋め込み工程の後、前記第1表面形成工程を実施することを特徴とする請求項23に記載の半導体装置の製造方法。 - 前記第1表面形成工程において、
前記第1表面の側から研削して、前記1次基板の上に形成された1次導電層を露出した後、該1次導電層をパターニングして前記1次基板を露出することを特徴とする請求項24に記載の半導体装置の製造方法。 - 前記1次絶縁体埋め込み工程において、
前記1次トレンチの下部に犠牲層を埋め込んだ後、その上部に前記絶縁体となる1次絶縁体を埋め込み、
前記第2表面形成工程において、
前記第2表面の側からの研削により前記基板の第2表面に露出する前記犠牲層を、エッチングにより除去することを特徴とする請求項24に記載の半導体装置の製造方法。 - 前記1次導電層形成工程の後、前記第1表面形成工程を実施し、
前記第1表面形成工程の後、前記1次絶縁体埋め込み工程を実施することを特徴とする請求項23に記載の半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記絶縁分離された複数個のベース半導体領域が表層部に形成されてなるベース基板を準備するベース基板準備工程と、
前記ベース基板に貼り合わされる前記領域分割基板を用いたキャップ基板であって、当該キャップ基板を構成する前記基板を貫通するトレンチにより、複数個の部分領域が形成されてなるキャップ基板を準備するキャップ基板準備工程と、
前記キャップ基板を、前記ベース基板の所定領域に対向するようにして、前記ベース基板に貼り合わせ、
前記空間を密封すると共に、前記引き出し導電領域を前記所定のベース半導体領域に電気的に接続する基板貼り合わせ工程とを有してなることを特徴とする請求項24乃至27のいずれか1項に記載の半導体装置の製造方法。
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-
2010
- 2010-08-05 JP JP2010176742A patent/JP5218497B2/ja not_active Expired - Fee Related
- 2010-10-12 US US12/902,696 patent/US8455973B2/en not_active Expired - Fee Related
- 2010-12-03 DE DE102010062419A patent/DE102010062419A1/de not_active Ceased
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2014517912A (ja) * | 2011-04-14 | 2014-07-24 | ロベルト・ボッシュ・ゲゼルシャフト・ミト・ベシュレンクテル・ハフツング | アウトオブプレーンスペーサが画成する電極 |
Also Published As
Publication number | Publication date |
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US20110133295A1 (en) | 2011-06-09 |
DE102010062419A1 (de) | 2011-06-09 |
US8455973B2 (en) | 2013-06-04 |
JP2011139018A (ja) | 2011-07-14 |
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