US8106511B2 - Reduced-stress through-chip feature and method of making the same - Google Patents
Reduced-stress through-chip feature and method of making the same Download PDFInfo
- Publication number
- US8106511B2 US8106511B2 US12/039,232 US3923208A US8106511B2 US 8106511 B2 US8106511 B2 US 8106511B2 US 3923208 A US3923208 A US 3923208A US 8106511 B2 US8106511 B2 US 8106511B2
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- United States
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- coefficient value
- layer
- electrically insulating
- cte
- semiconductor device
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- FIG. 2 an exemplary embodiment of an interconnect is shown.
Abstract
Description
Claims (24)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/039,232 US8106511B2 (en) | 2008-02-28 | 2008-02-28 | Reduced-stress through-chip feature and method of making the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/039,232 US8106511B2 (en) | 2008-02-28 | 2008-02-28 | Reduced-stress through-chip feature and method of making the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090218690A1 US20090218690A1 (en) | 2009-09-03 |
US8106511B2 true US8106511B2 (en) | 2012-01-31 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/039,232 Expired - Fee Related US8106511B2 (en) | 2008-02-28 | 2008-02-28 | Reduced-stress through-chip feature and method of making the same |
Country Status (1)
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US (1) | US8106511B2 (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6479382B1 (en) * | 2001-03-08 | 2002-11-12 | National Semiconductor Corporation | Dual-sided semiconductor chip and method for forming the chip with a conductive path through the chip that connects elements on each side of the chip |
US6534814B2 (en) * | 1993-09-16 | 2003-03-18 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor memory device having a trench capacitor with sufficient capacitance and small junction leak current |
US20050260812A1 (en) * | 2004-05-07 | 2005-11-24 | Christian Kapteyn | Memory cell having a trench capacitor and method for fabricating a memory cell and trench capacitor |
US20060148250A1 (en) | 2004-12-30 | 2006-07-06 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
US7199050B2 (en) * | 2004-08-24 | 2007-04-03 | Micron Technology, Inc. | Pass through via technology for use during the manufacture of a semiconductor device |
US20070166991A1 (en) * | 2003-09-23 | 2007-07-19 | Nishant Sinha | Methods for forming conductive vias in semiconductor device components |
US7425499B2 (en) * | 2004-08-24 | 2008-09-16 | Micron Technology, Inc. | Methods for forming interconnects in vias and microelectronic workpieces including such interconnects |
-
2008
- 2008-02-28 US US12/039,232 patent/US8106511B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6534814B2 (en) * | 1993-09-16 | 2003-03-18 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor memory device having a trench capacitor with sufficient capacitance and small junction leak current |
US6479382B1 (en) * | 2001-03-08 | 2002-11-12 | National Semiconductor Corporation | Dual-sided semiconductor chip and method for forming the chip with a conductive path through the chip that connects elements on each side of the chip |
US20070166991A1 (en) * | 2003-09-23 | 2007-07-19 | Nishant Sinha | Methods for forming conductive vias in semiconductor device components |
US20050260812A1 (en) * | 2004-05-07 | 2005-11-24 | Christian Kapteyn | Memory cell having a trench capacitor and method for fabricating a memory cell and trench capacitor |
US7199050B2 (en) * | 2004-08-24 | 2007-04-03 | Micron Technology, Inc. | Pass through via technology for use during the manufacture of a semiconductor device |
US7425499B2 (en) * | 2004-08-24 | 2008-09-16 | Micron Technology, Inc. | Methods for forming interconnects in vias and microelectronic workpieces including such interconnects |
US20060148250A1 (en) | 2004-12-30 | 2006-07-06 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
Also Published As
Publication number | Publication date |
---|---|
US20090218690A1 (en) | 2009-09-03 |
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