JP5093563B2 - 導電性構成部品、貫通ビア及び導電性貫通ウェーハ・ビアを含む半導体構成部品を製造するためのプロセス及び集積化スキーム - Google Patents
導電性構成部品、貫通ビア及び導電性貫通ウェーハ・ビアを含む半導体構成部品を製造するためのプロセス及び集積化スキーム Download PDFInfo
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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Description
到達水準:半導体チップは、チップの両面に集積回路を有するように製作することができ、或いは、他の電子構成部品や他の半導体チップと接続し又は相互作用するように設計することができる。インターポーザは、半導体デバイスやプリント回路板などの2つの電気構成部品をインタフェースするのに利用することができ、コンタクタ・ボードは、半導体ウェーハ上のダイを試験するためにその半導体ウェーハとプローブ・カードをインタフェースするのに使用することができる。半導体チップは、半導体ウェーハ又は他のバルク基板材料から形成することができ、インターポーザ及びコンタクタ・ボードは、シリコン、セラミック又はポリマー基板から形成することができる。
本発明は、幾つかの実施の形態においては、上記の困難を、半導体構成部品に導電性ビアを形成するための方法、及び該方法から得られる半導体構成部品を提供することによって克服する。導電性ビアが電気めっき又は無電解めっきされた金属で完全には充てんされないため、導電性ビアを形成する本発明の方法は、公知のプロセスよりも高速である。さらに、本発明の導電性ビアは、空洞、ボイド及びキーホールを実質的に含まず、そのため、ビアの導電率が損なわれない導電材料の環状層を含む。
発明を実施するための最良の形態
一般に、本発明は、半導体構成部品の基板の一方の表面からその基板の反対側の表面への電気相互接続、すなわちビアを製造するための方法を含む。ビアは、半導体構成部品の様々な電気構造を電気的に接続することができ、又は他の構成部品と電気的に接続するために使用することができる。当業者には明白なように、ビアを製造するための本発明の方法は、電気相互接続が要求されるインターポーザやコンタクタ・ボードなど他の基板を製造する際にも有用である。本明細書で使用されるとき、用語「半導体構成部品」は、半導体ウェーハ、他のバルク半導体基板、及び本発明に基づく貫通ビアの形成が可能な他の基板材料から製造された電子構成部品を意味し、このような電子構成部品を含む。
Claims (19)
- 半導体構成部品に導電性ビアを形成するための方法であって、
第1の表面及び対向する第2の表面を有する基板を設けるステップと、
側壁によって規定され、前記基板の前記第1の表面から前記基板の前記対向する第2の表面まで延びる、前記基板を貫通する少なくとも1つの穴を、選択された位置に形成するステップと、
前記基板の前記第1の表面、前記基板の前記対向する第2の表面及び前記少なくとも1つの穴の前記側壁にシード材料を付着させるステップと、
前記基板の前記第1の表面及び前記基板の前記対向する第2の表面の上にある前記シード材料を除去するために研磨平坦化を実施するステップと、
前記少なくとも1つの穴の前記シード材料に導電材料を無電解めっきするステップと、
前記少なくとも1つの穴の内部の残りの空間に充てん材料を導入するために、前記残りの空間の中にスピン・オン・ガラスをスピンコーティングするステップ、ポリシリコンを付着させるステップ、半田ペーストを付着させるステップ、および半田合金を付着させるステップのうちの一つを実施するステップ、
を含むことを特徴とする方法。 - 前記基板を貫通した前記少なくとも1つの穴を形成するステップが、レーザ・アブレーション、ドライエッチング及びウェットエッチングのうちの少なくとも1つによって実施されることを特徴とする請求項1に記載の方法。
- 前記シード材料を付着させるステップの前に、前記少なくとも1つの穴を規定する前記側壁を洗浄するステップをさらに含むことを特徴とする請求項1に記載の方法。
- 前記シード材料を付着させるステップの前に、前記基板の前記第1の表面、前記基板の前記対向する第2の表面及び前記少なくとも1つの穴の前記側壁に絶縁材料を形成するステップをさらに含むことを特徴とする請求項1に記載の方法。
- 前記導電材料の少なくとも一部分の上に重なる少なくとも1つのボンド・パッドを形成するステップをさらに含むことを特徴とする請求項1に記載の方法。
- 前記シード材料を付着させるステップが、化学蒸着プロセス、物理蒸着プロセス、原子層付着プロセス、プラズマ化学蒸着プロセス、真空蒸着又はスパッタリングを使用してシード材料を付着させるステップを含むことを特徴とする請求項1に記載の方法。
- 前記シード材料を前記導電材料で無電解めっきするステップが、前記シード材料を金属材料で無電解めっきするステップを含むことを特徴とする請求項1に記載の方法。
- 前記シード材料の表面にレジスト材料を塗布するステップと、前記研磨平坦化プロセスの実施後に前記レジスト材料を除去するステップとをさらに含むことを特徴とする請求項1に記載の方法。
- 半導体構成部品に導電性ビアを形成するための方法であって、
第1の表面及び対向する第2の表面を有する半導体基板を設けるステップと、
側壁によって規定され、前記基板の前記第1の表面から前記基板の前記対向する第2の表面まで延びる少なくとも1つの穴を、前記半導体基板の選択された位置に形成するステップと、
前記少なくとも1つの穴の面にシード材料を形成するステップと、
前記半導体基板の前記第1の表面と前記半導体基板の対向する前記第2の表面の上の前記シード材料を全面的に除去するための研磨平坦化プロセスと、ウエットエッチのいずれか少なくとも一方を実施するステップと、
前記少なくとも1つの穴の前記シード材料面に導電材料を無電解めっきするステップと、
前記少なくとも1つの穴に、半田合金を含む導電性充てん材料を付着させるステップと、
を含むことを特徴とする方法。 - 前記導電性充てん材料を付着させるステップは、前記少なくとも1つの穴に、溶融した半田合金を流し入れるプロセスを含むことを特徴とする請求項9に記載の方法。
- 前記導電性充てん材料を付着させるステップは、前記少なくとも1つの穴に、前記半田合金をスクリーン印刷するステップを含むことを特徴とする請求項9に記載の方法。
- 前記基板を貫通して前記少なくとも1つの穴を形成するステップが、レーザ・アブレーション、ドライエッチング及びウェットエッチングのうちの少なくとも1つによって実施されるステップを含むことを特徴とする請求項9に記載の方法。
- 前記導電性充てん材料を付着させるステップの前に、前記側壁を洗浄するステップをさらに含むことを特徴とする請求項9に記載の方法。
- 前記導電性充てん材料を付着させるステップの前に、前記第1の表面、前記対向する第2の表面及び前記側壁に絶縁材料を形成するステップをさらに含むことを特徴とする請求項9に記載の方法。
- 前記導電性充てん材料を導入するステップの後に、前記導電性材料の少なくとも一部分の上に重なる少なくとも1つのボンド・パッドを形成するステップをさらに含むことを特徴とする請求項9に記載の方法。
- 基板に導電性ビアを形成するための方法であって、
第1の表面及び対向する第2の表面を有する基板を設けるステップと、
前記基板の前記第1の表面に少なくとも1つのブラインドビアを形成するステップと、
前記少なくとも一つのブラインドビアの表面を酸化材料で被膜保護するステップと、
前記基板の前記第1の表面と前記少なくとも一つのブラインドビアの表面に被膜保護された前記酸化材料の表面とに銅シード材料を形成するステップと、
前記少なくとも一つのブラインドビアの前記シード材料の一部を保持する一方で、前記基板の前記第1の表面の上の前記銅シード材料を全面的に除去するための、研磨平坦化プロセスと、ウエットエッチのいずれか少なくとも一方を実施するステップと、
前記少なくとも一つのブラインドビアの前記シード材料を導電性材料で無電解めっきするステップと、
塗布法により、前記少なくとも1つのブラインドビアの残りの空間を、導電性材料で満たすステップと、
前記少なくとも1つのブラインドビア内の前記導電性材料を露出させるために、前記基板の前記対向する第2の表面に平坦化研磨プロセスを実施するステップと、
を含むことを特徴とする方法。 - 前記第1の表面に前記少なくとも1つのブラインドビアを形成するステップが、レーザ・アブレーション、ドライエッチング及びウェットエッチングのうちの少なくとも1つを実施するステップを含むことを特徴とする請求項16に記載の方法。
- 前記少なくとも一つのブラインドビアの表面を前記酸化材料で被膜保護するステップの前に、前記少なくとも1つのブラインドビアの表面をテトラメチルアンモニウムヒドロキシド溶液で洗浄するステップをさらに含むことを特徴とする請求項16に記載の方法。
- 前記導電性ビアの少なくとも一部分の上に重なる少なくとも1つのボンド・パッドを、前記導電性材料の少なくとも一部の表面に形成するステップをさらに含む、請求項16に記載の方法。
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US11772829B2 (en) | 2018-06-27 | 2023-10-03 | Mitsubishi Electric Corporation | Power supply device |
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US20100133661A1 (en) | 2010-06-03 |
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JP2007520051A (ja) | 2007-07-19 |
JP2012235134A (ja) | 2012-11-29 |
EP1668689A2 (en) | 2006-06-14 |
EP2393109B1 (en) | 2021-09-15 |
TW200512877A (en) | 2005-04-01 |
US20050064707A1 (en) | 2005-03-24 |
TWI293793B (en) | 2008-02-21 |
CN1853262A (zh) | 2006-10-25 |
EP2393109A1 (en) | 2011-12-07 |
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