ATE511703T1 - Herstellungsverfahren für durchkontakte - Google Patents

Herstellungsverfahren für durchkontakte

Info

Publication number
ATE511703T1
ATE511703T1 AT07709445T AT07709445T ATE511703T1 AT E511703 T1 ATE511703 T1 AT E511703T1 AT 07709445 T AT07709445 T AT 07709445T AT 07709445 T AT07709445 T AT 07709445T AT E511703 T1 ATE511703 T1 AT E511703T1
Authority
AT
Austria
Prior art keywords
wafer
connections
low resistivity
front side
layer
Prior art date
Application number
AT07709445T
Other languages
English (en)
Inventor
Edvard Kaelvesten
Tomas Bauer
Thorbjoern Ebefors
Original Assignee
Silex Microsystems Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silex Microsystems Ab filed Critical Silex Microsystems Ab
Application granted granted Critical
Publication of ATE511703T1 publication Critical patent/ATE511703T1/de

Links

Classifications

    • H10W20/4451
    • H10W70/635
    • H10W20/023
    • H10W20/0261
    • H10W20/211
    • H10W20/217
    • H10W70/662
    • H10W72/884
    • H10W74/00
    • H10W90/734
    • H10W90/754

Landscapes

  • Engineering & Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)
AT07709445T 2006-02-01 2007-01-31 Herstellungsverfahren für durchkontakte ATE511703T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE0600214 2006-02-01
PCT/SE2007/050052 WO2007089206A1 (en) 2006-02-01 2007-01-31 Vias and method of making

Publications (1)

Publication Number Publication Date
ATE511703T1 true ATE511703T1 (de) 2011-06-15

Family

ID=38327689

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07709445T ATE511703T1 (de) 2006-02-01 2007-01-31 Herstellungsverfahren für durchkontakte

Country Status (5)

Country Link
US (2) US9312217B2 (de)
EP (2) EP1987535B1 (de)
AT (1) ATE511703T1 (de)
SE (2) SE533308C2 (de)
WO (2) WO2007089207A1 (de)

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SE538058C2 (sv) 2012-03-30 2016-02-23 Silex Microsystems Ab Metod att tillhandahålla ett viahål och en routing-struktur
US9102517B2 (en) 2012-08-22 2015-08-11 International Business Machines Corporation Semiconductor structures provided within a cavity and related design structures
SE538062C2 (sv) * 2012-09-27 2016-02-23 Silex Microsystems Ab Kemiskt pläterad metallvia genom kisel
DE102013208816A1 (de) 2013-05-14 2014-11-20 Robert Bosch Gmbh Verfahren zum Erzeugen eines Durchkontakts in einem CMOS-Substrat
KR102245134B1 (ko) 2014-04-18 2021-04-28 삼성전자 주식회사 반도체 칩을 구비하는 반도체 패키지
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TW202247724A (zh) 2021-04-09 2022-12-01 美商山姆科技公司 填充有液態金屬填充物的縱橫比通孔
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WO2023129538A1 (en) * 2021-12-28 2023-07-06 Medtronic, Inc. Electrical component and method of forming same

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Also Published As

Publication number Publication date
US8324103B2 (en) 2012-12-04
SE0801620L (sv) 2008-10-30
WO2007089207A1 (en) 2007-08-09
EP1987535B1 (de) 2011-06-01
US20090195948A1 (en) 2009-08-06
WO2007089206A1 (en) 2007-08-09
SE533308C2 (sv) 2010-08-24
US20100052107A1 (en) 2010-03-04
EP2005467B1 (de) 2018-07-11
SE1050461A1 (sv) 2010-05-10
US9312217B2 (en) 2016-04-12
EP1987535A1 (de) 2008-11-05
EP2005467A4 (de) 2011-05-18
EP2005467A1 (de) 2008-12-24

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