ATE511703T1 - Herstellungsverfahren für durchkontakte - Google Patents

Herstellungsverfahren für durchkontakte

Info

Publication number
ATE511703T1
ATE511703T1 AT07709445T AT07709445T ATE511703T1 AT E511703 T1 ATE511703 T1 AT E511703T1 AT 07709445 T AT07709445 T AT 07709445T AT 07709445 T AT07709445 T AT 07709445T AT E511703 T1 ATE511703 T1 AT E511703T1
Authority
AT
Austria
Prior art keywords
wafer
connections
low resistivity
front side
layer
Prior art date
Application number
AT07709445T
Other languages
English (en)
Inventor
Edvard Kaelvesten
Tomas Bauer
Thorbjoern Ebefors
Original Assignee
Silex Microsystems Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silex Microsystems Ab filed Critical Silex Microsystems Ab
Application granted granted Critical
Publication of ATE511703T1 publication Critical patent/ATE511703T1/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49872—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing semiconductor material
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/181—Encapsulation
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT07709445T 2006-02-01 2007-01-31 Herstellungsverfahren für durchkontakte ATE511703T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE0600214 2006-02-01
PCT/SE2007/050052 WO2007089206A1 (en) 2006-02-01 2007-01-31 Vias and method of making

Publications (1)

Publication Number Publication Date
ATE511703T1 true ATE511703T1 (de) 2011-06-15

Family

ID=38327689

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07709445T ATE511703T1 (de) 2006-02-01 2007-01-31 Herstellungsverfahren für durchkontakte

Country Status (5)

Country Link
US (2) US8324103B2 (de)
EP (2) EP2005467B1 (de)
AT (1) ATE511703T1 (de)
SE (2) SE1050461A1 (de)
WO (2) WO2007089207A1 (de)

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US9266721B2 (en) 2010-11-23 2016-02-23 Robert Bosch Gmbh Eutectic bonding of thin chips on a carrier substrate
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SE538062C2 (sv) * 2012-09-27 2016-02-23 Silex Microsystems Ab Kemiskt pläterad metallvia genom kisel
DE102013208816A1 (de) 2013-05-14 2014-11-20 Robert Bosch Gmbh Verfahren zum Erzeugen eines Durchkontakts in einem CMOS-Substrat
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TWI769376B (zh) 2018-03-30 2022-07-01 美商山姆科技公司 導電性通孔及其製造方法
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SE0801620L (sv) 2008-10-30
WO2007089207A1 (en) 2007-08-09
US20100052107A1 (en) 2010-03-04
EP1987535B1 (de) 2011-06-01
EP2005467B1 (de) 2018-07-11
US20090195948A1 (en) 2009-08-06
EP2005467A1 (de) 2008-12-24
SE1050461A1 (sv) 2010-05-10
US8324103B2 (en) 2012-12-04
US9312217B2 (en) 2016-04-12
EP2005467A4 (de) 2011-05-18
WO2007089206A1 (en) 2007-08-09
SE533308C2 (sv) 2010-08-24
EP1987535A1 (de) 2008-11-05

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