SE0700172L - Metod för mikrokapsling och mikrokapslar - Google Patents

Metod för mikrokapsling och mikrokapslar

Info

Publication number
SE0700172L
SE0700172L SE0700172A SE0700172A SE0700172L SE 0700172 L SE0700172 L SE 0700172L SE 0700172 A SE0700172 A SE 0700172A SE 0700172 A SE0700172 A SE 0700172A SE 0700172 L SE0700172 L SE 0700172L
Authority
SE
Sweden
Prior art keywords
wafer
insulating material
analogue
digital
microcapsulation
Prior art date
Application number
SE0700172A
Other languages
English (en)
Other versions
SE533579C2 (sv
Inventor
Thorbjoern Ebefors
Edvard Kaelvesten
Tomas Bauer
Original Assignee
Silex Microsystems Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silex Microsystems Ab filed Critical Silex Microsystems Ab
Priority to SE0700172A priority Critical patent/SE533579C2/sv
Priority to EP08705365.8A priority patent/EP2121511B1/en
Priority to US12/523,811 priority patent/US20100053922A1/en
Priority to EP08705364.1A priority patent/EP2106617B1/en
Priority to US12/523,786 priority patent/US20090302414A1/en
Priority to TW097103022A priority patent/TWI461348B/zh
Priority to PCT/SE2008/050093 priority patent/WO2008091221A2/en
Priority to PCT/SE2008/050092 priority patent/WO2008091220A1/en
Publication of SE0700172L publication Critical patent/SE0700172L/sv
Publication of SE533579C2 publication Critical patent/SE533579C2/sv
Priority to US13/566,081 priority patent/US8598676B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0077—Other packages not provided for in groups B81B7/0035 - B81B7/0074
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/008—Aspects related to assembling from individually processed components, not covered by groups B81C3/001 - B81C3/002
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6688—Mixed frequency adaptations, i.e. for operation at different frequencies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Geometry (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Element Separation (AREA)
  • Packages (AREA)
SE0700172A 2007-01-25 2007-01-25 Metod för mikrokapsling och mikrokapslar SE533579C2 (sv)

Priority Applications (9)

Application Number Priority Date Filing Date Title
SE0700172A SE533579C2 (sv) 2007-01-25 2007-01-25 Metod för mikrokapsling och mikrokapslar
EP08705365.8A EP2121511B1 (en) 2007-01-25 2008-01-25 Method of packaging an electronic or micromechanical component
US12/523,811 US20100053922A1 (en) 2007-01-25 2008-01-25 Micropackaging method and devices
EP08705364.1A EP2106617B1 (en) 2007-01-25 2008-01-25 Trench isolation for reduced cross talk
US12/523,786 US20090302414A1 (en) 2007-01-25 2008-01-25 Trench isolation for reduced cross talk
TW097103022A TWI461348B (zh) 2007-01-25 2008-01-25 微封裝方法及裝置
PCT/SE2008/050093 WO2008091221A2 (en) 2007-01-25 2008-01-25 Micropackaging method and devices
PCT/SE2008/050092 WO2008091220A1 (en) 2007-01-25 2008-01-25 Trench isolation for reduced cross talk
US13/566,081 US8598676B2 (en) 2007-01-25 2012-08-03 Barrier structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE0700172A SE533579C2 (sv) 2007-01-25 2007-01-25 Metod för mikrokapsling och mikrokapslar

Publications (2)

Publication Number Publication Date
SE0700172L true SE0700172L (sv) 2008-07-26
SE533579C2 SE533579C2 (sv) 2010-10-26

Family

ID=39644725

Family Applications (1)

Application Number Title Priority Date Filing Date
SE0700172A SE533579C2 (sv) 2007-01-25 2007-01-25 Metod för mikrokapsling och mikrokapslar

Country Status (5)

Country Link
US (3) US20090302414A1 (sv)
EP (2) EP2121511B1 (sv)
SE (1) SE533579C2 (sv)
TW (1) TWI461348B (sv)
WO (2) WO2008091221A2 (sv)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7745909B2 (en) * 2007-02-26 2010-06-29 International Business Machines Corporation Localized temperature control during rapid thermal anneal
US7759773B2 (en) 2007-02-26 2010-07-20 International Business Machines Corporation Semiconductor wafer structure with balanced reflectance and absorption characteristics for rapid thermal anneal uniformity
SE534510C2 (sv) 2008-11-19 2011-09-13 Silex Microsystems Ab Funktionell inkapsling
US8426233B1 (en) 2009-01-09 2013-04-23 Integrated Device Technology, Inc. Methods of packaging microelectromechanical resonators
CN101692441B (zh) * 2009-04-16 2012-04-11 旭丽电子(广州)有限公司 一种印刷电路板封装结构
SE537499C2 (sv) 2009-04-30 2015-05-26 Silex Microsystems Ab Bondningsmaterialstruktur och process med bondningsmaterialstruktur
DE102011006100A1 (de) * 2011-03-25 2012-09-27 Carl Zeiss Smt Gmbh Spiegel-Array
US8704428B2 (en) 2011-04-20 2014-04-22 Qualcomm Mems Technologies, Inc. Widening resonator bandwidth using mechanical loading
US8803269B2 (en) * 2011-05-05 2014-08-12 Cisco Technology, Inc. Wafer scale packaging platform for transceivers
JP5999833B2 (ja) * 2011-06-08 2016-09-28 日本電波工業株式会社 水晶デバイス
CN104507853B (zh) * 2012-07-31 2016-11-23 索泰克公司 形成半导体设备的方法
TWI576972B (zh) * 2013-01-18 2017-04-01 精材科技股份有限公司 半導體晶片封裝體及其製造方法
CN108290730A (zh) * 2015-11-30 2018-07-17 W.L.戈尔及同仁股份有限公司 用于裸芯片的保护环境阻隔件
CN108369285B (zh) * 2015-12-02 2022-04-26 深圳帧观德芯科技有限公司 半导体x射线检测器的封装方法
US10546816B2 (en) * 2015-12-10 2020-01-28 Nexperia B.V. Semiconductor substrate with electrically isolating dielectric partition
EP3182445B1 (en) * 2015-12-15 2020-11-18 Nexperia B.V. Semiconductor device and method of making a semiconductor device
US10410981B2 (en) * 2015-12-31 2019-09-10 International Business Machines Corporation Effective medium semiconductor cavities for RF applications
US11226402B2 (en) * 2016-06-09 2022-01-18 Ams Sensors Singapore Pte. Ltd. Optical ranging systems including optical cross-talk reducing features
US10510741B2 (en) * 2016-10-06 2019-12-17 Semtech Corporation Transient voltage suppression diodes with reduced harmonics, and methods of making and using
CN110710118B (zh) * 2017-06-02 2021-08-20 株式会社村田制作所 高频模块以及通信装置
US10319654B1 (en) * 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
CN108358160B (zh) * 2018-04-18 2023-08-01 中国兵器工业集团第二一四研究所苏州研发中心 吊装式可释放应力的mems器件封装结构
US10870575B2 (en) * 2018-06-29 2020-12-22 Infineon Technologies Dresden GmbH & Co. KG Stressed decoupled micro-electro-mechanical system sensor
TWI722348B (zh) * 2018-12-11 2021-03-21 創意電子股份有限公司 積體電路封裝元件及其載板

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5064771A (en) * 1990-04-13 1991-11-12 Grumman Aerospace Corporation Method of forming crystal array
JPH07321140A (ja) * 1994-05-19 1995-12-08 Toshiba Corp 半導体装置
US5767561A (en) * 1997-05-09 1998-06-16 Lucent Technologies Inc. Integrated circuit device with isolated circuit elements
EP0951068A1 (en) * 1998-04-17 1999-10-20 Interuniversitair Micro-Elektronica Centrum Vzw Method of fabrication of a microstructure having an inside cavity
FR2782843B1 (fr) * 1998-08-25 2000-09-29 Commissariat Energie Atomique Procede d'isolation physique de regions d'une plaque de substrat
US6524890B2 (en) 1999-11-17 2003-02-25 Denso Corporation Method for manufacturing semiconductor device having element isolation structure
TW523486B (en) * 2001-08-29 2003-03-11 Asia Pacific Microsystems Inc Structure of self-assembled, 3D Micro-Opto-Electro-Mechanical System and method of fabricating same
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US7004015B2 (en) * 2001-10-25 2006-02-28 The Regents Of The University Of Michigan Method and system for locally sealing a vacuum microcavity, methods and systems for monitoring and controlling pressure and method and system for trimming resonant frequency of a microstructure therein
TW560018B (en) * 2001-10-30 2003-11-01 Asia Pacific Microsystems Inc A wafer level packaged structure and method for manufacturing the same
WO2003054927A2 (en) * 2001-11-07 2003-07-03 The Board Of Trustees Of The University Of Arkansas Structure and process for packaging rf mems and other devices
JP2003174082A (ja) * 2001-12-06 2003-06-20 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6696645B2 (en) * 2002-05-08 2004-02-24 The Regents Of The University Of Michigan On-wafer packaging for RF-MEMS
US7554136B2 (en) * 2002-09-13 2009-06-30 Advantest Corporation Micro-switch device and method for manufacturing the same
US6621135B1 (en) * 2002-09-24 2003-09-16 Maxim Integrated Products, Inc. Microrelays and microrelay fabrication and operating methods
US7052939B2 (en) 2002-11-26 2006-05-30 Freescale Semiconductor, Inc. Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications
US6867060B2 (en) * 2002-11-27 2005-03-15 Intel Corporation Wafer-level packaging of electronic devices before singulation
JP4342174B2 (ja) * 2002-12-27 2009-10-14 新光電気工業株式会社 電子デバイス及びその製造方法
SE526366C3 (sv) 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
TWI223622B (en) * 2003-03-24 2004-11-11 Chien Hui Chuan Built-in high frequency induction-heating module for injection molding and thereof applications
US20040232535A1 (en) * 2003-05-22 2004-11-25 Terry Tarn Microelectromechanical device packages with integral heaters
US20040259325A1 (en) * 2003-06-19 2004-12-23 Qing Gan Wafer level chip scale hermetic package
US6930368B2 (en) * 2003-07-31 2005-08-16 Hewlett-Packard Development Company, L.P. MEMS having a three-wafer structure
US20050093134A1 (en) * 2003-10-30 2005-05-05 Terry Tarn Device packages with low stress assembly process
WO2005055317A1 (ja) * 2003-12-05 2005-06-16 Matsushita Electric Industrial Co., Ltd. パッケージされた電子素子、及び電子素子パッケージの製造方法
EP1695387A4 (en) 2003-12-10 2009-07-29 Univ California Office Of The SUBSTRATE WITH LITTLE TRANSMISSION FOR INTEGRATED MIX SIGNAL CIRCUITS
US6936918B2 (en) * 2003-12-15 2005-08-30 Analog Devices, Inc. MEMS device with conductive path through substrate
JP3875240B2 (ja) * 2004-03-31 2007-01-31 株式会社東芝 電子部品の製造方法
EP1585171A1 (en) 2004-04-07 2005-10-12 Andrea Pizzarulli An SOI circuit having reduced crosstalk interference and a method for forming the same
EP1738411A4 (en) * 2004-04-22 2012-06-27 Panasonic Corp SENSOR DEVICE, SENSOR SYSTEM, AND METHODS OF MANUFACTURING THEREOF
US7261793B2 (en) * 2004-08-13 2007-08-28 Hewlett-Packard Development Company, L.P. System and method for low temperature plasma-enhanced bonding
US7204737B2 (en) * 2004-09-23 2007-04-17 Temic Automotive Of North America, Inc. Hermetically sealed microdevice with getter shield
US7098070B2 (en) * 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
TWI246502B (en) * 2004-11-30 2006-01-01 Wen-Chang Dung Method for forming a separable interface and micro electromechanical film made therefrom
KR100594952B1 (ko) * 2005-02-04 2006-06-30 삼성전자주식회사 웨이퍼 레벨 패키징 캡 및 그 제조방법
US7262079B2 (en) * 2005-02-10 2007-08-28 Altera Corporation Consolidated flip chip BGA assembly process and apparatus
US7365382B2 (en) 2005-02-28 2008-04-29 Infineon Technologies Ag Semiconductor memory having charge trapping memory cells and fabrication method thereof
US7262622B2 (en) * 2005-03-24 2007-08-28 Memsic, Inc. Wafer-level package for integrated circuits
JP5151012B2 (ja) * 2005-05-30 2013-02-27 富士電機株式会社 半導体装置の製造方法
KR100661169B1 (ko) * 2005-06-03 2006-12-26 삼성전자주식회사 패키징 칩 및 그 패키징 방법
US7067397B1 (en) * 2005-06-23 2006-06-27 Northrop Gruman Corp. Method of fabricating high yield wafer level packages integrating MMIC and MEMS components
US7233048B2 (en) * 2005-08-26 2007-06-19 Innovative Micro Technology MEMS device trench plating process and apparatus for through hole vias
KR100692520B1 (ko) * 2005-10-19 2007-03-09 삼성전자주식회사 웨이퍼 레벨 패키징 캡 및 그 제조방법
US7763489B2 (en) * 2006-09-27 2010-07-27 Miradia, Inc. Method of forming a micromechanical system containing a microfluidic lubricant channel
US7911023B2 (en) 2007-11-06 2011-03-22 Denso Corporation Semiconductor apparatus including a double-sided electrode element and method for manufacturing the same
US7923808B2 (en) * 2007-11-20 2011-04-12 International Business Machines Corporation Structure of very high insertion loss of the substrate noise decoupling

Also Published As

Publication number Publication date
WO2008091220A1 (en) 2008-07-31
EP2106617B1 (en) 2021-06-02
US20100053922A1 (en) 2010-03-04
TW200848359A (en) 2008-12-16
EP2121511A2 (en) 2009-11-25
US20090302414A1 (en) 2009-12-10
US20120292736A1 (en) 2012-11-22
TWI461348B (zh) 2014-11-21
EP2121511A4 (en) 2014-07-02
US8598676B2 (en) 2013-12-03
SE533579C2 (sv) 2010-10-26
EP2121511B1 (en) 2017-08-16
EP2106617A4 (en) 2015-04-15
EP2106617A1 (en) 2009-10-07
WO2008091221A3 (en) 2008-09-18
WO2008091221A2 (en) 2008-07-31

Similar Documents

Publication Publication Date Title
SE0700172L (sv) Metod för mikrokapsling och mikrokapslar
SE0801620L (sv) Metoder för tillverkning av en startsubstratskiva för halvledartillverkning, med skivgenomgående anslutningar
TW200637041A (en) Nitride semiconductor light-emitting device and method for fabrication thereof
CN100595928C (zh) 半导体衬底、制备技术及在先进三维电子封装中的应用
FR2963982B1 (fr) Procede de collage a basse temperature
TW200725753A (en) Method for fabricating silicon nitride spacer structures
TW200633037A (en) Manufacturing method for semiconductor chips, and semiconductor chip
TW200727352A (en) Manufacturing method for semiconductor chips
WO2006112995A3 (en) Glass-based semiconductor on insulator structures and methods of making same
TW200607056A (en) Semiconductor chip-embedded substrate and method of manufacturing same
TW200715380A (en) Process for lateral disjonting of a semiconductor wafer and opto-electronic element
WO2012057893A3 (en) Multiple bonding layers for thin-wafer handling
TW200723394A (en) Manufacturing method for semiconductor chips, and semiconductor chip
TW200614507A (en) Finfet transistor process
WO2012052257A3 (de) Optoelektronischer halbleiterchip und verfahren zu dessen herstellung
TW200711066A (en) Manufacturing method for a semiconductor device, semiconductor device, circuit substrate and electronic device
WO2006012838A3 (de) Verfahren zur herstellung von halbleiterchips in dünnfilmtechnik und halbleiterchip in dünnfilmtechnik
TW200725745A (en) Method for forming semiconductor device having fin structure
WO2008087763A1 (ja) 半導体装置およびその製造方法
EP2230686A3 (en) Method of manufacturing semiconductor device
WO2012005540A3 (ko) 유기 발광 소자 및 이의 제조방법
TW200741934A (en) Wafer-shaped measuring apparatus and method for manufacturing the same
WO2009004889A1 (ja) 薄膜シリコンウェーハ及びその作製法
TW200739774A (en) Substrate for forming semiconductor components and manufacturing method of semiconductor components
CN109742151A (zh) 薄膜晶体管及其制作方法、阵列基板和显示面板