WO2012077617A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2012077617A1 WO2012077617A1 PCT/JP2011/078022 JP2011078022W WO2012077617A1 WO 2012077617 A1 WO2012077617 A1 WO 2012077617A1 JP 2011078022 W JP2011078022 W JP 2011078022W WO 2012077617 A1 WO2012077617 A1 WO 2012077617A1
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- gate electrode
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Definitions
- the present invention relates to a trench gate type semiconductor device and a manufacturing method thereof.
- insulated gate semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Semiconductor Field Field Effect Transistors) are widely used as switching elements that control the power supply to motors and other loads.
- IGBTs Insulated Gate Bipolar Transistors
- MOSFETs Metal Oxide Semiconductor Semiconductor Field Field Effect Transistors
- trench gate type MOSFET in which a gate electrode is embedded in a semiconductor layer (for example, Patent Documents 1 and 2 below).
- Patent Documents 1 and 2 In general, in a trench gate type MOSFET, there is a trade-off relationship between high breakdown voltage and low on-resistance.
- MOSFETs and IGBTs using wide band gap semiconductors such as silicon carbide (SiC) are attracting attention as next-generation switching elements that can achieve high breakdown voltage and low loss, and a high voltage of about 1 kV or higher. It is considered promising for application in the technical field.
- a wide band gap semiconductor there are, for example, gallium nitride (GaN) -based material, diamond and the like in addition to SiC.
- the avalanche electric field strength at the PN junction between the base region and the drift layer is equal to the breakdown electric field strength of the silicon oxide film used for the gate insulating film. For this reason, when a high voltage is applied to the MOSFET, the highest electric field is applied to the gate insulating film at the bottom of the trench in which the gate electrode is embedded, and there is a possibility that the dielectric breakdown of the gate insulating film occurs at that portion.
- Patent Documents 1 and 2 in an n-channel trench gate MOSFET, a p-type diffusion layer (protective diffusion layer) is formed at the bottom of the trench in the drift layer for the purpose of protecting the gate insulating film at the bottom of the trench of the gate electrode.
- the protective diffusion layer promotes depletion of the n-type drift layer when the MOSFET is turned off, and functions to alleviate electric field concentration at the bottom of the trench of the gate electrode.
- the protective diffusion layer is electrically connected to the base region (body region) of the MOSFET to fix the potential of the protective diffusion layer, thereby further reducing the electric field concentration at the bottom of the trench. Yes.
- Patent Document 1 the trench of the gate electrode is formed in a line shape, a low concentration p-type diffusion layer on the side surface of the longitudinal ends of the trench - extending the (p layer)
- the protective diffusion layer at the bottom of the trench and the upper base region are electrically connected through the p ⁇ layer.
- Patent Document 2 the trenches of the gate electrode are formed in a lattice pattern, and the protective diffusion layer at the bottom of the trench and the upper layer of the gate electrode pass through the gate electrode at the intersection of the gate electrode.
- a contact for connecting the source electrode is provided.
- the protective diffusion layer is electrically connected to the base region through the contact and the source electrode.
- the breakdown of the gate insulating film due to the displacement current can be prevented by reducing the resistance value between the protective diffusion layer and the base region.
- MOSFET of Patent Document 1 p extending in the longitudinal direction of the side surface of the line-shaped trenches - for a protective diffusion layer through a layer and the base region are connected, the center of the protective diffusion layers of the trench bottom The distance from the base area is long. Therefore, the resistance value between the protective diffusion layer and the base region is increased.
- the trench gate type MOSFET of Patent Document 2 has a configuration in which a contact for connecting the protective diffusion layer and the base region penetrates the gate electrode, the width of the contact is necessarily larger than the width of the trench of the gate electrode. Narrow. Therefore, when the MOSFET cell pitch, that is, the width of the trench of the gate electrode, is reduced in order to increase the current density, the contact must be thinned accordingly, and the resistance value between the protective diffusion layer and the base region is reduced. Becomes larger.
- the present invention has been made to solve the above-described problems, and prevents the gate insulating film from being destroyed due to a displacement current flowing into the protective diffusion layer at the bottom of the trench of the gate electrode at the time of turn-off. It is an object of the present invention to provide a trench gate type semiconductor device capable of narrowing the width and narrowing the cell pitch and a method of manufacturing the same.
- a semiconductor device is embedded in the semiconductor layer so as to penetrate the first conductivity type semiconductor layer, a second conductivity type base region formed on the semiconductor layer, and the base region.
- a gate electrode arranged in a lattice shape in plan view, a gate insulating film formed on the side and bottom surfaces of the gate electrode, and in contact with the gate electrode through the gate insulating film above the base region In at least one section among a plurality of sections divided by the gate electrode, the source region of the first conductivity type formed in the first conductivity type, the source electrode connected to the upper surface of the source region and the base region, the base region
- An opening formed so as to penetrate, and the semiconductor layer is formed across the bottom of the gate electrode and the bottom of the opening via the gate insulating film.
- the protective contact for connecting the protective diffusion layer and the source electrode is disposed in at least one section partitioned by the lattice-like gate electrode, the area of the protective contact is equal to that of the section. Can be secured up to Therefore, the resistance of the protective contact can be reduced, and the resistance value between the protective diffusion layer and the base region can be reduced. Therefore, the gate insulating film can be prevented from being destroyed due to the displacement current.
- the area of the protective contact is not limited by the width of the trench of the gate electrode, the resistance of the protective contact does not increase even if the cell pitch is reduced in order to increase the current density.
- FIG. 1 and 2 are diagrams showing a configuration of the semiconductor device according to the first embodiment.
- a trench gate type MOSFET which is a silicon carbide (SiC) semiconductor device is shown.
- FIG. 1 is a plan view of the MOSFET.
- FIG. 2A is a cross-sectional view taken along the line AA in FIG. 1, and shows a MOSFET cell formation region (MOSFET cell region).
- FIG. 2B is a cross-sectional view taken along the line BB in FIG. 1, and includes a contact (protective contact) formation region 20 (protective contact region) connected to the protective diffusion layer. Details of the protective contact region 20 will be described later.
- the MOSFET of the first embodiment is formed using an epitaxial substrate including an n-type SiC substrate 1 and an n-type SiC epitaxial layer 2 (semiconductor layer) grown thereon.
- a p-type base region 3 is formed on the epitaxial layer 2, and the n-type region of the epitaxial layer 2 where the base region 3 is not formed becomes the drift layer 2a.
- a trench 5 in which a gate electrode 7 is embedded is formed in the epitaxial layer 2 in the MOSFET cell region so as to penetrate the base region 3 of the epitaxial layer 2. That is, the bottom of the trench 5 reaches the drift layer 2 a below the base region 3.
- a gate insulating film 6 is provided on the bottom and side surfaces of the gate electrode 7 (inner surface of the trench 5).
- An n-type source region 4 is disposed in the vicinity of the gate electrode 7 above the base region 3 so as to be adjacent to the gate electrode 7 through the gate insulating film 6.
- a p-type protective diffusion layer 13 for preventing the above is formed.
- An interlayer insulating film 8 is formed on the upper surface of the epitaxial layer 2 so as to cover the gate electrode 7.
- a contact hole (first contact hole) reaching the source region 4 and the base region 3 is formed in the interlayer insulating film 8, and the source electrode 9 disposed on the interlayer insulating film 8 is connected to the source region through the contact hole. 4 and base region 3.
- Drain electrode 10 is formed on the lower surface of SiC substrate 1.
- the gate electrodes 7 are arranged in a lattice shape in plan view (the protective diffusion layer 13 also extends in a lattice shape as with the gate electrode 7).
- the protective diffusion layer 13 also extends in a lattice shape as with the gate electrode 7.
- each of the sections (cells) divided by the gate electrode 7 functions as a MOSFET.
- the interlayer insulating film 8 and the source electrode 9 on the epitaxial layer 2 are not shown (that is, FIG. 1 corresponds to a top view of the epitaxial layer 2).
- At least one of the sections separated by the gate electrode 7 is a protective contact region 20 for disposing a protective contact 21 that connects the protective diffusion layer 13 and the source electrode 9.
- a protective contact region 20 for disposing a protective contact 21 that connects the protective diffusion layer 13 and the source electrode 9.
- the trench 5 reaching the drift layer 2 a below the base region 3 is formed in the entire section partitioned by the gate electrode 7.
- the trench 5 is a rectangular opening, and the gate electrode 7 is formed on the outer periphery thereof.
- Interlayer insulating film 8 is formed to cover the upper surface of gate electrode 7 and the side surface facing protective contact region 20.
- a protective diffusion layer 13 is formed at the bottom of the trench 5 (rectangular opening) in the protective contact region 20 and is connected to the protective diffusion layer 13 at the bottom of the gate electrode 7 of the surrounding MOSFET cell. That is, the protective diffusion layer 13 is continuously formed at the bottom of the trench 5 across the MOSFET cell region and the protective contact region 20. Further, since the protective diffusion layer 13 extends in a lattice shape like the gate electrode 7, the protective diffusion layer 13 in the protective contact region 20 is connected to all the protective diffusion layers 13 of the surrounding MOSFET cells. .
- the source electrode 9 on the interlayer insulating film 8 also extends into the protective contact region 20.
- a contact hole (second contact hole) reaching the protective diffusion layer 13 is formed in the interlayer insulating film 8 in the protective contact region 20, and the source electrode 9 passes through the contact hole and the protective diffusion layer 13 in the protective contact region 20.
- the protective contact 21 shown in FIG. 2B is a part of the source electrode 9 extending in the protective contact region 20.
- the protective contact 21 and the gate electrode 7 are insulated by an interlayer insulating film 8 that covers the side surface of the gate electrode 7.
- the protective contact 21 in the protective contact region 20, since the trench 5 is formed in the entire section partitioned by the gate electrode 7, the protective contact 21 is adjacent to the gate electrode 7 through the interlayer insulating film 8. It will be. According to this configuration, since the area of the protective contact 21 is maximized, the resistance of the protective contact 21 can be reduced.
- At least one of the sections defined by the grid-like gate electrode 7 is provided with a protective contact 21 that connects between the source electrode 9 connected to the base region 3 and the protective diffusion layer 13.
- a protective contact region 20 is provided for installation. Therefore, the formation area of the protective contact 21 can be increased, and the resistance value of the protective contact 21 can be reduced. Therefore, the resistance value between the protective diffusion layer 13 and the base region 3 is reduced, and the gate insulating film 6 can be prevented from being destroyed due to the displacement current.
- the area of the protective contact 21 is not limited by the width of the trench 5, even if the cell pitch (the width of the trench 5) is reduced to increase the current density, the resistance of the protective contact 21 does not increase. Therefore, according to the present embodiment, it is possible to contribute to both a high breakdown voltage and a large capacity of the MOSFET.
- the protective diffusion layer 13 in the protective contact region 20 is connected to all the protective diffusion layers 13 of the surrounding MOSFET cells, at least one of the sections (cells) defined by the grid-like gate electrode 7 is used as a protective contact.
- the region 20 may be used. However, in a device having many MOSFET cells, a plurality of protective contact regions 20 may be provided so that the distance from each MOSFET cell to the protective contact region 20 does not increase. In that case, the protective contact regions 20 are preferably provided at equal intervals so that the path of the current flowing through the MOSFET cell is uniform.
- one of the centers may be the protective contact region 20 for every nine sections.
- the protective contact regions 20 are equally spaced and all the MOSFET cells are adjacent to the protective contact region 20, the resistance between the protective diffusion layer 13 and the protective contact region 20 of each MOSFET cell is reduced. Can be small.
- FIGS. 1 and 2 are process diagrams.
- (A) and (b) of these figures correspond to the cross sections of the regions corresponding to FIGS. 2 (a) and 2 (a), respectively.
- epitaxial layer 2 (semiconductor layer) is formed on SiC substrate 1.
- an n-type and low-resistance SiC substrate 1 having a 4H polytype was prepared, and an n-type drift layer 2a was epitaxially grown thereon by a chemical vapor deposition (CVD) method.
- the drift layer 2a has an impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 and a thickness of 5 to 50 ⁇ m.
- a base region 3 and a source region 4 are formed by ion-implanting a predetermined dopant into the surface of the epitaxial layer 2 (FIG. 3).
- the base region 3 is formed by ion implantation of aluminum (Al) which is a p-type impurity.
- Al aluminum
- the depth of Al ion implantation is about 0.5 to 3 ⁇ m within a range not exceeding the thickness of the epitaxial layer 2.
- the impurity concentration of Al to be implanted is higher than the n-type impurity concentration of the epitaxial layer 2.
- the region of the epitaxial layer 2 deeper than the Al implantation depth remains as the n-type drift layer 2a.
- the base region 3 may be formed by epitaxial growth. Also in this case, the impurity concentration and thickness of the base region 3 are the same as those formed by ion implantation.
- the source region 4 is formed by ion implantation of nitrogen (N), which is an n-type impurity, into the surface of the base region 3.
- N nitrogen
- the source region 4 is formed in a lattice pattern corresponding to the layout of the gate electrode 7 (trench 5) to be formed thereafter (see FIG. 1). Thereby, when the gate electrode 7 is formed, the source region 4 is disposed on both sides of the gate electrode 7.
- the ion implantation depth of N is made shallower than the thickness of the base region 3.
- the impurity concentration of N to be implanted is higher than the p-type impurity concentration of the base region 3 and is in the range of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
- a silicon oxide film layer 11 is deposited on the surface of the epitaxial layer 2, and an etching mask 12 made of a resist material is formed thereon (FIG. 4).
- the etching mask 12 is formed into a pattern in which the formation region of the trench 5 is opened by photolithography. Since the trench 5 has a lattice shape, the etching mask 12 has a matrix pattern obtained by inverting it. However, since the entirety of the protective contact region 20 is opened, the etching mask 12 has a matrix pattern in which a portion corresponding to the protective contact region 20 is missing.
- the silicon oxide film 11 is patterned by reactive ion etching (RIE) using the etching mask 12 as a mask (FIG. 5). That is, the pattern of the etching mask 12 is transferred to the silicon oxide film 11. The patterned silicon oxide film 11 becomes an etching mask for the next step.
- RIE reactive ion etching
- the trench 5 penetrating the source region 4 and the base region 3 is formed in the epitaxial layer 2 by RIE using the patterned silicon oxide film layer 11 as a mask (FIG. 6).
- the trench 5 formed in the protective contact region 20 has a rectangular shape including the entire protective contact region 20.
- the depth of the trench 5 is not less than the depth of the base region 3 and is about 0.5 to 3 ⁇ m.
- an implantation mask 15 having a pattern in which the trench 5 is opened (a part of the etching mask 12 in the form of a matrix) is formed, and p-type protection is applied to the bottom of the trench 5 by ion implantation using the mask.
- a diffusion layer 13 is formed (FIG. 7).
- Al is used as the p-type impurity.
- a (patterned) silicon oxide film 11 that is an etching mask for forming the trench 5 may be used. Thereby, simplification of the manufacturing process and cost reduction can be achieved.
- the silicon oxide film 11 is used instead of the implantation mask 15, the thickness and etching conditions of the silicon oxide film layer 11 are adjusted so that the silicon oxide film 11 having a certain thickness remains after the trench 5 is formed. There is a need to.
- annealing for activating the N and Al ions implanted in the above process is performed using a heat treatment apparatus.
- This annealing is performed in an inert gas atmosphere such as argon (Ar) gas under conditions of 1300 to 1900 ° C. and 30 seconds to 1 hour.
- the silicon oxide film to be the gate insulating film 6 may be formed by thermally oxidizing the surface of the epitaxial layer 2 or may be formed by being deposited on the epitaxial layer 2.
- the gate electrode 7 is embedded in the entire trench 5 as shown in FIG.
- the central gate electrode 7 is removed in order to secure a region for forming the protective contact 21, and only the outer peripheral portion as shown in FIG. Then, patterning or etching back is performed so that the gate electrode 7 remains.
- an interlayer insulating film 8 is formed on the entire surface of the epitaxial layer 2 by the low pressure CVD method to cover the gate electrode 7. Then, by patterning the interlayer insulating film 8, a first contact hole 81 reaching the source region 4 and the base region 3 and a second contact hole 82 reaching the protective diffusion layer 13 at the bottom of the trench 5 in the protective contact region 20 are formed. (FIG. 9).
- an electrode material such as an Al alloy is deposited on the epitaxial layer 2 to form the source electrode 9 on the interlayer insulating film 8 and in the first and second contact holes 81 and 82.
- an electrode material such as an Al alloy
- the MOSFET having the configuration shown in FIG. 1 is obtained.
- FIG. 11 is a graph showing an estimation result of the gate width density with respect to the width of the protective contact (ratio of the gate width of the entire MOSFET to the total area of the MOSFET).
- the solid line graph shows the case of the present invention
- the broken line graph shows the case of the conventional example (for example, Patent Document 2) in which the protective contact penetrates the gate electrode between the cells.
- the gate width density is reduced accordingly.
- the width of the trench 5 between the cells can be made constant regardless of the width of the protective contact 21, the gate width density can be increased as compared with the conventional example.
- the gate electrode 7 can be formed by either patterning or etchback.
- the trench 5 in the protective contact region 20 is formed in a tapered shape, if the gate electrode 7 is formed by etch back, the gate electrode 7 disposed in the trench 5 in the protective contact region 20 is completely removed. There is a fear.
- the gate electrode 7 is formed by patterning, the above problem does not occur. However, in that case, since the end of the gate electrode 7 is positioned on the upper surface of the epitaxial layer 2, the width of the gate electrode 7 is wider than the width of the trench 5. Therefore, from the viewpoint of narrowing the MOSFET cell pitch, it is more advantageous to use the gate electrode 7 by etch back.
- the gate electrode 7 disposed in the trench 5 of the protective contact region 20 is formed by patterning, and the other gate electrodes 7 (gate electrodes 7 disposed in the MOSFET cell region) are formed. , Formed by etch back.
- FIG. 12 is a cross-sectional view of the protective contact region 20 in the semiconductor device according to the second embodiment (corresponding to a cross section taken along line BB in FIG. 1).
- the configuration of the MOSFET cell region is the same as that of the first embodiment (FIG. 2A).
- the gate electrode 7 disposed in the trench 5 of the protective contact region 20 is formed by patterning a material film (for example, polysilicon) of the gate electrode 7. Therefore, as shown in FIG. 12, the ends of the gate electrode 7 and the gate insulating film 6 around the protective contact region 20 extend to the epitaxial layer 2 (that is, the ends of the gate electrode 7 and the gate insulating film 6 are (Positioned on the epitaxial layer 2).
- a material film for example, polysilicon
- the gate electrode 7 disposed in the trench 5 other than the protective contact region 20 is formed by etching back the material film (for example, polysilicon) of the gate electrode 7. Therefore, in the MOSFET cell region, the entire gate electrode 7 is buried in the trench 5 as shown in FIG.
- the present embodiment it is possible to prevent the gate electrode 7 in the trench 5 of the protective contact region 20 from disappearing without increasing the pitch of the MOSFET cells.
- FIG. 13 is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 3 of the present invention, and shows a cross section of the outermost peripheral portion of the MOSFET cell array of the semiconductor device.
- dummy cells 30 that do not function as MOSFETs are arranged so as to be adjacent to the outside of the outermost peripheral MOSFET cells.
- the dummy cell 30 is arranged so as to surround the MOSFET cell array.
- the configuration other than the outermost peripheral portion of the MOSFET cell array (including the protective contact region 20) is the same as that in the first or second embodiment.
- the dummy cell 30 has a trench 5 penetrating the base region 3 like the MOSFET cell.
- the trench 5 has a field insulating film 22 formed on the outer peripheral region of the semiconductor device. Is filled by part of.
- the trench 5 of the dummy cell 30 in which the field insulating film 22 is embedded and the trench 5 of the MOSFET cell in which the gate electrode 7 is embedded form a continuous lattice pattern in plan view. That is, the portion of the field insulating film 22 embedded in the trench 5 of the dummy cell 30 is arranged on the outer periphery of the lattice-like gate electrode 7 so as to form a lattice-like pattern together with the gate electrode 7 in plan view.
- a gate electrode 7 formed by patterning is disposed on the field insulating film 22.
- the gate electrode 7 on the field insulating film 22 is electrically connected to the MOSFET cell region and the gate electrode 7 in the protective contact region 20 in a region not shown.
- the gate electrode 7 on the field insulating film 22 is also covered with the interlayer insulating film 8, and a source electrode 9 extending from the MOSFET cell region is formed thereon.
- the source electrode 9 is connected to the base region 3 and the source region 4 of the MOSFET cell and the dummy cell 30 via contact holes formed in the interlayer insulating film 8 on the upper surface of the epitaxial layer 2.
- the gate insulating film 6 of the outermost MOSFET cell is provided. Substantially, it is not exposed at the outermost periphery of the MOSFET cell array. Therefore, the occurrence of electric field concentration in the gate insulating film 6 of the outermost MOSFET cell can be suppressed, and the gate insulating film 6 can be prevented from being broken.
- FIG. 14 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention, and shows a cross section of the outermost peripheral portion of the MOSFET cell array of the semiconductor device.
- the outermost peripheral protective contact region 40 in which the protective contact 21 is disposed is provided so as to surround the outermost MOSFET cell.
- the configuration other than the outermost peripheral portion of the MOSFET cell array (including the protective contact region 20) is the same as that in the first or second embodiment.
- a wide outermost trench 5a penetrating the base region 3 is formed in the outermost peripheral protective contact region 40.
- the outermost peripheral trench 5a is connected to the trench 5 in the MOSFET cell region and the protective contact region 20, and corresponds to the outermost peripheral portion of the lattice pattern formed by the trench 5.
- a protective diffusion layer 13 is formed at the bottom of the outermost periphery trench 5a, and is connected to the protective diffusion layer 13 in the MOSFET cell region and the protective contact region.
- a gate electrode 7 is formed on a side surface on the inner peripheral side (MOSFET cell array side) of the outermost peripheral trench 5 a via a gate insulating film 6. Further, the source region 4 of the outermost MOSFET cell is formed so as to be adjacent to the gate electrode 7 through the gate insulating film 6. Accordingly, the inner peripheral side surface of the outermost peripheral trench 5a also functions as a part of the channel of the outermost peripheral MOSFET cell.
- the outer peripheral side surface of the outermost peripheral trench 5a is covered with a part of the field insulating film 22 thicker than the gate insulating film 6 formed on the outer peripheral region of the semiconductor device, and a gate formed by patterning thereon.
- An electrode 7 is provided.
- the gate electrode 7 on the field insulating film 22 is electrically connected to the MOSFET cell region and the gate electrode 7 in the protective contact region 20 in a region not shown.
- the gate electrode 7 disposed in the outermost peripheral trench 5 a is also covered with an interlayer insulating film 8, and a source electrode 9 extending from the MOSFET cell region is formed on the interlayer insulating film 8.
- a part of the source electrode 9 is connected to the protective diffusion layer 13 at the bottom of the outermost peripheral trench 5a through a contact hole formed in the interlayer insulating film 8 in the outermost peripheral trench 5a.
- a part of the source electrode 9 extending in the outermost peripheral protective contact region 40 is buried in the contact hole reaching the protective diffusion layer 13, and that part is connected to the source electrode 9 and the protective diffusion layer 13. It is a protective contact 21 (outermost peripheral protective contact) to be connected.
- the protective contact 21 is disposed in the outermost peripheral protective contact region 40 surrounding the MOSFET cell array, the contact resistance between the protective diffusion layer 13 and the protective contact 21 can be lowered. Further, the gate insulating film 6 of the outermost MOSFET cell is not substantially exposed at the outermost periphery of the MOSFET cell array. Therefore, the occurrence of electric field concentration in the gate insulating film 6 of the outermost MOSFET cell can be suppressed, and the gate insulating film 6 can be prevented from being broken. Further, as described above, the inner peripheral side surface of the outermost peripheral trench 5a can be used as a channel of the MOSFET.
- the MOSFET having a structure in which the drift layer 2a and the substrate 1 (buffer layer) have the same conductivity type has been described.
- the drift layer 2a and the substrate 1 also have different conductivity types.
- Applicable For example, if the SiC substrate 1 is made p-type with respect to the configuration shown in FIG. 1, an IGBT configuration is obtained.
- the source region 4 and source electrode 9 of the MOSFET correspond to the emitter region and emitter electrode of the IGBT, respectively, and the drain electrode 10 of the MOSFET corresponds to the collector electrode.
- a semiconductor device formed using SiC which is one of wide band gap semiconductors, has been described.
- other wide band gap semiconductors such as gallium nitride (GaN) -based materials and diamond are used.
- the present invention can also be applied to a semiconductor device.
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Abstract
Description
図1および図2は、実施の形態1に係る半導体装置の構成を示す図である。ここでは半導体装置の一例として、炭化珪素(SiC)半導体装置であるトレンチゲート型MOSFETを示す。図1は当該MOSFETの平面図である。図2(a)は、図1のA-A線に沿った断面図であり、MOSFETセルの形成領域(MOSFETセル領域)を示している。一方、図2(b)は図1のB-B線に沿った断面図であり、保護拡散層に接続するコンタクト(保護コンタクト)の形成領域20(保護コンタクト領域)を含んでいる。保護コンタクト領域20の詳細については後述する。
実施の形態1で説明したように、ゲート電極7は、パターニングおよびエッチバックのいずれの手法でも形成できる。しかし、保護コンタクト領域20のトレンチ5がテーパー状に形成された場合、エッチバックによりゲート電極7を形成しようとすると、保護コンタクト領域20のトレンチ5内に配設されるゲート電極7が完全に除去される恐れがある。
図13は、本発明の実施の形態3に係る半導体装置の構成を示す断面図であり、当該半導体装置のMOSFETセルアレイの最外周部の断面を示している。本実施の形態では、最外周のMOSFETセルのさらに外側に隣り合うように、MOSFETとして機能しないダミーセル30を配設している。ダミーセル30は、MOSFETセルアレイを囲うように配置される。MOSFETセルアレイ(保護コンタクト領域20を含む)の最外周部以外の構成は、実施の形態1または2と同様である。
図14は、本発明の実施の形態4に係る半導体装置の構成を示す断面図であり、当該半導体装置のMOSFETセルアレイの最外周部の断面を示している。本実施の形態では、最外周のMOSFETセルの外側を囲うように、保護コンタクト21が配設される最外周保護コンタクト領域40を設けている。MOSFETセルアレイ(保護コンタクト領域20を含む)の最外周部以外の構成は、実施の形態1または2と同様である。
Claims (10)
- 第1導電型の半導体層と、
前記半導体層の上部に形成された第2導電型のベース領域と、
前記ベース領域を貫通するように前記半導体層に埋め込み形成され、平面視で格子状に配設されたゲート電極と、
前記ゲート電極の側面および底面に形成されたゲート絶縁膜と、
前記ベース領域の上部において前記ゲート絶縁膜を介して前記ゲート電極と接するように形成された第1導電型のソース領域と、
前記ソース領域および前記ベース領域の上面に接続するソース電極と、
前記ゲート電極で区切られた複数の区画のうち少なくとも1区画において、前記ベース領域を貫通するように形成された開口部と、
前記半導体層において前記ゲート絶縁膜を介した前記ゲート電極の底部および前記開口部の底部に渡って形成された第2導電型の保護拡散層と、
前記開口部を通して前記保護拡散層と前記ソース電極とを接続する保護コンタクトと、
前記保護コンタクトと前記ゲート電極との間に介在する層間絶縁膜とを備える
ことを特徴とする半導体装置。 - 前記保護コンタクトは、前記層間絶縁膜を介して前記ゲート電極に隣接している
請求項1記載の半導体装置。 - 前記開口部が配設された区画を規定する前記ゲート電極は、端部が前記半導体層の上面に位置しており、
前記開口部が配設された区画以外の区画を規定する前記ゲート電極は、全体が前記半導体層に埋め込まれている、
請求項1または請求項2記載の半導体装置。 - 前記開口部が配設された区画を除く前記複数の区画のそれぞれは、トランジスタセルであり、
前記複数の区画が配設された領域の外周に、トランジスタとして機能しないダミーセルがさらに配設され、
前記ダミーセルは、前記ベース領域を貫通するように前記半導体層に埋め込み形成された絶縁膜を備えており、
前記半導体層に埋め込み形成された前記絶縁膜は、平面視で、格子状のゲート電極の外周に、当該ゲート電極と共に格子状のパターンを形成するように配設されている
請求項1から請求項3のいずれか一項記載の半導体装置。 - 格子状に配設されたゲート電極の最外周部分は、前記ベース領域を貫通するように形成された最外周トレンチ内に形成されており、
前記最外周トレンチの内周側の側面には、前記ゲート絶縁膜を介して前記ゲート電極が形成されており、
前記最外周トレンチの外周側の側面には、フィールド絶縁膜を介して前記ゲート電極が形成されており、
前記保護拡散層は、前記最外周トレンチの底部にまで延在しており、
前記最外周トレンチの内周側の前記ゲート電極と前記最外周トレンチの外周側の前記ゲート電極との間の領域に、前記最外周トレンチの底部の前記保護拡散層と前記ソース電極とを接続する最外周保護コンタクトをさらに備える
請求項1から請求項3のいずれか一項記載の半導体装置。 - 前記半導体層は、ワイドバンドギャップ半導体である
請求項1から請求項5のいずれか一項記載の半導体装置。 - 第1導電型の半導体層を有する半導体基板を用意する工程と、
前記半導体層の上部に第2導電型のベース領域を形成する工程と、
前記ベース領域の上部に第1導電型で格子状のソース領域を形成する工程と、
前記半導体層上に少なくとも一箇所が欠けたマトリクス状のエッチングマスクを形成する工程と、
前記エッチングマスクを用いたエッチングにより、前記ソース領域および前記ベース領域を貫通する格子状のトレンチを形成すると共に、前記マトリクス状の欠けた部分に前記ソース領域および前記ベース領域を貫通する開口部を形成する工程と、
前記トレンチおよび前記開口部の底部に第2導電型の保護拡散層を形成する工程と、
前記トレンチおよび前記開口部の内面にゲート絶縁膜を形成した後、前記トレンチ内および前記開口部の外周部にゲート電極を形成する工程と、
前記ゲート電極を覆う層間絶縁膜を形成する工程と、
前記層間絶縁膜に、前記ソース領域および前記ベース領域に達する第1コンタクトホール並びに前記開口部の底の前記保護拡散層に達する第2コンタクトホールを形成する工程と、
前記層間絶縁膜上並びに前記第1および第2コンタクトホール内に電極を形成する工程とを備える
ことを特徴とする半導体装置の製造方法。 - 前記保護拡散層は、前記エッチングマスクを使用したイオン注入によって形成される
請求項7記載の半導体装置の製造方法。 - 前記ゲート電極を形成する工程において、
前記トレンチ内に形成する前記ゲート電極は、当該ゲート電極の材料膜をエッチバックすることによって形成され、
前記開口部の外周部に形成するゲート電極は、当該ゲート電極の材料膜をパターニングすることによって形成される
請求項7または請求項8記載の半導体装置の製造方法。 - 前記半導体層は、ワイドバンドギャップ半導体である
請求項7から請求項9のいずれか一項記載の半導体装置の製造方法。
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US9614029B2 (en) | 2017-04-04 |
JP6049784B2 (ja) | 2016-12-21 |
US9985093B2 (en) | 2018-05-29 |
JPWO2012077617A1 (ja) | 2014-05-19 |
JP2015128180A (ja) | 2015-07-09 |
CN103262248B (zh) | 2016-07-13 |
US20160071922A1 (en) | 2016-03-10 |
US20170162649A1 (en) | 2017-06-08 |
US20130285140A1 (en) | 2013-10-31 |
US9224860B2 (en) | 2015-12-29 |
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