CN103262248A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN103262248A
CN103262248A CN2011800594644A CN201180059464A CN103262248A CN 103262248 A CN103262248 A CN 103262248A CN 2011800594644 A CN2011800594644 A CN 2011800594644A CN 201180059464 A CN201180059464 A CN 201180059464A CN 103262248 A CN103262248 A CN 103262248A
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gate electrode
protection
groove
diffusion layer
base
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CN103262248B (zh
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香川泰宏
古川彰彦
日野史郎
渡边宽
今泉昌之
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

提供一种能够防止在关断时流入栅电极的沟槽底部的保护扩散层的位移电流所引起的栅绝缘膜的破坏，同时使单元间距变窄而提高电流密度的沟槽栅型的半导体装置。该半导体装置具备埋入到贯通基区3的沟槽5的栅电极7。栅电极7在俯视时配设为格子状，在其底部的漂移层2a形成保护扩散层13。由栅电极7划分的至少一个区段是在整体形成了沟槽5的保护触点区域20。在保护触点区域20，配设连接沟槽5的底部的保护扩散层13和源电极9的保护触点21。

Description

半导体装置及其制造方法
技术领域
本发明涉及沟槽栅型的半导体装置及其制造方法。
背景技术
在功率电子设备中，作为控制向马达等负载的供电的开关元件，广泛使用IGBT（Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管）、MOSFET（Metal Oxide Semiconductor Field EffectTransistor，金属氧化物半导体场效应晶体管）等绝缘栅型半导体装置。作为功率控制用的纵型MOSFET的一种，有在半导体层中埋入（embed）栅电极而形成的沟槽栅型MOSFET（例如下述专利文献1、2）。一般，在沟槽栅型MOSFET中，高耐压化和低导通电阻化处于相互制约的关系。
另一方面，作为能够实现高耐压以及低损失的下一代的开关元件，使用了碳化硅（SiC）等宽能带隙半导体的MOSFET、IGBT等正受到关注，很有望能应用至处理1kV左右或者其以上的高电压的技术领域。作为宽能带隙半导体，除了SiC以外，例如还有氮化镓（GaN）系材料、金刚石等。
在使用了宽能带隙半导体的沟槽栅型MOSFET中，基区与漂移层之间的PN结中的雪崩电场强度与栅绝缘膜中使用的氧化硅膜的绝缘破坏电场强度等同。因此，在对MOSFET施加了高电压时，对埋入了栅电极的沟槽底部的栅绝缘膜施加最高的电场，在该部分有可能引起栅绝缘膜的绝缘破坏。
在专利文献1、2中，提出了分别在n沟道型的沟槽栅型MOSFET中，以保护栅电极的沟槽底部的栅绝缘膜为目的，在漂移层内的沟槽底部设置p型扩散层（保护扩散层）。保护扩散层发挥在MOSFET的截止时促进n型的漂移层的耗尽化、并且缓和向栅电极的沟槽底部的电场集中的作用。在专利文献1、2中，使保护扩散层与MOSFET的基区（体区域）电连接，固定保护扩散层的电位，从而使沟槽底部的电场集中进一步缓和。
例如，在专利文献1（图3）中，栅电极的沟槽形成为线状，在该沟槽的长度方向的端部的侧面，使低浓度的p型扩散层（p--层）延伸，通过该p--层而使沟槽底部的保护扩散层和上层的基区电连接。
另外，在专利文献2（图1、2）中，栅电极的沟槽形成为格子状，在栅电极的交叉部分，设置了贯通该栅电极而连接沟槽底部的保护扩散层和栅电极的上层的源电极的触点（contact）。保护扩散层通过该触点和源电极而与基区电连接。
但是，如果对高电压进行开关的MOSFET关断（TURN OFF），则漏极电压急剧上升（例如从0V变化为几百V）。在栅电极的沟槽底部具有保护扩散层的MOSFET中，如果漏极电压急剧上升，则经由保护扩散层与漂移层之间的寄生电容，位移电流流入保护扩散层。该位移电流由保护扩散层的面积和漏极电压（V）相对时间（t）的变动（dV/dt）决定（专利文献3）。
在如专利文献1、2那样保护扩散层与基区连接了的情况下，流入到了保护扩散层的位移电流向基区流入。此时，在保护扩散层与基区之间的电阻分量中产生电压降，这也成为引起栅绝缘膜的绝缘破坏的原因。
现有技术文献
专利文献
专利文献1：日本专利4453671号公报
专利文献2：日本特开2010-109221号公报
专利文献3：国际公开WO2010/073759号公报
发明内容
发明所要解决的技术问题
关于上述位移电流所引起的栅绝缘膜的破坏，能够通过减小保护扩散层与基区之间的电阻值来防止。但是，在专利文献1的MOSFET中，由于通过在线状的沟槽的长度方向的端部侧面延伸的p--层，保护扩散层和基区连接，所以沟槽底部的保护扩散层的中心至基区的距离长。因此，保护扩散层与基区之间的电阻值变大。
另外，专利文献2的沟槽栅型MOSFET是用于连接保护扩散层和基区的触点贯通栅电极的结构，所以该触点的宽度必然地比栅电极的沟槽的宽度窄。因此，在为了增大电流密度而减小MOSFET单元的间距、即栅电极的沟槽的宽度的情况下，必须与其配合地使触点变细，保护扩散层与基区之间的电阻值变大。
本发明是为了解决以上那样的课题而完成的，其目的在于提供一种沟槽栅型的半导体装置及其制造方法，能够防止在关断时流入栅电极的沟槽底部的保护扩散层的位移电流所引起的栅绝缘膜的破坏，同时使栅电极的宽度变窄而使单元间距变窄。
解决技术问题的方案
本发明提供一种半导体装置，具备：第1导电类型的半导体层；第2导电类型的基区，形成于所述半导体层的上部；栅电极，以贯通所述基区的方式埋入所述半导体层而形成，俯视时配设为格子状；栅绝缘膜，形成于所述栅电极的侧面以及底面；第1导电类型的源区，形成为在所述基区的上部隔着所述栅绝缘膜而与所述栅电极相接；源电极，与所述源区以及所述基区的上表面连接；开口部，形成为在由所述栅电极划分的多个区段中的至少一个区段中贯通所述基区；第2导电类型的保护扩散层，在所述半导体层中遍及隔着所述栅绝缘膜的所述栅电极的底部以及所述开口部的底部形成；保护触点，通过所述开口部连接所述保护扩散层和所述源电极；以及层间绝缘膜，介于所述保护触点与所述栅电极之间。
发明的效果
根据本发明，将连接保护扩散层和源电极的保护触点配设于通过格子状的栅电极划分的至少一个区段，所以能够将保护触点的面积确保为大至与该区段等同的面积。因此，能够使保护触点低电阻化，能够减小保护扩散层与基区之间的电阻值。因此，能够防止位移电流所引起的栅绝缘膜的破坏。另外，保护触点的面积不受到栅电极的沟槽的宽度的限制，所以即使为了增大电流密度而使单元间距变窄，保护触点的电阻也不会变高。
本发明的目的、特征、情形以及优点根据以下的详细的说明和附图而更加明确。
附图说明
图1是本发明的实施方式1的半导体装置的外延层的俯视图。
图2是本发明的实施方式1的半导体装置的剖面图。
图3是示出本发明的实施方式1的半导体装置的制造方法的工序图。
图4是示出本发明的实施方式1的半导体装置的制造方法的工序图。
图5是示出本发明的实施方式1的半导体装置的制造方法的工序图。
图6是示出本发明的实施方式1的半导体装置的制造方法的工序图。
图7是示出本发明的实施方式1的半导体装置的制造方法的工序图。
图8是示出本发明的实施方式1的半导体装置的制造方法的工序图。
图9是示出本发明的实施方式1的半导体装置的制造方法的工序图。
图10是示出本发明的实施方式1的半导体装置的制造方法的工序图。
图11是示出栅宽密度相对于保护触点宽度的估计结果的曲线图。
图12是本发明的实施方式2的半导体装置的剖面图。
图13是本发明的实施方式3的半导体装置的剖面图。
图14是本发明的实施方式4的半导体装置的剖面图。
（符号说明）
1：SiC基板；2：外延层；2a：漂移层；3：基区；4：源区；5：沟槽；6：栅绝缘膜；7：栅电极；8：层间绝缘膜；9：源电极；10：漏电极；11：氧化硅膜；12：蚀刻掩模；13：保护扩散层；14：保护触点；15：注入掩模；20：保护触点区域；21：保护触点；81：第1接触孔；82：第2接触孔。
具体实施方式
<实施方式1>
图1以及图2是示出实施方式1的半导体装置的结构的图。此处，作为半导体装置的一个例子，示出作为碳化硅（SiC）半导体装置的沟槽栅型MOSFET。图1是该MOSFET的俯视图。图2（a）是沿着图1的A-A线的剖面图，示出了MOSFET单元的形成区域（MOSFET单元区域）。另一方面，图2（b）是沿着图1的B-B线的剖面图，包括与保护扩散层连接的接触（保护触点）的形成区域20（保护触点区域）。对于保护触点区域20的细节将后述。
实施方式1的MOSFET是使用由n型的SiC基板1和在其上生长的n型SiC的外延层2（半导体层）构成的外延基板而形成的。在外延层2的上部形成p型的基区3，未形成基区3的外延层2的n型区域成为漂移层2a。
首先，参照图2（a），说明MOSFET单元的结构。在MOSFET单元区域的外延层2，以贯通外延层2的基区3的方式，形成埋入栅电极7的沟槽5。即，沟槽5的底部达到基区3之下的漂移层2a。在栅电极7的底面以及侧面（沟槽5的内面）设置了栅绝缘膜6。在基区3的上部的栅电极7的附近，以隔着栅绝缘膜6与栅电极7邻接的方式，配设n型的源区4。
另外，在漂移层2a中的栅电极7（沟槽5）的底部，形成在MOSFET截止时促进漂移层2a的耗尽化、并且缓和向沟槽5的底部的电场集中而防止栅绝缘膜6的破坏的p型的保护扩散层13。
在外延层2的上表面，以覆盖栅电极7的方式，形成层间绝缘膜8。在层间绝缘膜8，形成了达到源区4以及基区3的接触孔（第1接触孔），在层间绝缘膜8上配设的源电极9通过该接触孔而与源区4以及基区3连接。漏电极10形成于SiC基板1的下表面。
如图1所示，栅电极7在俯视时配设为格子状（保护扩散层13也与栅电极7同样地延伸为格子状）。在MOSFET单元区域中，由栅电极7划分的各个区段（单元）作为MOSFET发挥功能。另外，在图1中，省略了外延层2上的层间绝缘膜8以及源电极9的图示（即，图1相当于外延层2的顶视图）。
在本发明中，由栅电极7划分的区段的至少一个作为用于配设连接保护扩散层13和源电极9的保护触点21的保护触点区域20。如图2（b）那样，在保护触点区域20中，达到基区3之下的漂移层2a的沟槽5形成于由栅电极7划分的区段的整体。
即，在保护触点区域20中，沟槽5是矩形的开口，栅电极7形成于其外周部。另外，层间绝缘膜8形成为覆盖栅电极7的上表面以及与保护触点区域20面对的侧面。
另外，在保护触点区域20的沟槽5（矩形的开口）的底部也形成了保护扩散层13，它与周围的MOSFET单元的栅电极7的底部的保护扩散层13连接。即，保护扩散层13遍及MOSFET单元区域以及保护触点区域20，连续形成在沟槽5的底部。另外，保护扩散层13与栅电极7同样地延伸为格子状，所以保护触点区域20的保护扩散层13与周围的MOSFET单元的所有保护扩散层13连接。
层间绝缘膜8上的源电极9也在保护触点区域20内延伸。在保护触点区域20内的层间绝缘膜8形成了达到保护扩散层13的接触孔（第2接触孔），源电极9通过该接触孔而与保护触点区域20的保护扩散层13连接。即，图2（b）所示的保护触点21是在保护触点区域20内延伸的源电极9的一部分。
另外，保护触点21与栅电极7之间通过覆盖栅电极7的侧面的层间绝缘膜8被绝缘。在实施方式1中，在保护触点区域20中，在由栅电极7划分的区段的整体形成沟槽5，所以保护触点21隔着层间绝缘膜8而与栅电极7邻接。根据该结构，保护触点21的面积最大限度地变宽，所以能够减小保护触点21的电阻。
在此，简单说明上述MOSFET的工作。如果对栅电极7施加了阈值电压以上的正电压，则在栅电极7的侧面的基区3（沟道区域）形成反转沟道层。该反转沟道层成为作为载流子的电子从源区4向漂移层2a流过的路径。通过反转沟道层从源区4流入漂移层2a的电子根据由漏电极10的正电压产生的电场，通过SiC基板1而到达漏电极10。其结果，MOSFET能够从漏电极10向源电极9流入电流。该状态是MOSFET的接通状态。
另一方面，在对栅电极7施加了比阈值电压低的电压时，在沟道区域中未形成反转沟道，所以在漏电极10与源电极9之间不流过电流。该状态是MOSFET的截止状态。
如上所述，在MOSFET关断时，由于漏电极10的电压急剧上升，经由保护扩散层13与漂移层2a之间的寄生电容，位移电流流入保护扩散层13。此时，在保护扩散层13与基区3之间的电阻分量产生电压降，如果它变大，则引起栅绝缘膜6的绝缘破坏。为了防止位移电流所引起的栅绝缘膜6的破坏，减小保护扩散层13与基区3之间的电阻值是有效的。
在实施方式1的MOSFET中，将由格子状的栅电极7规定的区段的至少一个作为用于配设保护触点21的保护触点区域20，该保护触点21连接与基区3连接的源电极9、和保护扩散层13之间。因此，能够增大保护触点21的形成面积，能够减小保护触点21的电阻值。因此，保护扩散层13与基区3之间的电阻值变小，能够防止位移电流所引起的栅绝缘膜6的破坏。
另外，保护触点21的面积不受到沟槽5的宽度的限制，所以即使为了增大电流密度而使单元间距（沟槽5的宽度）变窄，保护触点21的电阻也不会变高。因此，根据本实施方式，能够对MOSFET的高耐压化以及大电容化这两者作出贡献。
保护触点区域20的保护扩散层13与其周围的MOSFET单元的所有保护扩散层13连接，所以使由格子状的栅电极7规定的区段（单元）的至少一个成为保护触点区域20即可。但是，在具有大量MOSFET单元的装置中，配设多个保护触点区域20，以使各MOSFET单元至保护触点区域20的距离不会变长即可。在该情况下，等间隔地设置保护触点区域20，以使流过MOSFET单元的电流的路径变得均匀即可。
更优选为，如图1那样，针对每9个区段，使中心的一个成为保护触点区域20即可。在该情况下，保护触点区域20成为等间隔，而且所有MOSFET单元与保护触点区域20邻接，所以能够减小各MOSFET单元的保护扩散层13与保护触点区域20之间的电阻。
以下，说明图1以及图2所示的MOSFET的制造方法。图3～图10是其工序图。这些各图的（a）以及（b）分别对应于与图2（a）以及图2（a）对应的区域的剖面。
首先，在SiC基板1上形成外延层2（半导体层）。此处，准备具有4H的多型的n型且低电阻的SiC基板1，并在其上通过化学气相沉积（CVD：Chemical Vapor Deposition）法使n型的漂移层2a外延生长。漂移层2a成为1×1015cm-3～1×1017cm-3的杂质浓度、5～50μm的厚度。
接下来，通过在外延层2的表面对规定的掺杂物进行离子注入，形成基区3以及源区4（图3）。此处，通过作为p型杂质的铝（Al）的离子注入，形成基区3。关于Al的离子注入的深度，在不超过外延层2的厚度的范围内，为0.5～3μm左右。所注入的Al的杂质浓度设为比外延层2的n型杂质浓度高。此时，比Al的注入深度深的外延层2的区域残留为n型的漂移层2a。
另外，基区3也可以通过外延生长来形成。在该情况下，基区3的杂质浓度以及厚度也设为与通过离子注入而形成的情况等同。
源区4是在基区3的表面对作为n型杂质的氮（N）进行离子注入而形成的。源区4以与之后形成的栅电极7（沟槽5）的布局对应的格子状的图案形成（参照图1）。由此，在形成了栅电极7时，在栅电极7的两侧配设源区4。N的离子注入深度设为比基区3的厚度浅。所注入的N的杂质浓度设为比基区3的p型杂质浓度高，设为1×1018cm-3～1×1021cm-3的范围。
接下来，在外延层2的表面沉积1～2μm左右的氧化硅膜层11，在其上形成由抗蚀剂材料构成的蚀刻掩模12（图4）。在蚀刻掩模12，通过光刻技术，形成为沟槽5的形成区域开口了的图案。因为沟槽5是格子状，所以蚀刻掩模12成为使其反转的矩阵状的图案。但是，因为在保护触点区域20中，其整体被开口，所以蚀刻掩模12成为与保护触点区域20对应的部分缺损的矩阵状的图案。
然后，通过以蚀刻掩模12为掩模的反应离子蚀刻（RIE：ReactiveIon Etching）处理，对氧化硅膜11进行图案化（图5）。即，蚀刻掩模12的图案被转印到氧化硅膜11。图案化的氧化硅膜11成为接下来的工序的蚀刻掩模。
通过以图案化的氧化硅膜层11作为掩模的RIE，在外延层2形成贯通源区4以及基区3的沟槽5（图6）。此时，形成于保护触点区域20的沟槽5成为包括保护触点区域20的整体的矩形形状。沟槽5的深度为基区3的深度以上，设为0.5～3μm左右。
之后，形成沟槽5的部分被开口了的图案（与蚀刻掩模12同样地一部分缺损的矩阵状）的注入掩模15，通过以其为掩模的离子注入，在沟槽5的底部形成p型的保护扩散层13（图7）。此处，作为p型杂质，使用Al。另外，也可以代替注入掩模15，而使用作为沟槽5形成时的蚀刻掩模的（图案化的）氧化硅膜11。由此，能够实现制造工序的简化以及成本削减。在代替注入掩模15而使用氧化硅膜11的情况下，需要在形成了沟槽5之后，以使一定程度的厚度的氧化硅膜11残存的方式，调整氧化硅膜层11的厚度、蚀刻条件。
在去除了注入掩模15之后，使用热处理装置，进行使在上述工序中离子注入了的N以及Al活性化的退火。该退火在氩（Ar）气等惰性气体气氛中，在1300～1900℃、30秒～1小时的条件下进行。
然后，在包括沟槽5内的外延层2的整个面形成了氧化硅膜之后，通过减压CVD法沉积多晶硅，对它们进行图案化或者回蚀（etchback），从而在沟槽5内形成栅绝缘膜6以及栅电极7（图8）。成为栅绝缘膜6的氧化硅膜既可以使外延层2的表面热氧化而形成，也可以在外延层2上沉积而形成。
在MOSFET单元区域中，如图8（a）那样在沟槽5的整体埋入栅电极7。另一方面，在保护触点区域20的沟槽5（矩形的开口部），为了确保形成保护触点21的区域，去除中央部的栅电极7，以如图8（b）那样仅在外周部使栅电极7残存的方式，进行图案化或者回蚀。
接下来，通过减压CVD法，在外延层2的整个面形成层间绝缘膜8，覆盖栅电极7。然后，通过对层间绝缘膜8进行图案化，形成达到源区4以及基区3的第1接触孔81、和达到保护触点区域20的沟槽5的底部的保护扩散层13的第2接触孔82（图9）。
然后，通过在外延层2上沉积Al合金等电极材料，在层间绝缘膜8上以及第1和第2接触孔81、82内形成源电极9。在源电极9中，在保护触点区域20内延伸的部分成为保护触点21（图10）。最后，在SiC基板1的下表面对Al合金等电极材料进行沉积而形成漏电极10，从而得到图1所示的结构的MOSFET。
图11是示出栅宽密度（MOSFET整体的栅宽相对该MOSFET的总面积的比率）相对保护触点的宽度的估计结果的曲线图。在该图中，实线的曲线表示本发明的情况，虚线的曲线表示保护触点贯通单元间的栅电极的以往例（例如专利文献2）的情况。
在以往例的情况下，为了设置保护触点，需要在MOSFET单元间的栅电极内设置与保护触点的宽度和层间绝缘膜的厚度之和相当的宽度的开口，所以其开口的宽度比较大，栅宽密度变小相应量。另一方面，在本发明中，不论保护触点21的宽度如何，都能够使单元间的沟槽5的宽度成为恒定，所以能够比以往例增大栅宽密度。
<实施方式2>
如实施方式1的说明，栅电极7能够通过图案化以及回蚀中的任意一种方法来形成。但是，在保护触点区域20的沟槽5形成为锥状的情况下，如果想要通过回蚀来形成栅电极7，则在保护触点区域20的沟槽5内配设的栅电极7有可能被完全去除。
如果通过图案化形成栅电极7，则不产生上述问题。但是，在该情况下，使栅电极7的端部位于外延层2的上表面，所以栅电极7的宽度比沟槽5的宽度更宽。因此，根据使MOSFET单元的间距变窄的观点，通过回蚀栅电极7是有利的。
因此，在实施方式2中，通过图案化仅形成在保护触点区域20的沟槽5内配设的栅电极7，通过回蚀形成其以外的栅电极7（MOSFET单元区域中配设的栅电极7）。
图12是实施方式2的半导体装置中的保护触点区域20的剖面图（相当于沿着图1的B-B线的剖面）。MOSFET单元区域的结构与实施方式1（图2（a））相同。
在保护触点区域20的沟槽5内配设的栅电极7是通过对该栅电极7的材料膜（例如多晶硅）进行图案化而形成的。因此，如图12那样，成为保护触点区域20的周围的栅电极7以及栅绝缘膜6的端部延伸至外延层2上（即，栅电极7以及栅绝缘膜6的端部位于外延层2上）的结构。
另一方面，在保护触点区域20以外的沟槽5内配设的栅电极7是通过回蚀该栅电极7的材料膜（例如多晶硅）而形成的。因此，在MOSFET单元区域中，如图2（a）那样，栅电极7的整体被埋入沟槽5。
根据本实施方式，能够无需加宽MOSFET单元的间距，而防止保护触点区域20的沟槽5内的栅电极7消失。
<实施方式3>
图13是示出本发明的实施方式3的半导体装置的结构的剖面图，示出该半导体装置的MOSFET单元阵列的最外周部的剖面。在本实施方式中，以与最外周的MOSFET单元的更外侧相邻的方式，配设了不作为MOSFET发挥功能的虚设单元（dummy cell）30。虚设单元30被配置为包围MOSFET单元阵列。MOSFET单元阵列（包括保护触点区域20）的最外周部以外的结构与实施方式1或者2相同。
如图13那样，虚设单元30与MOSFET单元同样地具有贯通基区3的沟槽5，但该沟槽5内被在半导体装置的外周区域上形成的场绝缘膜22的一部分充满。埋入了场绝缘膜22的虚设单元30的沟槽5、和埋入了栅电极7的MOSFET单元的沟槽5在俯视时，形成连续的格子状的图案。即，埋入到虚设单元30的沟槽5的场绝缘膜22的部分被配设为在俯视时，在格子状的栅电极7的外周，与该栅电极7一起形成格子状的图案。
在场绝缘膜22上配设通过图案化形成的栅电极7。场绝缘膜22上的栅电极7在未图示的区域与MOSFET单元区域以及保护触点区域20的栅电极7电连接。
另外，场绝缘膜22上的栅电极7也被层间绝缘膜8覆盖，在其上形成了从MOSFET单元区域延伸的源电极9。源电极9在外延层2的上表面隔着形成于层间绝缘膜8的接触孔而与MOSFET单元以及虚设单元30各自的基区3以及源区4连接。
根据本实施方式，在最外周的MOSFET单元的更外侧配设具有由场绝缘膜22充满的沟槽5的虚设单元30，所以最外周的MOSFET单元的栅绝缘膜6实质上不会在MOSFET单元阵列的最外周露出。因此，最外周的MOSFET单元的栅绝缘膜6中的电场集中的发生被抑制，能够防止该栅绝缘膜6的破坏。
<实施方式4>
图14是示出本发明的实施方式4的半导体装置的结构的剖面图，示出该半导体装置的MOSFET单元阵列的最外周部的剖面。在本实施方式中，以包围最外周的MOSFET单元的外侧的方式，设置了配设保护触点21的最外周保护触点区域40。MOSFET单元阵列（包括保护触点区域20）的最外周部以外的结构与实施方式1或者2相同。
在最外周保护触点区域40形成贯通基区3的宽度宽的最外周沟槽5a。该最外周沟槽5a与MOSFET单元区域以及保护触点区域20的沟槽5连接，相当于沟槽5形成的格子状图案的最外周部分。
在最外周沟槽5a内配设沿着沟槽5的格子状的栅电极7的最外周部。另外，在最外周沟槽5a的底部形成了保护扩散层13，其与MOSFET单元区域以及保护触点区域的保护扩散层13连接。
在最外周沟槽5a的内周侧（MOSFET单元阵列侧）的侧面，隔着栅绝缘膜6形成栅电极7。另外，以隔着栅绝缘膜6而与栅电极7邻接的方式，形成最外周的MOSFET单元的源区4。因此，最外周沟槽5a的内周侧的侧面还作为最外周的MOSFET单元的沟道的一部分发挥功能。
另一方面，最外周沟槽5a的外周侧的侧面被形成于半导体装置的外周区域上的、比栅绝缘膜6厚的场绝缘膜22的一部分覆盖，在其上配设通过图案化形成的栅电极7。场绝缘膜22上的栅电极7在未图示的区域与MOSFET单元区域以及保护触点区域20的栅电极7电连接。
在最外周沟槽5a内配设的栅电极7也被层间绝缘膜8覆盖，在该层间绝缘膜8上形成从MOSFET单元区域延伸的源电极9。源电极9的一部分在最外周沟槽5a内经由形成于层间绝缘膜8的接触孔，而与最外周沟槽5a底部的保护扩散层13连接。换言之，在最外周保护触点区域40内延伸的源电极9的一部分埋入达到保护扩散层13的接触孔内，该部分成为连接源电极9和保护扩散层13的保护触点21（最外周保护触点）。
根据本实施方式，在包围MOSFET单元阵列的最外周保护触点区域40配设保护触点21，所以能够降低保护扩散层13与保护触点21之间的接触电阻。进而，最外周的MOSFET单元的栅绝缘膜6实质上在MOSFET单元阵列的最外周不会露出。因此，最外周的MOSFET单元的栅绝缘膜6中的电场集中的发生被抑制，能够防止该栅绝缘膜6的破坏。另外，如上所述，最外周沟槽5a的内周侧的侧面还能够用作MOSFET的沟道。
在以上的说明中，叙述了漂移层2a和基板1（缓冲层）具有相同的导电类型的构造的MOSFET，但对于漂移层2a和基板1具有不同的导电类型的构造的IGBT也能够适用。例如，如果针对图1所示的结构，使SiC基板1成为p型，则成为IGBT的结构。在该情况下，MOSFET的源区4以及源电极9分别对应于IGBT的发射极区域以及发射极电极，MOSFET的漏电极10对应于集电极电极。
另外，在各实施方式中，对于使用作为宽能带隙半导体之一的SiC形成的半导体装置进行了说明，但对于使用了例如氮化镓（GaN）类材料、金刚石等其他宽能带隙半导体的半导体装置也能够适用。
虽然详细说明了本发明，但上述说明在所有情形下仅为例示，本发明不限于此。理解的是未例示的无数的变形例是不脱离于本发明的范围而能够想到的。

Claims (10)

1.一种半导体装置，其特征在于，具备：
第1导电类型的半导体层；
第2导电类型的基区，形成于所述半导体层的上部；
栅电极，以贯通所述基区的方式埋入所述半导体层而形成，配设为俯视时的格子状；
栅绝缘膜，形成于所述栅电极的侧面以及底面；
第1导电类型的源区，形成为在所述基区的上部隔着所述栅绝缘膜而与所述栅电极相接；
源电极，与所述源区以及所述基区的上表面连接；
开口部，形成为在由所述栅电极划分的多个区段中的至少一个区段中贯通所述基区；
第2导电类型的保护扩散层，在所述半导体层中遍及隔着所述栅绝缘膜的所述栅电极的底部以及所述开口部的底部而形成；
保护触点，通过所述开口部连接所述保护扩散层和所述源电极；以及
层间绝缘膜，介于所述保护触点与所述栅电极之间。
2.根据权利要求1所述的半导体装置，其特征在于，
所述保护触点经由所述层间绝缘膜而与所述栅电极邻接。
3.根据权利要求1或者2所述的半导体装置，其特征在于，
规定配设了所述开口部的区段的所述栅电极的端部位于所述半导体层的上表面，
规定配设了所述开口部的区段以外的区段的所述栅电极的整体被埋入所述半导体层。
4.根据权利要求1至3中的任意一项所述的半导体装置，其特征在于，
除了配设了所述开口部的区段以外的所述多个区段分别是晶体管单元，
在配设了所述多个区段的区域的外周，还配设了不作为晶体管发挥功能的虚设单元，
所述虚设单元具备以贯通所述基区的方式埋入所述半导体层而形成的绝缘膜，
埋入所述半导体层而形成的所述绝缘膜被配设为在俯视时在格子状的栅电极的外周，与该栅电极一起形成格子状的图案。
5.根据权利要求1至3中的任意一项所述的半导体装置，其特征在于，
配设为格子状的栅电极的最外周部分形成于以贯通所述基区的方式形成的最外周沟槽内，
在所述最外周沟槽的内周侧的侧面，隔着所述栅绝缘膜形成了所述栅电极，
在所述最外周沟槽的外周侧的侧面，隔着场绝缘膜形成了所述栅电极，
所述保护扩散层延伸至所述最外周沟槽的底部，
在所述最外周沟槽的内周侧的所述栅电极与所述最外周沟槽的外周侧的所述栅电极之间的区域，还具备连接所述最外周沟槽的底部的所述保护扩散层和所述源电极的最外周保护触点。
6.根据权利要求1至5中的任意一项所述的半导体装置，其特征在于，
所述半导体层是宽能带隙半导体。
7.一种半导体装置的制造方法，其特征在于，具备：
准备具有第1导电类型的半导体层的半导体基板的工序；
在所述半导体层的上部形成第2导电类型的基区的工序；
在所述基区的上部形成第1导电类型的、格子状的源区的工序；
在所述半导体层上形成至少一处缺损的矩阵状的蚀刻掩模的工序；
通过使用了所述蚀刻掩模的蚀刻，形成贯通所述源区以及所述基区的格子状的沟槽，并且在所述矩阵状的缺损的部分形成贯通所述源区以及所述基区的开口部的工序；
在所述沟槽以及所述开口部的底部形成第2导电类型的保护扩散层的工序；
在所述沟槽以及所述开口部的内面形成了栅绝缘膜之后，在所述沟槽内以及所述开口部的外周部形成栅电极的工序；
形成覆盖所述栅电极的层间绝缘膜的工序；
在所述层间绝缘膜形成达到所述源区以及所述基区的第1接触孔、以及达到所述开口部的底的所述保护扩散层的第2接触孔的工序；以及
在所述层间绝缘膜上以及所述第1和第2接触孔内形成电极的工序。
8.根据权利要求7所述的半导体装置的制造方法，其特征在于，
所述保护扩散层是通过使用了所述蚀刻掩模的离子注入而形成的。
9.根据权利要求7或者8所述的半导体装置的制造方法，其特征在于，
在所述形成栅电极的工序中，
在所述沟槽内形成的所述栅电极是通过对该栅电极的材料膜进行回蚀而形成的，
在所述开口部的外周部形成的栅电极是通过对该栅电极的材料膜进行图案化而形成的。
10.根据权利要求7至9中的任意一项所述的半导体装置的制造方法，其特征在于，
所述半导体层是宽能带隙半导体。
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US20130285140A1 (en) 2013-10-31
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